BSc Thesis Abstract: Electrical characterization of microelectronic structures and materials for novel MOS structures Spyros Tsevas

Technological Educational Institute (TEI) of Piraeus

Supervised by Prof. Maria Vasilopoulou and Prof. Ε. Kyriakis-Bitzaros Abstract The increasing need for faster Integrated Circuits (ICs) has resulted in the realization of higher-speed and higher-density semiconductor devices. For the last two decades, device feature size has decreased from 1 μm down to 90 nm, increasing the working frequency of the microprocessors. However, further decrease of feature sizes to values lower than 0.1 μm has introduced certain limitations such as the interconnection delay and fluctuations in the dopant concentrations from device to device will that result in unacceptably large threshold voltage spreads. This trend is expected to necessitate the use of novel materials that can deal effectively with the challenges that arise in the nanometric scale. The purpose of this thesis was to investigate, by using electrical characterization techniques, materials that can potentially replace the traditional ones. Our focus was on two main directions. On the one hand, we investigated the use of Tungsten (W) and Copper/Tungsten (Cu/W) Metal Oxide Semiconductor (MOS) gates on thin oxides that were fabricated by a process utilizing Low Pressure CVD (LPCVD) of W that can be used with copper metallization. For Ultra Large Scale Integration (ULSI) Complementary-MOS (CMOS) devices with channel lengths below 100 nm the fluctuations in dopant concentration result in large threshold voltage spreads. This necessitated the use of intrinsic channels and of a gate material with midgap Fermi level, to facilitate its use for both p- and n-channel MOS-Field Effect Transistors (MOSFETs). W gates deposited by CVD (Chemical Vapour Deposition) are very attractive, since W offers good adhesion, a midgap work function, good conductivity and conductivity and, since it does not exhibit any undesirable interaction, such as interdiffusion, with Silicon Dioxide (SiO2), compatibility with very thin gate oxide processing. Moreover, W can also be used as barrier against Cu diffusion, allowing the use of tungsten gates or Cu/W gates in conjunction with Cu metallization, which has now fully replaced Al metallization in advanced CMOS fabrication lines. Copper gate devices would be especially useful in more specific applications such as TFT pixel drivers for active matrix liquid crystal displays (AMLCDs), where the gate lines are deposited first on the glass backplane and must be thin to ensure good step coverage by the PECVD dielectric layer; they should also be narrow in order to achieve, in combination with smaller size high mobility polysilicon TFTs (4), large pixel aperture ratios. The relatively high resistivities (> 10 μΩ cm) of the refractory metals (like molybdenum or tantalum) mostly used today for the gate bus lines result in RC propagation delays, for such narrow and thin lines, that restrict AMLCD diagonal sizes to 15-20 inches; drastic 1

reduction of the RC gate delay is needed for future large area and high resolution AMLCDs, such as 40-inch high definition television. For the purpose of this part of the thesis, MOS capacitors with W gates or Cu/W gates on thin oxides were fabricated by a process utilizing Low Pressure CVD (LPCVD) of W that can be used with copper metallization, compatible with CMOS technology, and their electrical properties are characterized. On the other hand, we examined the use of PDMS (Polydimethylsiloxane) and POSS (Polyhedral oligomeric silsesquioxane) polymers as alternative to SiO2 interlayer or interlevel dielectric materials. Both polymers were applied by spinning and cured at temperatures below 160 oC. Silicon dioxide till recently appeared to be the standard insulating material with a dielectric constant about 3.9. However, to fulfill the requirements for ULSI materials with dielectric constants lower than 3.9 (so called low-k dielectrics) are necessary. Generally speaking, a low-k material is an insulating material that exhibits weak polarization when subjected to an externally applied electric field. As a result, a capacitor with a dielectric medium of lower k will hold less electric charge at the same applied voltage or, in other words, its capacitance will be lower. There are several guidelines employed to the design of low-k materials. The most obvious one is to choose materials with chemical bonds of lower polarizability than SiO. The IC industry has already moved to materials, which exhibit less polarizable bonds such as Si-F or Si-C in order to replace Si-O bonds. Additionally, by using materials, like organic polymers, with virtually non-polar bonds such as C-C or C-H we can help out a more fundamental reduction in k values. Another approach is to minimize the moisture content in the dielectric since water has extremely polar O-H bonds and a k value close to 80. A low-k dielectric needs to be as hydrophobic as possible to prevent deterioration of its k value. Furthermore, since the air’s dielectric constant is equal to unity, dielectric materials can have lower effective k’s with the introduction of some porosity into their chemical structure. By introducing porosity, we manage to increase the free volume and as a result to decrease the density of a material. Generally, in order to create porosity in the films, the template material is thermally decomposed and the decomposition products will volatise and permeate through the main matrix during the thermal treatment. As a result, voids are created at sites occupied by the templates prior to the decomposition process. In most cases thermal treatment at high temperatures is necessary in order to render the material porous. Indeed, this is the case of spin-on glasses (SOGs). In the field of non-porous, organic materials polyimides and fluorinated polymers are the most promising candidates for use as low-k dielectrics. Such materials have received considerable attention lately. The PDMS and POSS organic materials that were selected for this study were both newly synthesized, low-k candidate polymers

Selected References Buchanan, F.R. McFeely and J.J. Yurkas, Appl. Phys. Lett. 73, 1676 (1998). Homma T, Yamaguchi R and Murao Y 1993 J. Electrochem. Soc. 140 687 Kaplan and F.M. d’Heurle, J. Electrochem. Soc. 117, 694 (1970). Kouvatsos, A.T. Voutsas, M.K. Hatalis, IEEE Trans. Electron. Dev. 43 (1996) 1399.

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Kouvatsos, D.N., V. Ioannou-Sougleridis, S. Tsevas, F. Christoforou, D. Davazoglou and C. Boukouras, “Characteristics of W and Cu/W gate MOS diodes fabricated by a process utilizing LPCVD of tungsten and copper liftoff,” Microelectronic Engineering, Volume 70, Issues 2-4, November 2003, Pages 501-505. Kouvatsos, V. Ioannou-Sougleridis, S. Tsevas, F. Christoforou, D. Davazoglou, C. Boukouras, Micr. Eng. 70 (2003 Petkov M P, Weber M H, Lynn K G, Rodbell K P and Cohen S A 1999 J. Appl. Phys. 86 3104 Shamirayan D, Abell T, Iacopi F and Maex K Materials today January 2004, p.34 Shang, M.H. White, K.W. Guarini, P. Solomon, E. Cartier, F.R. McFeely, J.J. Yurkas, W. Lee, Appl. Phys. Lett. 70 (2003) 3139. Shina K 1981 J. Vac. Sci. Technol. 19 778 Sirringhaus, S.D. Theiss, A. Kahn, S. Wagner, IEEE Electron. Dev. Lett. 18 (1997) 388. Tauber R, Lattice Press (2000) p. 793 The National Technology Roadmap for Semiconductors, Semiconductor Industry Association 2002 Tsevas, M. Vasilopoulou, D.N. Kouvatsos, T. Speliotis, D. Niarchos, “Characteristics of MOS diodes fabricated using sputter-deposited W or Cu/W films,” Microelectronic Engineering, Volume 83, Issues 4-9, April-September 2006, Pages 1434-1437. Vasilopoulou, S. Tsevas, P. Argeitis and D. Kouvatsos, “Characterization of various low-k dielectrics for possible use in applications at temperatures below 160 oC,” J. Phys.: Conf. Ser. 10, 2005, Pages 218-221. Wong and Y. Taur, Tech. Dig. Int. Electron. Devices Meet., 705 (1993). Bellas, E. Tegou, I. Raptis, E. Gogolides, P. Argitis, H. Iatrou, N. Hadjichristidis, E. Sarantopoulou, A.C. Cefalas, Evaluation of siloxane and polyhedral silsequioxane copolymers for 157 nm lihtography, J. Vac. Sci. Technol B, 20(6), p.2902 (2002) Vasilopoulou, A. Douvas, D. Kouvatsos, D. Davazoglou, Characterization of various insulators for possible use as low‐k dielectrics at temperatures below 200 oC, Microel. Rel. (2005). Bachelder T March 1988 Solid State Technol. 29 Baney R H, Itoh M, Sakakibara A and Suzuki T 1995 Chem. Rev. 95 1409

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