Full Board Design and Verification of RF Systems Based on the Three-Dimensional Field Analysis KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University Advised by Professor SungWoo Hwang

Outlines • • • •

Motivation Introduction Full Board Simulation Design and Verification of the RF Systems – CMOS RF IC – RF LPA – RF PDP

• Conclusions

KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

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I-1. Motivation

Motivation I • Multimedia Services and Products I

CPU Clock Speed [Hz]

– Intel® Microprocessor Clock Speed

10G 1G 100M 10M CPU Clock Speed [Hz] Doubling time = 2.7 Years

1M 1970

1980

1990

2000

2010

2020

Year KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

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Motivation II • Multimedia Services and Products II – Evolutions of the Communication Standards

High speed

Medium

2G/2.5G Cellular/PCS (0.8/1.8GHz)

4G (? GHz)

3G EVDO/ WCDMA (0.8/1.8/2.1GHz)

1G AMPS (0.8GHz)

PI (2.3 GHz)

Pedestrian

Y2010 WLAN (5.x GHz)

WLAN (2.4 GHz) Y1995

Y2005 Y2000

Fixed

Data rate Voice

Data

Image

Moving pictures

KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Multimedia

Dec. 2004

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Motivation III • The Requirements

1. High Operating Frequency 2. High Carrier Frequency 3. (High Level of Integration) Components and Systems

KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

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I-2. Introduction

Introduction I • Characteristics of the RF Components and Systems I Increased Guided Frequency Full Wave Analysis Electromagnetic Fields →

→

∇ × E = − jω B →

→

(Quasi) – TEM Analysis →

∇ × H = J + jω D →

∇ ⋅ D = ρv →

∇⋅B = 0

Distributed Circuits

dV = (R + jωL ) ⋅ I dz dI − = (G + jωC ) ⋅V dz −

KVL & KCL Analysis (SPICE) Lumped Circuits

V = jωLI I = jωCV V = IR

KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

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Introduction II • Characteristics of the RF Components and Systems II – Full Wave Analysis of the Complex RF System: Practicable ?

RF System Shielding Box Passive Components Pads and Bondwires Package MMIC Die SMA Connector KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

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Introduction II • Design the RF Components and Systems I

Theory-based Design and Verification

Electromagnetic Fields Effects

Technique-based Design and Verification KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

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Introduction III • Design the RF Components and Systems II 1. Theory-based Design and Verification

Z0 = E/H

Z0 = ?

• Accurate, But Hard to Apply to the Complex Structures KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

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Introduction IV • Design the RF Components and Systems III 2. Technique-based Design and Verification Trial and Error

Know-how

=0.5pF

Signal Ground

=1.0pF

• Case-by-Case KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

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Introduction V • Design the RF Components and Systems IV 3. Computer Aided Design (CAD) and Verification Theory-based Design and Verification

Electromagnetic Fields Effects

Computer Aided Design and Verification

Technique-based Design and Verification KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

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Introduction VI • Computer Aided Design and Verification – Objectives of the Simulation: Measurements (RF)

Accurately Predicting and Describing the Measurement Results Simulation of the RF Component and System

KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

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II-1. Full Board Simulation – Introduction

Full Board Simulation – Introduction I • Type of the Simulator

– Solving KVL, KCL and Node Equations • Circuit-Level Simulator – KVL and KCL: Simplified Maxwell’s Equation • System-Level Simulator – Behavioral Model

KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

General Method

• 2D/ 3D Device Simulator • 2D/ 3D Field Simulator

Dec. 2004

Complexity of Problem

– (Numerically) Solving Maxwell’s Equations

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Full Board Simulation – Introduction II • Full Board Simulation Using Only the 3D Field and Device Simulators: – No Problems ? Measurements (RF)

Accurately Predicting and Describing the Measurement Results (Numerical) Field and Device Simulation KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

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Full Board Simulation – Introduction III • Problem I: Large Size Problem – 60 inch RF PDP Panel

• Large Computational Resource • Large Simulation Time

KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

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Full Board Simulation – Introduction IV • Problem II: Simulation of the Full Board – 2.4 GHz Wireless LAN Card

• Full Board Simulation – Device Simulation – Field Simulation

KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

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Full Board Simulation – Introduction V • Full Board Simulation of the RF System I RF System, Governed by the Maxwell’s Equations

Segmentation I (Materials)

Conductor and Dielectrics

KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Conductor, Dielectrics, and Semiconductors

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Full Board Simulation – Introduction VI • Full Board Simulation of the RF System II Segmentation II (Problem Regions)

Segment #3b: Drain bias network and Transistor launcher

Segment #1: SMA-MSL (w. transition model) Segment #3a: Gate bias network and Transistor launcher

Segment #2: Uniform MSL

Segment #2: Uniform MSL

Segment #1: SMA-MSL (w. transition model)

Field Simulation S10P SNP16 File="G:\CircuitDesign_PowerGarden\ADS\Simulation libraries\20040711_mrf21030v1p1_parameter_extraction\red_multiport_segsetb_2.s10p"

L L55 L= 0.5 nH R=0.0

Term Term7 Num= 7 Z=50 Ohm

L L46 L=0.4 nH R=0.3

L L52 L=0.29 nH R=0.325

C C30 C=11 pF

Compact Circuit Modeling

R C R8 C35 R= 10 Ohm C= 2.2 uF

L L51 TLINP TLINP L=0.29 nH TL8 TL9 R=0.325 S2P Z=51.21313-1.26392e-10*freq+1.14622e-19*freq*freq-1.76927e-29*freq*freq*freq+ Z=51.21313-1.26392e-10*freq+1.14622e-19*freq*freq-1.76927e-29*freq*freq*freq+1.19269e-39*freq*freq*freq*freq-2.699e-50*freq*freq*freq*freq*freq 1.19269e-39*freq*freq*freq*freq-2.699e-50*freq*freq*freq*freq*freq SNP14 L=4.82 mm L=9.21 mm L File="G:\CircuitDesign_PowerGarden\040903_Test_board_modeling\SimulationData_HFSS\tran_msl_sma_left_10p0mm.s2p" K=3.13+1.51545e-11*freq K=3.13+ 1.51545e-11*freq L53 A=0.8 A=0.8 L=39.3 nH F=1 GHz F=1 GHz R=0.325 TanD=0.018 TanD=0.018 1

TLINP TL7 Z=50.65 Ohm L=14 mm K=1.672 A=0.001 F=1 GHz TanD=0.001

C C36 C=1.2 pF

Device Simulation

C C34 C=30 pF

2

Ref

1

10

9

8

2

7

3

6

4

L L49 L=0.29 nH R=0.325

C C33 C=5 pF

L L48 L=0.29 nH R=0.325

C C32 C=51 pF

L L47 L=0.29 nH R=0.325

C C31 C=1 nF

5

Ref

4 1

2

L L50 L L=0.29 nH L54 S4P R=0.325 SNP17 L= 0.01 nH File="G:\CircuitDesign_PowerGarden\040903_Test_board_modeling\SimulationData_HFSS\rem_red_multiport_segsetb_1.s4p" R=0.4 3

Ref

R R7 R=22 Ohm

1

TLINP TL3 Z=50.65 Ohm L=14 mm K=1.672 A=0.001 F=1 GHz TanD=0.001

2 Ref

S2P SNP13 File=

TLINP TL5 Z= L=4.82 mm K=3.13+1.51545e-11*freq A=0.8 F=1 GHz TanD=0.018

Term Term8 Num=8 Z=50 Ohm

Full Board Simulation of the RF System Dec. 2004

KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

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Full Board Simulation – Introduction VII

n tio ca ifi er V

ra ct io rE xt Pa ra m et e

d an

(S im

ul

at

io

n

Measurements (RF)

n ig es eD at ur cc A

n)

• Full Board Simulation of the RF System III

(Numerical) Field and Device Simulation

Simulation of the RF Component and System

Segmentation and Compact Circuit Modeling KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

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II-2. Full Board Simulation – Segmentation

Full Board Simulation – Segmentation I • Segmentation Method: Transition Regions I – Expected Causes of the Segmentation Error n ion o i g e g e R Z2 on R i t i s n a Tr gion e R ave Z1 W d itte m s n a Tr ave W t en Incid a ve W d e ct Refle

Impedance Discontinuity Propagating Mode Reflected Wave

Geometric Discontinuity Non-Propagating Mode Capacitive Fringing Current Crowding

KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

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Full Board Simulation – Segmentation II • Segmentation Method: Transition Regions II – Types of the Simulated Structure Type-I: Impedance Discontinuity Different Z0, But Same Geometric Parameters

Type-II: Geometric Discontinuity Same Z0, But Different Geometric Parameters

KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

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Full Board Simulation – Segmentation III • Segmentation Method: Transition Regions III – Types of the Simulation Method

Full 3D Field Simulation Reference

Full Board Simulation I (Problem Regions) Uniform + Transition + Uniform Composition

Full Board Simulation II (Materials) Uniform + Uniform Composition KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

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Full Board Simulation – Segmentation IV • Segmentation Method: Transition Regions IV – Simulation Results: Type-I 0.5mm-0.5mm: 0.6mm-0.6mm: 0.7mm-0.7mm: 0.8mm-0.8mm: 0.9mm-0.9mm: 1.0mm-1.0mm:

3.0 2.5 2.0

3D-F.B.Sim#1 3D-F.B.Sim#1 3D-F.B.Sim#1 3D-F.B.Sim#1 3D-F.B.Sim#1 3D-F.B.Sim#1

3D-F.B.Sim#2 3D-F.B.Sim#2 3D-F.B.Sim#2 3D-F.B.Sim#2 3D-F.B.Sim#2 3D-F.B.Sim#2

1.5 1.0 0.5 0.0 -0.5 -1.0 0

5

10

15

20

S21_3D - S21_F.B.Sim. [dB]

S11_3D - S11_F.B.Sim. [dB]

• 60Ω to 30Ω Transition 1.0 0.5mm-0.5mm: 0.6mm-0.6mm: 0.7mm-0.7mm: 0.8mm-0.8mm: 0.9mm-0.9mm: 1.0mm-1.0mm:

0.8 0.6 0.4

3D-F.B.Sim#1 3D-F.B.Sim#1 3D-F.B.Sim#1 3D-F.B.Sim#1 3D-F.B.Sim#1 3D-F.B.Sim#1

3D-F.B.Sim#2 3D-F.B.Sim#2 3D-F.B.Sim#2 3D-F.B.Sim#2 3D-F.B.Sim#2 3D-F.B.Sim#2

0.2 0.0 -0.2 0

5

10

15

Frequency [GHz]

Frequency [GHz]

S11 Response

S21 Response

20

• Impedance Steps Cause No Segmentation Error KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

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Full Board Simulation – Segmentation V • Segmentation Method: Transition Regions V – Simulation Results: Type-II

1.0mm-0.6mm: 1.0mm-0.7mm: 1.0mm-0.8mm: 1.0mm-0.9mm:

15 10 5

3D-F.B.Sim#1 3D-F.B.Sim#1 3D-F.B.Sim#1 3D-F.B.Sim#1

3D-F.B.Sim#2 3D-F.B.Sim#2 3D-F.B.Sim#2 3D-F.B.Sim#2

0 -5 -10 -15 -20 -25 -30 0

5

10

15

20

S21_3D - S21_F.B.Sim. [dB]

S11_3D - S11_F.B.Sim. [dB]

• 30Ω to 30Ω Transition I 1.0mm-0.6mm: 1.0mm-0.7mm: 1.0mm-0.8mm: 1.0mm-0.9mm:

1.5

3D-F.B.Sim#1 3D-F.B.Sim#1 3D-F.B.Sim#1 3D-F.B.Sim#1

3D-F.B.Sim#2 3D-F.B.Sim#2 3D-F.B.Sim#2 3D-F.B.Sim#2

1.0 0.5 0.0 -0.5 0

Frequency [GHz]

5

10

15

20

Frequency [GHz]

S11 Response S21 Response • Geometric Discontinuity Cause the Segmentation Error KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

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Full Board Simulation – Segmentation VI • Segmentation Method: Transition Regions VI – Simulation Results: Type-II

7 6 5 4 3

[dB]

8

1.2

| RMS error of |S21

RMS error of |S11

| [dB]

• 30Ω to 30Ω Transition II 1.0 0.8 0.6 0.4

2 0.2

1 0 (Ge 0.0 0.2 om etri 0.4 cal_ S te p)x (ε

r1

m] m / [1 8

6 4

-ε

r2

o ity c o el

2

0.6 0.5

0. 5

0.8 0

) [m m]

/v eq Fr

gh f li

RMS Error of the S11

t

0.0 (Ge 0.0 0.2 om etri 0.4 cal_ S te p) x (ε

r1

m] m [1 / 8

6

h lig of

4 2

0.6 0.5

-ε

r2

0.5

0.8 0

) [m m]

eq Fr

y cit o l /ve

t

RMS Error of the S21

• Electrically Small Geometric Discontinuity Cause No Segmentation Error KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

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Full Board Simulation – Segmentation VII • Segmentation Method: Conclusion – Impedance Discontinuity Only • Cause No Segmentation Error – With Transition Model: Segmentation II (Problem Regions) – Without Transition Model: Segmentation I (Materials)

– Geometric Discontinuity Only • Cause No Segmentation Error – With Transition Model

• Cause the Segmentation Error – Without Transition Model

• Electrically Small Geometric Discontinuity Cause No Segmentation Error

KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

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II-3. Full Board Simulation – DUT Model Extraction

Full Board Simulation – DUT Model Extraction I • DUT (Device Under Test) Model Extraction I – Problems • To Apply Coaxial Instruments to Non-Coaxial DUT

– An Ideal Test Fixture • Provide the Electrical Transparent Connections Between the Instruments and the DUT

Cascade® Microtech

Inter-Continental Microwave

KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

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Full Board Simulation – DUT model Extraction II • DUT Model Extraction II – Method I: Direct Measurements • Response Calibration: S21 Only • Full Two-port Calibration: SOLT and TRL

Characterization of the Test Fixture: (Calibration Standards: OPEN, LINE, SHORT,LOAD, …,) DUT with Test Fixture

KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

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Full Board Simulation – DUT Model Extraction III • DUT Model Extraction III – Method II: Modeling • Port Extension: Constant Z0 and γ • De-Embedding: Full Fixture Modeling

Modeling of the Test Fixture: No Calibration Standards DUT with Test Fixture

KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

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Full Board Simulation – DUT Model Extraction IV • DUT Model Extraction IV – De-Embedding

[S]_Left [S]_DUT

[S]_Right

[S]_DUT

S DUT ,11 = [ S ]_ DUT = ⎛ S DUT ,11 S DUT ,12 ⎞ ⎟ ⎜ ⎜ S DUT ,21 S DUT ,22 ⎟ = ⎠ ⎝

S Full ,12 S Full , 21S Right ,11 + ( S Full ,11 − S Left ,11 )( S Full , 22 S Right ,11 + S Right ,12 S Right ,12 − S Right ,11S Right , 22 )

S DUT ,12 =

S Full ,12 S Left ,12 S Right ,12 D

D S DUT , 21 =

S Full , 21S Left , 21S Right , 21 D

S DUT , 22 =

− S Full ,12 S Full , 21 S Left , 22 + ( S Full , 22 − S Right , 22 )( S Left ,12 S Left ,12 + S Full ,11 S Left , 22 − S Left ,11 S Left , 22 ) D

D = − S Full ,12 S Full , 21S Left , 22 S Right ,11 + S Full , 22 ( S Left ,12 S Left ,12 + ( S Full ,11 − S Left ,11 ) S Left , 22 ) S Right ,11 + ( S Left ,12 S Left ,12 + S Full ,11S Left , 22 − S Left ,11S Left , 22 )( S Right ,12 S Right ,12 − S Right ,11S Right , 22 ) KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

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Full Board Simulation – DUT Model Extraction V • DUT Model Extraction V – (Internal Port) Impedance Analysis Direct Measurements: Requires Coaxial Interfaces Netwo rk Ana ly zer

Modeling: Can be Performed at Any Segments KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

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II-4. Full Board Simulation – Test Fixture Model: Modeling

Full Board Simulation – Test Fixture model I • Modeling of the Test Fixture I – Simulation Parameter Extraction • SPICE Circuit Simulation gm, rds, μn, μp, λ, Cds, Cgs, Cgd,……,

Accurate I-V, C-V

• 3D Field Simulation Effective Dielectric Constant (εeff) Characteristic Impedance (Z0)

KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Accurate E/H-Fields

Dec. 2004

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Full Board Simulation – Test Fixture model II • Modeling of the Test Fixture II – Problems: Coupled RF Characteristics

Uniform SMA Region

Transition Uniform MSL Region Region

Extraction, Separately KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

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Full Board Simulation – Test Fixture model III • Main Idea – The Characteristics of the Uniform Regions have Nothing to do with Those of Transition Regions

SSSM-type Test Jig

SSSM-type test jig

LSSM-type Test Jig

LSSM-type test jig

SSLM-type Test Jig

SSLM-type test jig

LSLM-type test jig LSLM-type Test Jig KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

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Full Board Simulation – Test Fixture model IV • Simulation Parameter Extractions I – Effective Dielectric Constant (εr) Δl c Δt ⎞ 2 ⎛ v= = ⇒ ε eff = ⎜ c ⎟ Δt ε eff ⎝ Δl ⎠ SSSM-Type SSLM-Type

200

LSSM-Type LSLM-Type

150

S21 [Deg.]

100 50 0 -50 -100 -150 -200 0

1

2

3

4

5

Frequency [GHz]

VNA Measurements KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

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Full Board Simulation – Test Fixture model V • Simulation Parameter Extractions II – Characteristic Impedance (Z0) 0.2 Uniform SMA section

Z (l ) − Z 0 ΓL (l ) = L Z L (l ) + Z 0

SMA-to-microstrip line transition

0.1 0.0

ΓρL(l)

-0.1 -0.2

TDR equipment

-0.3

Uniform microstrip line section (Difference in electrical length)

-0.4

ρ of LSSM-type ρ of LSLM-type

-0.5 -0.6 33.6

34.0

34.4

34.8

35.2

35.6

36.0

Time [ns]

TDR Measurements KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

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Full Board Simulation – Test Fixture model VI • 3D Field Simulation – LSSM-type Test Jig 5mm 1.42mm 32mm 30mm

0.76mm

0.67mm 2.0mm 3.05mm

– LSLM-type Test Jig

60mm KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

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Full Board Simulation – Test Fixture model VII • Compact Circuit Modeling I – Uniform Region of the Test Fixture • ADS TLINP Model Board-level interconnects SMA connector

L [mm] ZO [Ω]

(length of

K

the thread) 50.6

14/ 32

1.67

A (@1GHz)

Tan D

0

0.001

1.2

0.018

51.21313-1.26392⋅10-10× freq+1.14622⋅10-19×freq2Microstrip line

1.76927⋅10-29×

3.13+1.515 20/ 50

freq3+1.19269⋅10-39×freq4-

45⋅1011

×freq

2.699⋅10-50×freq5

KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

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Full Board Simulation – Test Fixture model VIII • Compact Circuit Modeling II – Non-uniform Region of the Test Fixture

[S ]transition = [eγ _ left⋅l1 ] ⋅ [S ]overall ⋅ [eγ _ right⋅l2 ] Uniform region, l1 (port1) Transition region (to be modeled) Uniform region, l2 (port2)

-

KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

=

Dec. 2004

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II-5. Full Board Simulation – Test Fixture Model: Verification

Full Board Simulation – Verification I • Measured-/ 3D Field, Circuit-Level Simulated Results I – SSSM-type Test Jig 200

-10

150

-20

S11 [Deg.]

S11 [dB]

100 -30 -40 -50 -60

VNA_Measurement_|S11| 3D_Field_Simulation_|S11| ADS_Simulation_|S11|

0 -50 -100 -150

-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VNA_Measurement_ph(S11) 3D_Field_Simulation_ph(S11) -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 ADS_Simulation_ph(S11)

Frequency [GHz]

Frequency [GHz]

-70

0.1

-200

200

0.0

150

-0.1

100

S21 [dB]

-0.2

S21 [dB]

50

-0.3 -0.4 -0.5 -0.6 -0.7 -0.8

VNA_Measurement_|S21| 3D_Field_Simulation_|S21| ADS_Simulation_|S21|

-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

50 0 -50 -100 -150 -200

VNA_Measurement_ph(S21) 3D_Field_Simulation_ph(S21) -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 ADS_Simulation_ph(S11)

Frequency [GHz] KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Frequency [GHz] Dec. 2004

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Full Board Simulation – Verification II • Measured-/ 3D Field, Circuit-Level Simulated Results II – LSSM-type Test Jig 200

-10

150

-20

S11 [Deg.]

S11 [dB]

100 -30 -40 -50 -60 -70

VNA_Measurement_|S11| 3D_Field_Simulation_|S11| ADS_Simulation_|S11|

50 0 -50 -100 -150

-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VNA_Measurement_ph(S11) 3D_Field_Simulation_ph(S11) -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 ADS_Simulation_ph(S11)

Frequency [GHz]

Frequency [GHz]

-200

200

0.0

150 100

S21 [Deg.]

S21 [dB]

-0.2 -0.4 -0.6 -0.8

VNA_Measurement_|S21| 3D_Field_Simulation_|S21| ADS_Simulation_|S21|

-1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

50 0 -50 -100 -150 VNA_Measurement_ph(S21) 3D_Field_Simulation_ph(S21) -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 ADS_Simulation_ph(S21)

-200

Frequency [GHz] KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Frequency [GHz] Dec. 2004

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Full Board Simulation – Verification III • Measured-/ 3D Field, Circuit-Level Simulated Results III – SSLM-type Test Jig 200

-10

150 100

S11 [Deg.]

S11 [dB]

-20 -30 -40 -50 -60

VNA_Measurement_|S11| 3D_Field_Simulation_|S11| ADS_Simulation_|S11|

Frequency [GHz]

Frequency [GHz] 200 150 100

S21 [Deg.]

-0.4

S21 [dB]

-100 VNA_Measurement_ph(S11) 3D_Field_Simulation_ph(S11) -0.5 0.0 0.5 1.0 1.5 2.0 2.5ADS_Simulation_ph(S11) 3.0 3.5 4.0 4.5 5.0 5.5

-0.2 -0.6 -0.8 -1.0 -1.4

-50

-200

0.0

-1.2

0

-150

-70 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.2

50

VNA_Measurement_|S21| 3D_Field_Simulation_|S21| ADS_Simulation_|S21|

-1.6 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

50 0 -50 -100 -150 VNA_Measurement_ph(S21) 3D_Field_Simulation_ph(S21) -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 ADS_Simulation_ph(S21)

-200

Frequency [GHz] KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Frequency [GHz] Dec. 2004

49/97

Full Board Simulation – Verification IV • Measured-/ 3D Field, Circuit-Level Simulated Results IV – LSLM-type Test Jig -10

200

-20

150 100

S11 [Deg.]

S11 [dB]

-30 -40 -50 -60 -70

VNA_Measurement_|S11| 3D_Field_Simulation_|S11| ADS_Simulation_|S11|

Frequency [GHz]

Frequency [GHz] 200 150

-0.6 -0.8 -1.0 VNA_Measurement_|S11| 3D_Field_Simulation_|S11| ADS_Simulation_|S11|

S21 [Deg.]

100

-0.4

S21 [dB]

-100

VNA_Measurement_ph(S11) -0.5 0.0 0.5 1.0 1.5 2.0 2.53D_Field_Simulation_ph(S11) 3.0 3.5 4.0 4.5 5.0 5.5 ADS_Simulation_ph(S11)

-0.2

-1.4

-50

-200

0.0

-1.2

0

-150

-80 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.2

50

50 0 -50 -100 -150 -200

-1.6 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VNA_Measurement_ph(S21) 3D_Field_Simulation_ph(S21) -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 ADS_Simulation_ph(S21)

Frequency [GHz] KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Frequency [GHz] Dec. 2004

50/97

II-6. Full Board Simulation – Test Fixture Model: Structure Optimization

Full Board Simulation – Structure Optimization I • Structure Optimization of the Test Fixture I – Design Idea

KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

52/97

Full Board Simulation – Structure Optimization II • Structure Optimization of the Test Fixture II – Implementation

KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

53/97

Full Board Simulation – Structure Optimization III • Structure Optimization of the Test Fixture III – Experimental Verification -10 -20

S11 [dB]

-30 -40 -50 -60

Original_measurement Optimized_measurement 3D_field_simulation

-70 -80 0

1

2

3

4

Original_measurement Optimized_measurement 3D_field_simulation

0.0

5

-0.2

S21 [dB]

Frequency [GHz]

-0.4 -0.6 -0.8 -1.0 0

1

2

3

4

5

Frequency [GHz] KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

54/97

III-1. Design and Verification of the RF Systems: Introduction

Design and Verification – Introduction • Case Studies: 1. Electrically Small, But Complex RF System CMOS RF IC 2. RF System, which Requires Identical RF Components RF LPA 3. Simple, But Repeated Large Size RF System RF PDP

KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

56/97

III-2. Design and Verification of the RF Systems – CMOS RF IC

CMOS RF IC – Introduction I • RF ICs in CMOS (Year 2004) – Dominant • Relatively Relaxed Communication Standard • Wireless LAN and Bluetooth

– Making Inroads • GSM Cellular Transceivers and GPS Receiver

– Perspective • RF System-On-a-Chip in CMOS

• CAD Tools Play an Important Role in the Development of RF ICs in CMOS

KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

58/97

CMOS RF IC – Introduction II • Problem Definition: CMOS RF IC – Plentiful Active Device Models • Use the SPICE Simulator

– But, Lack of the RF Models • • • • •

Test Fixture Package Bondwire Pad On-Chip Interconnects

KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

59/97

CMOS RF IC – Full Board Simulation Using SPICE I

Bonding wires

Silicon IC's (Device models)

Board Interconnects Pads

Verification

• Obstacles to the Accurate SPICE Simulation Verification is Performed in Time- and Frequency-Domain - Time Domain Simulation in SPICE: OK - S-Parameter Simulation in SPICE: ?

Packaged

Design

Lead Frames

Full Board Simulation - Segmentation Method - Accurate RF Models: Compact Circuit Modeling

KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

60/97

CMOS RF IC – Full Board Simulation Using SPICE II • Model Parameter Extraction I – Test Fixture

0.25 mm 0.254 mm

– Package

0.65 mm

KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

61/97

CMOS RF IC – Full Board Simulation Using SPICE III • Model Parameter Extraction II – Bondwires 0.49 mm

0.025 mm 3.46 mm

– Pads

KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

100 μm

Dec. 2004

20 μm

62/97

CMOS RF IC – Full Board Simulation Using SPICE IV • Segmentation: Verifications I – Test Fixture to Package Lead I • No Geometric Discontinuity Air Wave port (90Ω) 10mm

0.4mm 0.76mm 0.02mm

Lumped Gap port (50Ω) 0.4mm

Lumped Gap port 0.4mm (50Ω)

FR4 0.86mm

3mm

15mm 4.4mm

Paddle (connected to PCB GND) KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

63/97

CMOS RF IC – Full Board Simulation Using SPICE V • Segmentation: Verifications II -5

100

-10

50

S11 [Deg.]

S11 [dB]

– Test Fixture to Package Lead II

-15 -20 -25

Full 3D Field Simulation Segmenation without Transition Model

0 -50 Full 3D Field Simulation Segmenation without Transition Model

-100

-30 0

5

10

15

0

20

5

10

15

20

Frequency [GHz]

Frequency [GHz] 0

200 150 100

S21 [Deg.]

S21 [dB]

-1 -2 -3

10

15

Frequency [GHz]

-50 -100 Full 3D Field Simulation Segmenation without Transition Model

-200

-4 5

0

-150

Full 3D Field Simulation Segmenation without Transition Model 0

50

20

0

KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

5

10

15

20

Frequency [GHz] Dec. 2004

64/97

CMOS RF IC – Full Board Simulation Using SPICE VI • Segmentation: Verifications III – Package Lead to Bondwire Transition I • Electrically Small Structure 0.4mm

Lumped Gap port (50Ω)

Wave port 0.4mm 0.18mm

0.03mm

1.12mm 0.67mm

KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

65/97

CMOS RF IC – Full Board Simulation Using SPICE VII • Segmentation: Verifications IV -5 -10 -15 -20 -25 -30 -35 -40 -45 -50

80 60

S11 [Deg.]

S11 [dB]

– Package Lead to Bondwire Transition II

Full 3D Field Simulation Segmenation without Transition Model 0

5

10

15

40 20 Full 3D Field Simulation Segmenation without Transition Model

0

20

0

5

0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8

15

20

Frequency [GHz] 20 0 -20

S21 [Deg.]

S21 [dB]

Frequency [GHz]

10

5

10

15

Frequency [GHz]

-60 -80 -100 -120

Full 3D Field Simulation Segmenation without Transition Model 0

-40

Full 3D Field Simulation Segmenation without Transition Model

-140 20

0

KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

5

10

15

Frequency [GHz]

Dec. 2004

20

66/97

CMOS RF IC – Full Board Simulation Using SPICE VIII • Full Board Simulation I – Compact Circuit Modeling: Simulation Library Package Block (n)th (Lead frame+bonding wire +pad+substrate) LLS RLS LB L= Ln ZO=Zn LLM CLC L= Ln+1 ZO=Zn+1 L= L2n ZO=Z2n

CPC

LBM

CLS

CPS

CSUB RSUB

Package Block (n+1)th

Passive Components & Active Components

Package Block (2n)th

KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

67/97

CMOS RF IC – Full Board Simulation Using SPICE IX • Full Board Simulation II – S-Parameter Simulation in SPICE Vi − Z 0 I i

• Equations

2 Z 0 Vi − Z 0 I i b Sij = i = = V Z I + aj V j + Z0 I j j 0 j 2 Z0

• Equivalent Circuits 50 Ω Port1

AC 0V

Port2

ii +

50 Ω AC 1V @ Operating Frequency

Vi ij

-

+

Vj

V = Sii

DC_bias 2Vi

AC 1

1Ω

Porti N-port network Port j V = Sij

-

PortN-1

2Vi

1Ω

PortN KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

68/97

CMOS RF IC – Experimental Verification • Measured- and Simulated Results – Down-converter for PCS Application 0 20

-5 -10

S11 [dB]

Voltage [mV]

10 0

-15

Measured Simulated

-20

10

-25

Measured IF Simulated IF

20 -200

-100

0

100

200

300

-30 400

1.4

1.6

1.8

2.0

2.2

Time [ns]

Frequency [GHz]

Time Domain

Frequency Domain

KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

2.4

2.6

69/97

III-3. Design and Verification of the RF Systems – RF Linearized Power Amplifier (LPA)

RF LPA – Introduction I • The Relationship: Rated Output Power Level, Linearity Specification and Efficiency Output Power Level Efficiency Linearity Linearity Specification Unlinearized PA

PA with Back-Off

Linearized PA

KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

71/97

RF LPA – Introduction II • Linearization of the RF Power Amplifier – Schematics of the IMD Cancellation Approach Applied RF signal @ t1 [s]

Known IMD(@t1) @t2 [s]

Nonlinear device (e.g. Amplifier, Mixer, etc.)

IMD(@t1) linearization @ t2 [s] Requires output delay time t2-t1 [s]

Linearizer (cancellation)

t

t

t

– Schematics of the IMD Prediction Approach Applied RF signal @ t1 [s]

Predicted IMD(@t1) @t2 [s]

Linearizer (prediction)

t

IMD(@t1) linearization @ t2 [s] Requires no output delay time

Nonlinear device (e.g. Amplifier, Mixer, etc.)

t

KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

t

Dec. 2004

72/97

RF LPA – Introduction III • Efficiency Degradation Factors – Output Delay Line Diameter Delay/Frequency 0.047’’ 0.0865’’ 0.141’’ 3.30 1.78 0.99 1GHz 12ns 4.23 2.56 1.46 2GHz 4.12 2.22 1.24 1GHz 15ns 5.29 3.20 1.82 2GHz Delay Line Loss in [dB]

0.25’’ 0.62 0.97 0.77 1.22

– Output Power Combiner Coupling [dB]

6

10

15

20

30

Theoretical Minimum Main 1.20 0.46 0.14 0.04 0.004 Line Insertion Loss [dB]

– High Linear Error Amplifier • Trade-off: Output Power Combiner KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

73/97

RF LPA – Proposed Analog Predistortion-type LPA I • IMD Prediction Approaches: Predistortion-type LPA – Conventional Predistortion-type LPA Pi,PD Input Pi,LPA

Predistorter

Po,PA

Po,PD Pi,PA P3rd,PD

P3rd,PA

Output Po,LPA P3rd,LPA

Drive Amplifier Main Amplifier

– Proposed Predistortion-type LPA Pi,PD Input Pi,LPA

Po,PD Pi,PA

Po,PA

P3rd,PD

P3rd,PA

Drive Amplifier Predistorter

Output Po,LPA P3rd,LPA

Main Amplifier

KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

74/97

RF LPA – Proposed Analog Predistortion-type LPA II • Block Diagram of the Proposed LPA System Note: P 3rd = 3P out – 2OIP 3 : Positive comp. : Negative comp.

Identical devices & Identical input level (@fundamental freq.)

Main Amplifier

a+G1

a

a+G1+6

3(a+G1)-2A-G1

3(a+G1)-2A

Tr.

3(a+G1)-2A Pout=a+G1

Tr.

4 way

a

Tr.

P3rd=3(a+G1)-2A

Tr.

(a+3) dBm

2 way

Tr. Path I

Drive Amplifier G=G 1 dB OIP3=A dBm

CPL

Delay

4 way

2 way

Main Amplifier G=G 1 dB OIP3=A+10log(4) dBm

ATT 2•(3(a+G1)-2A)

Path II

a

Delay

Vector Modulator

2 way

Vector Modulator

Error Amp.

Predistorter & Drive Amplifier KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

75/97

RF LPA – Design the Tr. Blocks I • Test Fixture Modeling I – Full Board Simulation Model: Segmentation Segment #3b: Drain bias network and Transistor launcher Segment #2: Uniform MSL

Segment #1: SMA-MSL (w. transition model) Segment #3a: Gate bias network and Transistor launcher

Segment #1: SMA-MSL (w. transition model)

Segment #2: Uniform MSL

KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

76/97

RF LPA – Design the Tr. Blocks II • Test Fixture Modeling II – Measured- and Simulated- Results -5

Measured |S21| Simulated |S21|

|S21| [dB]

-6

1.0j 2.0j

0.5j

-7 -8 -9

5.0j

0.2j

-10 1.8

1.9

2.0

2.1

2.2

2.3

2.4

Frequency [GHz] 0.2

0.5

1.0

2.0

5.0

-0.2j

-2.0j

-0.5j

Measured |S11| Simulated |S11| Measured |S22| -5.0j Simulated |S22| From 1.8GHz to 2.4 GHz (Normalized to 50 Ω)

-1.0j KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

77/97

RF LPA – Design the Tr. Blocks III • Experimental Verification I – S11: Conjugate Impedance Matching 1.0j 0.5j

2.0j

0.2j

5.0j

0.2

0.5

1.0

2.0

5.0

-0.2j

-5.0j

-0.5j

-2.0j -1.0j

Measured |S11|_Tr.#0 Simulated |S11|_Tr.#0 Measured |S11|_Tr.#1 Simulated |S11|_Tr.#1 Measured |S11|_Tr.#2 Simulated |S11|_Tr.#2 Measured |S11|_Tr.#3 Simulated |S11|_Tr.#3 Measured |S11|_Tr.#4 Simulated |S11|_Tr.#4 From 2.0GHz to 2.3 GHz (Normalized to 50 Ω)

RMS modeling errors of |S11|, in [dB] Tr.#0 Tr.#1 Tr.#2 Tr.#3 Tr.#4 1.934 1.704 1.949 1.155 0.663 Deviated characteristics of each Tr. from those of Tr.#0 Tr.#0 Tr.#1 Tr.#2 Tr.#3 Tr.#4 1.702 2.413 1.032 0.843

KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

78/97

RF LPA – Design the Tr. Blocks IV • Experimental Verification II – S22: Conjugate Impedance Matching 1.0j 0.5j

2.0j

0.2j

5.0j

0.2

0.5

1.0

2.0

5.0

-0.2j

-5.0j

-0.5j

Measured |S22|_Tr.#0 Simulated |S22|_Tr.#0 Measured |S22|_Tr.#1 Simulated |S22|_Tr.#1 Measured |S22|_Tr.#2 Simulated |S22|_Tr.#2 Measured |S22|_Tr.#3 Simulated |S22|_Tr.#3 Measured |S22|_Tr.#4 Simulated |S22|_Tr.#4 From 2.0GHz to 2.3 GHz (Normalized to 50 Ω)

-2.0j -1.0j

RMS modeling errors of |S22|, in [dB] Tr.#0 Tr.#1 Tr.#2 Tr.#3 Tr.#4 1.426 1.971 2.112 3.868 0.167 Deviated characteristics of each Tr. from those of Tr.#0 Tr.#0 Tr.#1 Tr.#2 Tr.#3 Tr.#4 1.491 1.746 4.767 1.387

KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

79/97

RF LPA – Design the Tr. Blocks V • Experimental Verification III – S21: Conjugate Impedance Matching Measured |S21|_Tr.#0 Measured |S21|_Tr.#1 Measured |S21|_Tr.#2 Measured |S21|_Tr.#3 Measured |S21|_Tr.#4

16 15

S21 [dB]

14

Simulated |S21|_Tr.#0 Simulated |S21|_Tr.#1 Simulated |S21|_Tr.#2 Simulated |S21|_Tr.#3 Simulated |S21|_Tr.#4

13 12 11 10 9 2.00

2.05

2.10

2.15

Frequency [GHz]

2.20

2.25

2.30

RMS modeling errors of |S21|, in [dB] Tr.#0 Tr.#1 Tr.#2 Tr.#3 Tr.#4 0.326 0.305 0.294 0.267 0.128 Deviated characteristics of each Tr. from those of Tr.#0 Tr.#0 Tr.#1 Tr.#2 Tr.#3 Tr.#4 0.274 0.311 0.435 0.250

KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

80/97

RF LPA – Implementation of the RF LPA System I • Proposed Predistortion-type LPA System

Main Amplifier

Control part

Drive Amplifier 4way Vector modulator ATT Error amp. CPL 2way

Delay

KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

81/97

RF LPA – Implementation of the RF LPA System II • Experimental Set-up Power meter

Spectrum analyzer High power attenuator Signal generator Power supply

DUT

KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

82/97

RF LPA – Experiments I • Performances I: @ Specific Power – Test Conditions • Pout = 36dBm • Two-tone Signal: fc = 2150 MHz, Δf = 1MHz • WCDMA Signal: fc = 2150 MHz, 1FA Test Model-I 64 DPCH Unlinearized Response

Linearized Response KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

83/97

RF LPA – Experiments II • Performances II: Output Dynamic Ranges – Test Conditions • Two-tone Signal: fc = 2150 MHz, Δf = 1MHz • WCDMA Signal: fc = 2150 MHz, 1FA Test Model-I 64 DPCH

– Improvements -35

Efficiency_unlinearized Efficiency_linearized

IMD3 [dBc]

-40 -45

17dB

-50

Linearity Specification

-55 -60 -65 28

30

32

34

36

38

40

-40

Unlinearized ACLR (@5MHz offset) Linearized ACLR (@5MHz offset)

-45

Efficiency [%]

12 11 10 9 8 7 6 5 4 3 2 1

ACLR [dB]

IMD3_ IMD3_

-50

Linearity Specification

-55

13dB

-60 -65 30

Pout [dBm] KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

32

34

36

38

Pout [dBm] Dec. 2004

84/97

III-4. Design and Verification of the RF Systems – RF PDP

RF PDP – Introduction I • Development of Large Size Flat Panel Displays – The Plasma Display Panel (PDP) • Most Feasible Technologies due to – Cost-effective Manufacturability – Wide Viewing Angle – Light Weight and Thinness

• But, Large DC Power Consumption

– RF Signal Biasing • The Plasma Excitation Can Occur at much Lower Electric Field • Leads to Higher Power Efficiency (≅ 3 Times) KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

86/97

RF PDP – Introduction II • Problem Definition: RF PDP – Simple Structure – Large Size RF System • Repeated Structures of the Element Pixels

– Electrical Length of the DUT Physical size

AC PDP (conventional) More than 1 m

RF PDP (newly developed) More than 1 m

Operating frequency

A few tens kHz

A few tens MHz

The order of v⋅L The order or phase difference (Φ ) : the same v assumed

104

107

MMICs (conventional) A few mm A few ~ A few tens GHz 106 ~ 107

10-3

1

10-1 – 1

KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

87/97

RF PDP – Full Board Simulation of the RF PDP I • Segmentation: Full Board Simulation Model

(Segmented) Full Board Simulation Model 4x4 cell block

4x4 cell block

4x4 cell block

4x4 cell block

28 line connector

3D Field Simulation Model LC RC CC N type connector

28 line connector 4x4 cell block

4x4 cell block

4x4 cell block

4x4 cell block

4x4 cell block

4x4 cell block

4x4 cell block

4x4 cell block

28 line connector

28 line connector 4x4 cell block

4x4 cell block

CP1

4x4 cell block

4x4 cell block CP2

ground frame RG

LG

RG

LG

KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

RG

LG

Dec. 2004

RG

LG

88/97

RF PDP – Full Board Simulation of the RF PDP II • DUT Model Electrical Parameter Extraction I – RF PDP Element Pixels I

1.00 mm

1.26 mm 1.26 mm

Front View

3D Field Simulation Model

KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

89/97

RF PDP – Full Board Simulation of the RF PDP III • DUT Model Electrical Parameter Extraction II – RF PDP Element Pixels II 4x4 cell block sustain line1

5.04 mm

KS1

5.04 mm

LSUS

sus_line 2,3,4 KC1 KS2 sus_line 3,4 KS3 sus_line 4

LSCAN

scan_line 2,3,4 KC2 scan_line 3,4 KC3

2.80 mm

KSC1 scan_line 1,2,3,4

RSUS RSCAN

KSC2

KSC3 scan_line 3,4 KSC4

scan_line 4

CSC1

CSS

sus_line 2,3,4

scan_line 1,2,3,4

CC1 CS2

scan_line 2,3,4

scan_line 4

3D Field Simulation Model

CS1

CS3 sus_line 4

scan_line 2,3,4 CC2 scan_line 3,4 CC3

scan line1

CSC2 scan_line 2,3,4 CSC3 scan_line 3,4 sustain line 4 C SC4

scan_line 4 scan_line 4

scan line 4

Extracted Compact Circuit Model

KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

90/97

RF PDP – Full Board Simulation of the RF PDP IV • DUT Model Electrical Parameter Extraction III – 28 Line Connector 28 line connector

KCNTC1

25 mm

LCNT1

RCNT1

CCNTC1 CCNT1

line 2,3,...,28 KCNTC2 line 3,4,...,28

line 1

line 2,3,...,28 CCNTC2 line 3,4,...,28

line 2

20 mm KCNTC27 line 28

CCNTC27 line 28 LCNT28

RCNT28

line 27

line 28 CCNT28

3D Field Simulation Model

Extracted Compact Circuit Model

KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

91/97

RF PDP – Full Board Simulation of the RF PDP V • DUT Model Electrical Parameter Extraction IV – RF PDP Panel Test Frame

0.8 mm

12.5 mm 13.5 mm

3D Field Simulation Model

KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

92/97

RF PDP – Experimental Verification I • Measured- and Simulated Results – Input Impedance of the RF PDP Panel 40 measured Z(real) simulated Z(real)

40

Impedance [Ω]

Impedance [Ω]

60

20

0

0 40 80

measured Z(imag.) simulated Z(imag.)

120 160

20

40 60 80 Frequency [MHz]

100

20

Real Part

KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

40 60 80 Frequency [MHz]

100

Imaginary Part

Dec. 2004

93/97

RF PDP – Experimental Verification II • Display Image With and Without the Impedance Matching Block

Without I.M.B.

KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

With I.M.B.

Dec. 2004

94/97

IV. Conclusions

Conclusions I • Full Board Simulation of the RF Systems – – – –

Based-on the Three Dimensional Field Analysis Segmentation Method Simulation Parameter Extraction Software-based De-embedding/ Impedance Analysis

– Optimization of the Test Fixture

KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

96/97

Conclusions II • Designs and Verifications of Three Distinct RF Systems Using Proposed Full Board Simulation Method – CMOS RF IC • Electrically Small, But Complex RF System • Simulation Parameter Extraction for the Full Board

– RF LPA • Full Board Simulation of the LDMOS-based Power Amplifier • Propose Wide Dynamic Range Predistortion-type LPA

– RF PDP • Simple, But Repeated Large Size RF System • Simulation Parameter Extraction for the Full Structures

KiHyuk Kim, NanoElectronics Lab, Department of Electronics Engineering, Korea University

Dec. 2004

97/97