DesignCon 2015

Ultrascale DDR4 De-emphasis and CTLE Feature Optimization with Statistical Engine for BER Specification

Penglin Niu, Xilinx Inc Fangyi Rao, Keysight Technologies Juan Wang, Xilinx Inc Gary Otonari, Keysight Technologies Nilesh Kamdar, Keysight Technologies Yong Wang, Xilinx Inc

Abstract Effects of driver de-emphasis and receiver continuous time linear equalizer (CTLE) are investigated on a FPGA DDR4 2400Mbps memory system. Results show that de-emphasis and CTLE are effective techniques to mitigate inter-symbol-interference (ISI), increase margins and improve tolerance to driver slew rate. A highly efficient yet accurate approach is presented to calculate DQ eye opening at the extremely low bit-error-rate (BER) target of 10-16 specified in DDR4. The approach employs statistical methods to directly compute eye probability distributions and BER. ISI, crosstalk and asymmetric edges are taken into account in the calculations. Timing margins are measured for design verification and optimization.

Author(s) Biography Penglin Niu is an engineer manager at Xilinx. Her team is responsible for SI/PI modeling methodology, and product SSN and PDN analysis. She was the signal integrity lead for memory interface in Xilinx before the management position. Prior to Xilinx, she worked for Intel as signal integrity lead and package design lead. She was deeply involved in high speed DDR3/DDR3L system design and high performance CPU package design. Penglin received her Ph.D. degree from University of Illinois Urbana-Champaign, and M.S. degree from University of Missouri-Rolla. Fangyi Rao is a master engineer at Keysight Technologies. He received his Ph.D. degree in theoretical physics from Northwestern University. He joined Agilent EEsof in 2006 and works on Analog/RF and SI simulation technologies in ADS and RFDE. From 2003 to 2006 he was with Cadence Design Systems, where he developed the company's Harmonic Balance technology and perturbation analysis of nonlinear circuits. Prior to 2003 he worked in the areas of EM simulation, nonlinear device modeling, and medical imaging. Juan Wang is a Staff Signal Integrity engineer at Xilinx Inc. She has been focusing on memory interface timing analysis such as DDR4/DDR3/RLDRAM3 and corresponding lab verification. Prior to Xilinx, she worked for Juniper as signal integrity engineer for more than 5 years supporting system design 10GE/XFI/XLAUI/SFI/sGMII/rGMII/PCIE/DDR3 signal integrity modeling, simulation and measurements. Juan received her MSEE from University of Missouri-Rolla and Tsinghua University. Gary Otonari is a Signal Integrity and Power Integrity engineer with 25 years of experience in high frequency and high speed hardware design. He received his BSEE from UCLA and worked at Hughes Aircraft as a satellite communications RF payload engineer. Mr. Otonari worked for EEsof Inc., GigaTest Labs and Sigrity Inc (now Cadence) in a variety of positions related to EDA, Signal Integrity and Power Integrity design. He has published numerous technical papers on measurement and simulation topics. He is currently Account Manager for Keysight Technologies in Silicon Valley.

Nilesh Kamdar is District Manager, Applications Engineering, Western Region at Keysight Technologies. He has over 15 years of experience working on high frequency and high speed digital design. He has published various technical papers on Signal and Power Integrity designs. Previously, Mr. Kamdar was Senior Applications Engineer at Agilent EEsof and before that he managed the Simulation Architecture team at Agilent EEsof. He received his Masters of Science degree in Electrical Engineering from Utah State University in 1999. Yong Wang is currently Director of Engineering at Xilinx leading Device Power and Signal Integrity Group since 2011. His team owns Xilinx product families’ SI/PI methodology development, noise/timing/jitter analysis, interface timing such as DDR4/3, and corresponding verification/characterization. Prior to joining Xilinx, Mr. Yong Wang has been system design lead and SI/PI lead of several companies such as NVIDIA, MetaRAM, HP/Intel. He led the world first 16GB and 32GB R-DIMM design, validation and production with patented memory buffer ASIC design when he was system lead with MetaRAM. In NVIDIA/HP/Intel, he provided technical leadership in the areas such as but not limited to, IA-64 system front-side parallel bus channel timing, serial link channel analysis, system level power modeling, on-die power grid noise/timing analysis and timing/noise validation in the lab. Mr. Yong Wang received his M.S. degree in Electrical Engineering from Colorado State University and B.S. degree in Electrical Engineering from Peking University. Mr. Yong Wang has 21 US patents issued and several publications including best paper rewards in conferences like EPEP and ECTC.

1. Introduction DDR4 offers a variety of advantages over DDR3, including higher data rate, reduced power consumption, Vref training and additional control of on-die termination (ODT). Meanwhile, as DDR4 speed moves upwards closer to first generation SERDES, it poses new challenges to system designers. At higher I/O speeds, system will experience higher loss; timing margin, at the same time, becomes tighter. Comparing to an 1866Mbps DDR4 system, a 2400Mbps DDR4 system’s unit interval (UI) shrinks 120ps from 536ps to 416ps. On the other hand, inter-symbol interference (ISI) has been a major contribution to signal distortion and system margin degradation. For the same channel, higher system speed will intensify ISI effect and bring more jitter into system. To demonstrate the amplified ISI effect over speed, an example DDR4 channel was setup with all crosstalk disabled, the system was then tested at 1866Mbps and 2400Mbps. Figure 1 (a) and (b) shows the write path data eye diagram of the system at 1866Mbps and 2400Mbps. It is clearly shown that ISI has significantly distorted eye opening at higher speed.

Figure 1 Example DDR4 channel Data eye diagram (a) at 1866Mbps, (b) at 2400Mbps

Comparing to ASICs, FPGA memory systems face even more challenges. FPGAs are flexible in the I/O configuration aspect; IOs are programmable to different I/O standards. The I/O standards covered by FPGAs includes: DDR3, DDR3L, DDR4, LPDDR2, LPDDR3, RLDRAM3, QDR2+, and QDR4. This has caused much larger I/O pad capacitance. And consequently slows down the signal edge rate on both write and read direction. Moreover, FPGAs are generally designed with large amount of I/Os ranging from hundreds to thousands. Figure 2 shows the package pin out of an Ultrascale vertex product. This FPGA unit is capable of driving five 72-bit memory system. FPGA package form factor, on the other hand, is limited by cost and mechanical considerations, resulting in high density signal routing and high signal to ground ratio. While ACISs system designers are pushing 2:1 to 4:1 ratios in their package design to improve signal quality, 10:1 signal to ground ratio

has been commonly used in FPGA packages. Together, high I/O count and high signal to ground ratio contribute to higher crosstalk in an FPGA I/O system, making it even more critical to control ISI channel effects.

Figure 2 Pin map of an example Ultrascale Vertex FPGA product

With challenges from higher I/O speed of DDR4 system and FPGA design, signal enhancement techniques becomes necessary to mitigate timing and electrical impairments. Equalization techniques have been widely utilized on serial buses ISI effect compensation, and have been proven to improve system timing margin. Ultrascale DDR4 system has enabled configurable transmitter (Tx) de-emphasis and multi-level active receiver (Rx) continuous time linear equalization (CTLE). As memory channel configuration can differ from user to user, channel characteristic varies greatly and therefore requiring robust equalization design. Extensive channel simulation is required for equalization optimization and channel margin quantification. Traditional bit-by-bit mode simulation is no longer possible for JEDEC DDR4 BER mask definition. In this paper, a statistical approach is first presented for accurate calculation of eye opening at arbitrarily low BER. Then optimization of de-emphasis and CTLE for a FPGA 2400Mbps DDR4 system is elaborated.

2. Statistical Approach for BER Eye Opening Calculation At high speeds it is no longer adequate to estimate the worst case margins using a limited number of bits. Moreover, random jitter and noise become non-negligible in DDR4. To address design uncertainty caused by ISI, RJ and noise, JEDEC introduces the DQ receiver compliance mask at 10-16 BER in the DDR4 spec [1]. As shown in Figure 3 the mask consists of deterministic and random portions. All DQ eyes are required to have BER lower than 10-16 inside the total mask. With the Rx mask designers can optimize design margins while maintaining sufficiently low BER, hence avoiding overly conservative designs without risking system reliability.

Figure 3 DDR4 DQ Rx mask definition.

The introduction of the Rx mask indicates a paradigm shift in the DDR design methodology from step-hold centric to BER centric. It also poses a new challenge to simulation technologies. In the traditional time-domain approach, to determine DQ eye opening at 10-16 BER, at least 1016 bits must be simulated, which is impractical. New simulation techniques are needed to design against the BER mask spec. Based on the linear time invariant assumption, the statistical approach directly computes eye probability distributions and BER without running an actual bit sequence. Results are equivalent to those of simulating infinite number of bits, allowing accurate BER prediction in a very short amount of time. With this approach, ISI and crosstalk are captured by channel step responses characterized using Spice simulations; and rise and fall edges are characterized separately to account for asymmetric pull-up and pull-down. Equal BER contours at target BER, e.g. 10-16, are plotted for DQ lines. Margins between the contour and

the Rx mask are measured. For a typical 8-bit byte lane, the simulation time is only a few minutes and scales linearly with the number of DQ lines. With its superior simulation speed, the statistical method provides a highly efficient way to verify and optimize DDR4 system performance. 2.1 Linear Superposition Method In statistical eye simulations the channel is assumed to be linear and time invariant (LTI). Consider a transmit data pattern defined by a series of rise-fall pulse edge index pair {(nr(i), nf(i))} as shown in Figure 4, where i is the pulse index, nr(i) the bit index of the i-th pulse’s rise edge, and nf(i) the bit index of the i-th pulse’s fall edge. In a LTI channel, the output voltage, v(t), can be calculated from the superposition of channel step responses as [2]





v(t )   R[t  nr (i)  T   (nr (i))]  F[t  n f (i)  T   (n f (i))]  v0

(1)

i

where R(t) is the rise edge step response, F(t) the fall edge step response, T the unit interval (UI), v0 a constantand (n) the transmit jitter at the n-th bit. The Tx jitter consists of clock duty-cycle-distortion (DCD), data DCD, periodic jitter (PJ) and random jitter (RJ) and is modeled as 𝜏(𝑛𝑟 ) = − 𝜏(𝑛𝑓 ) =

𝑑𝑎𝑡𝑎 𝐷𝐶𝐷𝑝𝑝

2

𝑑𝑎𝑡𝑎 𝐷𝐶𝐷𝑝𝑝

2

− (−1)𝑛𝑟

− (−1)𝑛𝑓

𝑐𝑙𝑘 𝐷𝐶𝐷𝑝𝑝

2

𝑐𝑙𝑘 𝐷𝐶𝐷𝑝𝑝

2

+ 𝐴𝑠𝑖𝑛(2𝜋𝑓𝑛𝑟 𝑇 + 𝜙) + 𝜌(𝑛𝑟 )

(2.1)

+ 𝐴𝑠𝑖𝑛(2𝜋𝑓𝑛𝑓 𝑇 + 𝜙) + 𝜌(𝑛𝑓 )

(2.2)

clk where DCDdata pp is the peak-to-peak data DCD, DCDpp the peak-to-peak clock DCD, A the

PJ amplitude, f the PJ frequency, the PJ phase offset, and (n) the uncorrelated RJ at the nth bit.

i th pulse 0

1

1

nr (i)T

n f (i)T

 (nr (i))

0

0

1

0

1

0 ideal edge

 (n f (i))

Figure 4 Transmitter jitter model used in statistical eye probability calculation.

In a DQ line whose step responses settle after M UIs, the output at time t depends on the pattern of M bits around t, and there are 2M possible patterns. For the m-th pattern, the output is





v ( m) (t )   R[t  nr( m) (i)  T   (nr( m) (i))]  F[t  n (fm) (i)  T   (n (fm) (i))]  v0

(3)

i

(m)

(m)

where nr (i) and nf pattern, respectively.

(i) denote rise and fall edge bit indices of the i-th pulse in the m-th

It should be pointed out that effects of Tx de-emphasis and Rx CTLE can be included by applying the equalizations to step responses R(t) and F(t). 2.2 Statistical Eye Probability Calculation Given an independent random variable x with probability density function (PDF) p(x), the PDF of a dependent variable y=f(x) is given by 𝑝(𝑥)

𝑝(𝑦) = 𝑑𝑦/𝑑𝑥

(4)

Equation 4 can be rewritten into a more general form. ∞

𝑝(𝑦) = ∫−∞ 𝑝(𝑥)𝛿[𝑦 − 𝑓(𝑥)]𝑑𝑥

(5)

where  is the Dirac delta function. For discrete random variable q, eq. 5 yields

𝑝(𝑦) = ∑𝑖 𝑃(𝑞𝑖 )𝛿[𝑦 − 𝑓(𝑞𝑖 )]

(6)

where {qi} are the discrete values of q and P(qi) the probability of q at qi. For multiple independent variables x1,…,xn with PDF p(x1,…,xn) and dependent variable y=f(x1,…,xn), eq. 5 becomes ∞

∞

𝑝(𝑦) = ∫−∞ … ∫−∞ 𝑝(𝑥1 , … , 𝑥𝑛 )𝛿[𝑦 − 𝑓(𝑥1 , … , 𝑥𝑛 )] 𝑑𝑥1 … 𝑑𝑥𝑛

(7)

Equation 7 can be applied to calculate the channel output PDF with the presence of RJ. Combining eq. 3 and eq. 7 yields the PDF of the m-th pattern as p ( m) (v, t )    [v  v ( m) (t )]   g[  (nr( m) (i))]  g[ (n (fm) (i))]  d (nr( m) (i))  d (n (fm) (i))

(8)

i

where g() is the RJ PDF, which is assumed to be a Gaussian in simulation. The output eye PDF is given by averaging over all patterns and all PJ phases. 1 p(v, t )  2



2

0

1 d M 2

2M

p m1

( m)

(v, t )

(9)

Note that in eq. 8 the Tx jitter affects the output distribution through channel step responses and its effect is directly handled in the PDF calculation instead of being added to the final eye in post-processing by PDF convolution. As a result, channel modulation and amplification on Tx jitter are taken into account [3-5]. A brute-force evaluation of eq. 8 and eq. 9 is impractical as the computation cost is in the order of O(2M). To overcome the complexity, an efficient algorithm is employed to carry out the computations, and the cost scales linearly with M [2,6]. The calculation is rigorous and without such approximation as step response linearization or low probability extrapolation, yielding accurate eye distributions at any BER level. According to the JEDEC Spec [1], Rx jitter and noise are accounted for in the mask as shown in Figure 2. However, extra Rx jitter, if needed, can be added by convolving the jitter PDF with p(v,t) along the time axis. Similarly, extra Rx noise, if needed, can be included by convolving the noise PDF with p(v,t) along the voltage axis. Crosstalk is treated as additive noise to the victim signal. Equations 8 and 9 can be used to compute crosstalk noise PDFs with step responses from aggressors to the victim. The crosstalk effect on the victim eye is calculated by convolving the victim PDF, pvictim, with crosstalk PDFs, p(i)xtlk, along the voltage axis. (1) ( 2) (n) p(v, t )   pvictim (v  v1  v2   vn , t ) p xtlk (v1 , t ) p xtlk (v2 , t )  p xtlk (vn , t )dv1dv2 dvn

(10)

2.3 Timing and Voltage Margin Measurement From eye probability distributions the equal BER contour at target BER is constructed, and its margins against the Rx mask is measured at each mask corner as demonstrated in Figure 5. In addition, to capture ring back, minimum voltage margins along upper and lower mask edges are computed.

voltage margin

minimum voltage margin

equal BER contour

timing margin Rx mask

minimum voltage margin

Figure 5 Timing and voltage margin measurements against Rx mask.

3. Equalization Optimization for a FPGA 2400Mbps DDR4 System With the statistical DDR4 simulation engine, large amount of quantification and optimization simulation can be carried out in a relatively short period of time, enabling effective system design. For FPGAs, user configuration is versatile, thus system design optimization has to cover a large range of design space. This section will focus on optimization of FPGA DDR4 equalizations. 3.1 CTLE Optimization The idealized CTLE works by boosting energy in frequency that was attenuated by the channel. The design target is to compensate the channel ISI loss to restore waveform distortion. A generalized active CTLE topology and design parameters are shown in Figure 6 [7]. The CTLE parameters are zero (fz), first pole (fp1), second pole (fp2), dc gain (Gain_dc), and peaking. In the statistical engine, CTLE is modeled as a pole-zero mathematical function with four independent parameters: fz, fp1, fp2, and Gain_dc. (s w_zero) (s w_pole1)( s  w _ pole 2) w_pole1 * w _ pole 2 c  Gain _ dc w_zero H CTLE (s)  c

(11)

Figure 6 Generalized active CTLE schematic and parameters [7]

For design optimization, design parameters are swept for sensitivity study within the design limits. As one of the most critical parameter, fz is first studied on two channels. Figure 7 shows the eye width response to CTLE zero frequency for two different package designs. From the study, even though the absolute eye width is different between the two package designs, the two systems showed similar response trend to CTLE. As the zero frequency increases from 100Mhz to 300Mhz, system margin increases very fast with the zero frequency; from 300Mhz to 600Mhz, margin increase slowly with zero frequency; while after 600Mhz, system margin saturates with increased zero frequency.

Figure 7 BER 10-16 eye width from CTLE zero frequency sweep for two difference package designs

Next, by holding the fz at fixed value, fp1, fp2, and Gain_dc are swept for their timing margin sensitivity. Figure 8 (a) and (b) shows eye width surface plot from fp1 and Gain_dc at different bandwidth (fp2).

Figure 8 (a) BER 10-16 eye width from fp1 and gain_dc at 4.5GHz bandwidth (fp2)

Figure 8 (b) BER 10-16 eye width from fp1 and gain_dc at 6GHz bandwidth (fp2)

At both bandwidth levels, fp1 shows less sensitivity to the eye width; while dc gain value has higher impact on the eye opening. Based on the CTLE parameter sensitivity study and system timing requirement, design range for each parameter can be identified and used for implementation. Four levels of CTLE design was derived from circuit implementation.

Each level of CTLE was then separately plugged into DDR4 channel simulation; the best performed setting is recommended for the design space. However, all four level of CTLE will be available for customer configuration. This is to ensure that a robust solution can be available for the customer whose design falls outside of the recommended design space. Figure 9 shows a FPGA 2400Mbps DDR4 read path statistical eye diagram of the worst case channel with and without optimized CTLE at 10-16 BER. Without CTLE, channel loss, ISI, and crosstalk have caused a small eye opening at the receiver end. With the implementation of optimized CTLE, significant improvement on eye opening is achieved. Over 70ps margin improvement from CTLE has been observed in various DDR4 channel study, which has proven CTLE as an important enabler for FPGA DDR4 high speed system.

Figure 9 Eye diagram of with and without optimized CTLE

3.2 De-emphasis Optimization Another equalization feature that has been commonly used on serial buses is transmitter deemphasis. De-emphasis can mitigate ISI effect by suppressing low frequency component at transmitter. When a bit transition ‘1-0’ or ‘0-1’ happens, the voltage swing is kept at the regular level; while in a continuous bit sequence ‘111’ or ‘000’, the voltage swing starting the second continuous bit is reduced [8]. Figure 10 shows the output waveform of a DDR4 2400Mbps driver with one tap de-emphasis. De-emphasis dB level is defined as 20*log(Vde/Vpre).

Figure 10 One tap DDR4 de-emphasis waveform

As single ended signals, DDR4 de-emphasis is designed differently from serial bus deemphasis. DDR4 driver output high and low levels are a function of both driver strength and on die termination (ODT) value. In order to reduce the swing on the second consecutive bit, dedicated de-emphasis branch is needed for both pull up and pull down transition. However, the de-emphasis strength, dB level, will not change with ODT setting; it is fully determined by driver design. In the statistical simulation, DDR de-emphasis is incorporated as a mathematical modeled with dB as the variable. Channel response varies with channel topology. Thus, different channel will respond differently to the de-emphasis. To best utilize the benefit of the equalization, de-emphasis dB level need to be optimized. First, the worst case channel is identified from the design space. As slower driver slew rate has been a major contribution to the FPGA DDR4 write path margin degradation, optimization analysis is carried out by sweeping driver rise time and de-emphasis strength. Figure 11 shows the BER eye width of a DDR4 2400Mbps system from driver rise time and de-emphasis strength. From the plot, for some rise time, multiple de-emphasis strength will help to create equal sized eye opening. Relationship between eye width and de-emphasis strength is not pure linearly increasing. Based on the study, the optimal de-emphasis strength range can be identified within the driver rise time range and sent to circuit team for implementation. The optimal strength is then plugged back into simulation for margin improvement verification in the design space.

Figure 11 BER 10-16 eye width from Tx rise time and de-emphasis post cursor sweep

Figure 12 shows an example FPGA DDR4 2400Mbps system write eye width with and without De-emphasis. The measured statistical 10-16 BER eye width at Vref +/-68mV has 1020ps improvement with de-emphasis enabled.

Figure 12 DDR4 2400Mpbs system write eye width with and and without de-emphasis

4. Conclusion In this paper, a statistical simulation engine is introduced for designing DDR4 system to JEDEC 10-16 BER target. The approach employs statistical methods to directly compute eye probability distributions and BER. ISI, crosstalk and asymmetric edges are taken into account in the calculations. With the approach, Effects of driver de-emphasis and receiver continuous time linear equalizer (CTLE) on DDR4 timing at BER target of 10-16 are investigated. It is clearly shown that de-emphasis and CTLE are effective techniques to mitigate jitter and achieve DDR4 design target after optimization.

REFERENCE [1] JEDEC DDR4 Standard, Sept. 2012. [2] F. Rao, V. Borich, H. Abebe and M. Yan, “Rigorous modeling of transmit jitter for accurate and efficient statistical eye simulation,” IEC DesignCon, Feb. 2010. [3] S. Chaudhuri, W. Anderson, J. McCall, and S. Dabrai, “Jitter amplification characterization of passive clock channels at 6.4 and 9.6 Gb/s,” Proc. IEEE 15th Topical Meeting on Electric Performance of Electronic Packaging, Scottsdale, AZ, Oct. 2006, pp. 21-24. [4] C. Madden, S. Chang, D. Oh and C. Yuan, “Jitter Amplification Considerations for PCB Clock Channel Design,” IEEE 16th Topical Meeting on Electr. Performance Electron. Packag., Atlanta, GA, pp. 135-138, Oct. 2007. [5] F. Rao and S. Hindi, “Frequency domain analysis of jitter amplification in clock channels,” Proc. IEEE 21th Topical Meeting on Electric Performance of Electronic Packaging, Tempe, AZ, Oct. 2012, pp. 51-54. [6] Casper, M. Haycock, R. Mooney, “An accurate and efficient analysis method for multiGb/s chip-to-chip signaling schemes,” VLSI Circuit Symposium, pp. 54-57, June 2002. [7] S. Gondi and B. Razavi, “Equalization and clock and data recovery techniques for 10Gb/s CMOS serial-link Receivers,” IEEE J. solid-state circuits, Vol. 42, No. 9, Sept. 2007. [8] Equalization for High-Speed Serial Interfaces in Xilinx 7 Series FPGA Transceivers, http://www.xilinx.com/support/documentation/white_papers/wp419-7Series-XCVREqualization.pdf