Signal Integrity Q&A Collection using Keysight ADS

Lin, Ming Chih Application Engineer, Taiwan Oct, 2014

Resources EEsof EDA Official Website

Signal Integrity Blog

ADS Tips Website

Signal Integrity Document Library

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Table of Contents Part 1 Fundamental SI Matrix 001- I am new to SI simulation. How to start learning SI simulation? 002- What is difference between SERDES and DDR in SI simulation and analysis? 003- What SI analysis approaches does ADS support? 004- What is the difference between pre-simulation and post-simulation? 005- What kind of circuit simulator & EM solver supported by ADS for SI analysis?

ADS Platform 006- What are benefits of ADS platform for SI design and analysis? 007- How to make a complex schematic readable? 008- What is “DesignGuide” and what it can help in signal integrity analysis? 009- What are benefits of ADS data display?

Part 2 Design Cycle 010- What is a “Signal Integrity Design Cycle”?

Modeling IO Modeling 011- How to import an HSPICE netlist of IO Buffer for SI simulation? 012- How to build SERDES transmitter and receiver Algorithmic Model Interface (AMI) models with SystemVue? 013- How to set up IBIS (Input/Output Buffer Information Specification) models for SI simulation in ADS? Channel Modeling 014- Could you explain how to model high speed channel? And what I have to pay attention to when modeling a channel? 015- Which components in ADS are used in channel modeling for signal integrity design and analysis? 016- How to design a transmission line in ADS? 017- How to design controlled impedance vias with Via Drawing Utility? 018- What is current return path of a transmission line? 019- How to build a measurement-based channel model? 020- What is “broadband SPICE model” and how to generate it?

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EM Modeling 021- What structures in a transmission line cause impedance mismatch? 022- How to Import a PCB layout into ADS layout editor 023- How to perform an Electromagnetic (EM) simulation within ADS? 024- How to define pins and ports in ADS momentum? 025- How to extract an RLC equivalent circuit of a package from S parameters? 026- How to extract S parameters of a high speed connector in EMPro? 027- How to export EMPro simulation results to ADS for SI simulation?

Simulation 028- What is the benefit of S parameter simulation? And what components are specific for S parameter simulation? 029- What components in ADS are used for Transient analysis? 030- What are benefits of ChannelSim? What components in ADS are compatible with ChannelSim? 031- How to set up bit sequence in ADS source components? 032- How to build an optimal and robust high speed digital design? 033- How to perform batch simulation efficiently with Batch Simulation controller? 034- How to examine performance of multi-channels efficiently? 035- How to calculate insertion loss, return loss and crosstalk of differential pairs in mixed mode S parameters?

Analyses 036- Does ADS have signal analyses like those in oscilloscopes? 037- Keysight ENA option TDR is used to convert measured S parameter to TDR. How can I get TDR impedance from an S parameter in ADS? 038- How to debug a SERDES design with jitter analysis? 039- How to export waveform files from ADS to Infiniium for eye and jitter analyses? 040- How to read a waveform file of csv format in ADS for SI analysis? 041- How to build a compliance test report of DDR4 simulation?

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Part 3 Applications SERDES 042- What are architectures of high speed SERDES transmitter and receiver? 043- What is Inter Symbol Interference (ISI)? 044- How does pre-emphasis work to improve a high speed digital signal? 045- How does Continuous Time Linear Equalizer (CTLE) work to improve a high speed digital signal? 046- How does Feed Forward Equalizer (FFE) work to improve a high speed digital signal? 047- How does Decision Feedback Equalizer (DFE) work to improve a high speed digital signal?

Power Integrity 048- What are high frequency characteristics of a real capacitor? 049- How to import vendor component libraries and use those components in a design? 050- How to model a power distribution system? 051- How to analyze impedance of a Power Distribution Network (PDN)? 052- How to select decoupling capacitors to meet target impedance of a PDN efficiently?

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ADS SI Simulation Q&A SI_Q&A_001

Question

I am new to SI simulation. How to start learning SI simulation?

Answer

It is useful to know matrix of SI simulation .

Application

Approach

•SERDES •DDR

•Channel •Signal

Phase

Simulator

•Pre-layout Simulation •Post-layout Simulation

•S-Parameters •Transient •ChannelSim

Figure 1. Matrix of SI Simulation First, make sure which application you would like to do. Simulation skills between SERDES and DDR are quite different. In SERDES design, channel loss dominates system performance. Equalizers are used to compensate channel loss. In DDR design, delay, load and crosstalk are crucial. Timing analysis is essential for DDR analysis. Second, there are two approaches to examine SI issues. ByChannel-Approach is to study characteristics of channels, such as loss, impedance mismatch and crosstalk. By-Signal-Analysis is to study how signal travels along the channel. We gauge signal quality with eye and eye statistics.

ADS SI Simulation Q&A Third, Pre-layout simulation is to define PCB layout rules. Equationbased transmission line components are generally used as channel models. Post-layout simulation is to examine performance of real PCB routing. EM solvers are used to extract channel models from PCB layout. Finally, you have to understand capabilities of the three simulators. S-parameters simulator is used to calculate channel performance in frequency domain. Transient is used to simulate time domain waveform of a link including transmitter, channel and receiver. ChannelSim is used to calculate statistics of eye pattern and eye statistics of a link. Figure 2 shows an example of ChannelSim simulation of a SERDES link with equation based transmission line models. We can view eye variation along the channel. Figure 3 shows an example of S parameters simulation of a SERDES channel, which is modeled with EM solvers.

Figure 2. Pre-Simulation, Eye density along a SERDES link

Figure 3. Post-Simulation, Sdd21 of a SERDES channel 7

ADS SI Simulation Q&A SI_Q&A_002

Question

What is difference between SERDES and DDR in SI simulation and analysis?

Answer

SI simulation and analysis is important in SERDES and DDR channel design. Because of difference in topology, IO structure and timing, SI design between SERDES and DDR can be very different. For instance, the major bottleneck of SERDES SI is bandwidth of channel. So, impedance and loss control are the first priorities of SERDES channel design. De-emphasis and Equalizer are signal processing blocks used to improve eye opening. As for DDR, all DQs are aligned to DQS Strobe; Command and Address are aligned to Clock. Therefore, timing control is the most important design goal. Further, crosstalk and simultaneous switching noise (SSN) also degrade DDR signal. SERDES

DDR

Application

PCIE, SATA, USB3…

DDR3, DDR4…

Topology

Point to Point

Point to Point, T Branch, Fly-By

Signal

Differential Pair

Differential Pair, Single-Ended

Termination

Fixed

Variable

Channel Length

Long

Short

Coding

Yes

No

Equalizer

Yes

No

Clock

Embedded

Outside

SSN

Weak

Strong

Table 1. SERDES vs. DDR

ADS SI Simulation Q&A SERDES simulation: IBIS AMI model is a popular IO model. ChannelSIm simulator is dedicated to long bit patter simulation for SERDES. In general channel length of a SERDES design is longer. Loss is the most critical factor of SERDES signal integrity. To compensate high frequency loss of a channel, de-emphasis at transmitter or equalizer at receiver are utilized to open closed eye due to channel loss. In addition, TDR simulation and mixed mode S parameter simulation can check channel quality quickly.

Figure 1. PCI Express Channel Simulation using IBIS AMI Models DDR Simulation: IBIS model is widely used in DDR SI simulation. Transient simulator calculates setup time and hold time of DQ with respect to DQS Strobe in write and read mode. S parameter simulation is also useful to check electrical delay (group delay) in frequency domain. DDR topology could be in multi-drop or daisy chain architecture. On Die Termination (ODT) must be adjusted dynamically by specific control signal. Batch controller can handle complex parameter sweeps, such as length, impedance, ODT, etc.

Figure 2. DDR Waveform Simulation using IBIS Models

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ADS SI Simulation Q&A SI_Q&A_003

Question

What SI analysis approaches does ADS support?

Answer

There are two types of SI analysis approaches.

One is By-Channel-Analysis. TDR analysis could help to identify impedance mismatch of a channel. If impedance deviation is over criterion, the defect can be located and fixed. S parameter analysis provides information of channel bandwidth in frequency domain. In short, By-Channel-Analysis gives designer more insight into quality of channel. The other is By-Signal-Analysis, SPICE or IBIS IO model serve as Transmitter (Tx) and Receiver (Rx). Combine SPICE IO model and channel model, run a transient simulation to check waveform at receiver side before prototyping. Generally speaking, channel is analyzed firstly to ensure channel quality. Then, signal is simulated to confirm full system performance. By-Channel-Analysis • Analyze Impedance Mismatch by TDR • Check Impulse Response • Measure Bandwidth • Estimate Group Delay • Calculate Insertion Loss to Crosstalk Ratio (ICR) • … By-Signal-Analysis • Check Eye Pattern • Evaluate Eye Height and Eye Width at BER • Calculate Setup Time and Hold Time • Estimate Peak to Peak Jitter or Root Mean Square Jitter • Estimate BER with Bathtub • …

ADS SI Simulation Q&A By-Signal-Analysis can provide a whole picture of system performance. But if system performance is out of specification, it is difficult to figure out the root cause. In contrast, By-ChannelAnalysis is helpful to find out channel defect, but it can’t give the full system performance metrics. Understanding both analysis skills is necessary for a competent SI engineer. Example of By-Channel-Analysis:

Figure 1. ICR Simulation Example of By-Signal-Analysis:

Figure 2. Eye Pattern Simulation

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ADS SI Simulation Q&A SI_Q&A_004

Question

What is the difference between pre-simulation and postsimulation?

Answer

PCB routing plays an important role to signal integrity in high speed digital design. To ensure quality of signals on routing, the stack-up, impedance, length, spacing, via size, pad size and material must be well planned before PCB routing. Pre-simulation is adopted in this phase to define layout rules. Channel model would be based on equation-based transmission line mode.

Pre-Simulation

PCB Routing

Post-Simulation

Usually layout engineers would follow layout rules as much as possible. In reality, it is almost impossible to follow all rules. The problem is we don’t know if those traces not following design rules would work well or not. In Post-Simulation, channel model is extracted by EM solver based on routing, substrate material and stack-up. So, it provides more accurate details than equationbased transmission line model.

PCB Design Phase Pre-Simulation: Equation-based transmission line model as channel model. Define transmission line width, spacing, etc. Design via, pad… Study channel topology . Estimate signal performance roughly. … Post-Simulation EM-based transmission line model as channel model. Calculate impedance mismatch due to via, pad, etc. Check effect of imperfect loop path. Evaluate level of crosstalk induced by other channels. Estimate signal performance precisely. …

ADS SI Simulation Q&A In IC design company, pre-simulation is more often used than postsimulation. Comprehensive PCB layout guideline is useful for system integration company when adopting the IC. Thus, postsimulation is more popular in system integration company. A real electronic system would have tens to hundreds ICs. Out of rules routing is inevitable in most cases. Below are examples of presimulation and post-simulation.

Figure 1. Pre-simulate Eye with Equation-Based model

EM Solver Simplified PCB Routing S Parameter

Figure 2. Post-simulate Eye with EM-Based Model

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ADS SI Simulation Q&A SI_Q&A_005

Question

What kind of circuit simulator & EM solver supported by ADS for SI analysis?

Answer

ADS platform supports schematic, layout design and simulation environment. ADS Platform

Schematic

S Parameter Simulator

Transient Simulator

Layout

Channel Simulator

MoM EMSolver

FEM EMSolver

Figure 1. ADS platform architecture In ADS schematic environment, there are 3 circuit simulators for SI simulation and analysis:

• S Parameter Simulator: for channel S parameter simulation. S parameter helps user to identify insertion loss, bandwidth and crosstalk of channel in frequency domain. • Transient Simulator: a classical time domain simulator. TDR, waveform rising/falling, ringing and eye pattern can be analyzed by Transient Simulator. IO model (SPICE or IBIS) can be with channel model in transient simulation. • Channel Simulator: for longer bit sequence simulation. ChannelSim is more efficient than Transient. It is useful to check system performance such as Bathtub, BER Contour, etc. IBIS AMI or behavioral IO model can be used in ChannelSim.

ADS SI Simulation Q&A User can build multi-layer structure such as PCB layout manually in ADS layout environment or import layout with GERBER format. After stack-up setup and port setting, Run EM solver to get broadband S parameter of layout by electromagnetic (EM) solver. ADS supports two EM solvers: • Method of Moment (MoM): for pure planar structure modeling, like long PCB traces, differential pairs, power distribution network (PDN), spiral inductor, etc. Only metal are meshed. Current distribution and radiation pattern can be shown after simulation. • Finite Element Method (FEM): full 3D EM solver, for package (BGA, lead frame, bond-wire), connector, socket, etc. All material inside bounding box are meshed. Electronic field, magnetic field, current field and radiation pattern can be shown after simulation. Flow chart below is a typical SI analysis flow. Firstly, run EM solver to get S parameter of interconnect under test. Secondly, insert S parameter model in schematic. Finally, run circuit simulation to check signal performance at receiver side.

Step1: Run EM solver to get S parameter

Step2: Insert S parameter model in schematic

Step3: Run Transient simulation to get eye pattern at receiver side

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ADS SI Simulation Q&A SI_Q&A_006

Question

What are benefits of ADS platform for SI design and analysis?

Answer

ADS is a platform for SI design and analysis including: • Main window: for workspaces, libraries, cells and data display management. A cell could be a schematic or a layout design. We can build, open or delete cells in main window. A library is a collection of cells with same technology. Component suppliers provide their component models in a library called design kit. We can download design kits from official websites of component suppliers and install them in ADS.

muRata™ Design Kit

• Schematic editor: provides a flexible Graphical User Interface for models building and simulators setup. For example, we can construct a high speed SERDES system with channel models and IO models block by block in schematic editor and run transient simulation. We can also setup analysis such as DOE and optimization in schematic editor. • Layout editor: for IC, IC package and PCB layout. We can build a circuit layout from scratch. Or we can import layout in standard layout format, such as GERBER or dxf. When we want to model specific traces for signal integrity analysis, we can launch EM setup window to define substrate stack-up, material properties and frequency band-width for EM simulation. • Data display window: for data management and visualization. We can build various charts and tables in one page for reporting. There are hundreds of equations for data processing, such as fft(), eye(), histogram(), etc. We can also export simulation data or import data into data display for data analysis. Eye, Jitter and SP-TDR front panels provide advanced signal analyses.

ADS SI Simulation Q&A • Examples and design guides: There are hundreds of signal integrity designs grouped in examples and design guides in ADS. These examples are used to speed up design process. There are high speed digital applications include USB3, DDR3, HDMI, SASII, UHSII, etc. There will be more new applications.

USB3 Design Guide

• Technical support, knowledge center and websites: every ADS legal user can request ADS support team’s assistance via email or phone call. In addition, we can find a lot of solved questions and solutions in EEsof knowledge center website. ADS signal integrity and ADS tips websites provide abundant application notes and videos for signal integrity learning.

Schematic editor • Circuit design • Circuit simulation • Statistical analyses

Simulation Data

Data display window • Data display edit • Data processing • Data import and export

Main window • Library management • Cells management • Data display management

Layout editor • Layout edit • EM simulation • EM field visualization

Simulation Data

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ADS SI Simulation Q&A SI_Q&A_007

Question

How to make a complex schematic readable?

Answer

To perform a complete signal integrity simulation, we might have to build a complex schematic including channels, transmitters, receivers, scopes, etc. It might not be easy to view and debug a complex schematic. To make a complex schematic become compact and readable, we can group several components into a single component. Then, there are few components left in the schematic.

Figure 1 shows a schematic of channel simulation. The channel is composed with four S parameter blocks. The schematic looks complicated. How to make it more compact? Firstly, copy the four S parameter blocks into a new cell called “Channel_Model”. Then, attach pins to inputs and outputs of channels as shown in figure 2. We can’t perform simulation of this cell because there are no sources and simulators in this cell.

Figure 1. A complex schematic of channel simulation

ADS SI Simulation Q&A

Pin component

Figure 2. “Channel_Model” cell includes four S parameter blocks Secondly, create a symbol view of “Channel_Model” cell in symbol view editor as shown in figure 3. Symbols are used to represent lower level cells in higher level schematic.

Figure 3. Build a symbol of “Channel_Model” cell Finally, replace the four S parameter blocks with “Channel_Model” cell as shown in figure 4. Now, we have a more compact schematic.

Figure 4. A more compact schematic 19

ADS SI Simulation Q&A SI_Q&A_008

Question

What is “DesignGuide” and what it can help in signal integrity analysis?

Answer

For novices at signal integrity analysis, DesignGuide is a useful tool to start a signal integrity analysis. There are two kinds of DesignGuides in ADS. One is for Radio Frequency (RF) circuit design, such as amplifier, filter, mixers, etc. The other is for signal integrity analysis, such as HDMI, SASII, IBIS AMI, etc. We’ll introduce DesignGuide of signal integrity analysis. In ADS schematic menu, select DesignGuide in menu bar to open DesignGuide list. Click an item of the list will open a DesigGuide window. For example, click USB3 DesignGuide, a USB3 DesignGuide window as shown in figure 1 will pop up.

Figure 1. USB3 DesignGuide window

ADS SI Simulation Q&A A DesignGuide would include models, design templates and data analysis displays. For example, double click “USB Reference Channel Simulation” in USB3 DesignGuide window, ADS would bring up a schematic of “Reference_Channel_With_IBIS_AMI” as shown in figure 2. It is a good example to setup a USB3 channel simulation with AMI models.

Figure 2. Schematic of “Reference_Channel_With_IBIS_AMI” To check if S parameters of a channel meet mask requirement, double click “USB S-Parameter Mask Template” to load a data display of “USB_S_Parameter_Mask.dds” as shown in figure 3. Mask in frequency domain are defined with equations in data display. We can then examine characteristics of the channel easily.

Figure 3. USB_S_Parameter_Mask.dds 21

ADS SI Simulation Q&A SI_Q&A_009

Question

What are benefits of ADS data display?

Answer

ADS Data display is a powerful tool to process and display complex simulation data. It allows user to design a readable display as shown in figure 1 with building blocks including Rectangular Plot, Mark, List and Equation. In addition, a well designed data display could be saved as a template for future use.

Figure 1. A well designed data display Sometimes, we have to further process simulation results for specific data. For example, run FFT to get spectrum of a timedomain waveform. ADS provides hundreds of equations in data display for data processing. The usage of these equations could be found in ADS Help. There are eight categories of equations which are often used for high speed digital signal analyses:

ADS SI Simulation Q&A • • • • • • • •

Data Access Functions for Measurement Expressions FrontPanel Eye Diagram Functions Jitter Analysis Functions FrontPanel S-Parameter TDR Functions Math Functions For Measurement Expressions Statistical Analysis Functions Transient Analysis Functions Utility Functions for Measurement Expressions

For example, we can transform a time-domain waveform to a frequency-domain spectrum with fs() as shown in left chart of figure 2. Or, we can calculate histogram of a waveform with histogram() as shown in right chart of figure 2.

Figure 2. Signal processing with equations In addition, when all data are ready, we can copy the data display to Microsoft™ Word™ or PowerPoint™ directly with Ctrl+C and Ctrl+V as shown in figure 3. It saves us a lot of time when generating a report.

Figure 3. Copy and paste data display with Ctrl+C and Ctrl+V 23

ADS SI Simulation Q&A SI_Q&A_010

Question

What is a “Signal Integrity Design Cycle”?

Answer

A complete Signal Integrity Design Cycle includes Modeling, Simulation, Analyses and Correlation.

Modeling

Simulation

Correlation

Analyses

Figure 1. Signal Integrity Design Cycle Modeling is to define mathematical presentations of channels, transmitters and receivers using proper tools such as EM solvers or test instruments, etc. The challenge of modeling is how well we know the components and how well we handle modeling tools. Correct models are essential to accurate simulation. Thus, to understand pros and cons of different model types and modeling tools are helpful to improve SI analysis qualities.

When we have component models, we can assemble these models into a system. We can then prove how well the system work by simulation. We will get different system performance results with different simulators. For SI simulation, S Parameter, Transient and ChannelSim are commonly used simulators in ADS.

ADS SI Simulation Q&A Analyses include system optimization, Monte Carlo, yield analysis, sensitivity and Design of Experiment (DOE), etc. For example, we can test how dimension deviation of a differential pair and substrate property deviation affect eye pattern with DOE as shown in figure 2. In this case, we can see that the most critical factor to eye height is spacing of the differential pair as shown in figure 3.

Figure 2. An example of DOE analysis

Figure 3. Pareto chart of effect of each factor Value of a simulation is it can estimate performance of a real system. To know how good a simulation, we will rely on correct measurement. The correlation between simulation and measurement provides know-how to improve modeling and simulation. Figure 4 shows an example of eye pattern correlation.

Simulation

Measurement

Figure 4. A eye correlation between simulation and measurement 25

ADS SI Simulation Q&A SI_Q&A_011

Question

How to import an HSPICE netlist of IO Buffer for SI simulation?

Answer

Generally, an IO Buffer design includes a SPICE (Simulation Program with Integrated Circuit Emphasis) netlist of IO circuit and models of transistors. HSPICE™ netlist is a common format for netlist and models. To import an HSPICE netlist of IO Buffer into ADS, select Tools > HSPICE Compatibility Component > Wizard to open HSPICE Compatibility Wizard window. Then, follow steps below to import an HSPICE netlist:

1. Specify HSPICE file name to import 2. Input ADS design name 3. Setup input and output pins of the ADS design 4. Edit symbol 5. Setup parameters 6. View summary and click Finish button to import the netlist Now, we can combine the imported HSPICE format IO buffer model with transmission lines, DC bias, sources, resistors and probes as shown in figure 1 for SI simulation. When necessary, we can push into the model to view and edit netlist.

Figure 1. Using HSPICE netlist of IO model for SI simulation

ADS SI Simulation Q&A Step1. Specify HSPICE file name to import

Step2. Input ADS design name

Step3. Setup input and output pins of the ADS design

Step4. Edit symbol

Step5. Setup parameters

Step6. View summary and click Finish button to import the netlist

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ADS SI Simulation Q&A SI_Q&A_012

Question

How to build SERDES transmitter and receiver Algorithmic Model Interface (AMI) models with SystemVue?

Answer

Keysight SystemVue is an Electronic System Level (ESL) design tool for system architecture engineers to design mathematical models of electronic systems. Therefore, SystemVue is useful for SERDES architecture modeling and verification. Figure 1 shows a SERDES receiver modeled with SystemVue. The receiver model includes FFE, CDR and DFE. Parameters of these components are editable. We can modify parameters of these components and perform Data-Flow simulation to examine system performance, such as eye pattern. Besides, the models could be exported in AMI format. Then, we can use these AMI models in a channel simulation in ADS.

CDR FFE

DFE

Figure 1. A receiver modeled with SystemVue

ADS SI Simulation Q&A SystemVue provides AMI transceivers library as shown in figure 2 for SERDES architecture engineers to build AMI models. The library includes many useful components for SERDES system modeling, such as VCO, FFE, DFE and CDR. In addition, we can build our proprietary components in C++ and use them in SystemVue. To create AMI models: 1. Build TX or RX models with AMI transceiver and proprietary components in SystemVue as shown in figure 1. 2. Perform Data-Flow simulation to make sure response of the models meet design objectives. 3. Generate C++ code of the models as shown in figure 3 and compile the C++ code to AMI compatible .dll and .ami files. 4. Combine .ibs, .dll and .ami files in the same folder and use keyword [Algorithmic Model] in .ibs file to link related files. 5. Verify the models in ADS as shown in figure 4. Make sure all parameters are workable and the performance is correct. 6. Publish AMI models with their application notes, which explain architectures, parameters and usage of the models.

Figure 2. AMI transceivers library

Figure 3. AMI model generation window

Figure 4. Verify AMI models with ChannelSim in ADS 29

ADS SI Simulation Q&A SI_Q&A_013

Question

How to set up IBIS (Input/Output Buffer Information Specification) models for SI simulation in ADS?

Answer

IBIS models are widely used in signal integrity simulation. IC chip vendors provide IBIS model files of chips. SI engineers then could use the IBIS models in EDA tools for simulation. There are various IBIS components as shown in figure 1, which map to different IO circuit architectures. We could edit and view properties of the IBIS model in the property dialogue box as shown in figure 2. IBIS_3S_ECL (3-State_ECL) IBIS_3S (3-State) IBIS_D3S_ECL (Differential 3-State_ECL) IBIS_D3S (Differential 3-State) IBIS_DI_ECL (Differential Input_ECL) IBIS_DI (Differential Input) IBIS_DIO_ECL (Differential Input-Output_ECL) IBIS_DIO (Differential Input-Output) IBIS_DIO_OPENSINK (Differential IO Open Sink) IBIS_DIO_OPENSOURCE (Differential IO Open Source) IBIS_DO_ECL (Differential Output_ECL) IBIS_DO (Differential Output) IBIS_DOPENSINK (Differential Open Sink) IBIS_DOPENSOURCE (Differential Open Source)

IBIS_DT (Differential Terminator) IBIS_I_ECL (Input_ECL) IBIS_I (Input) IBIS_IO_ECL (Input-Output_ECL) IBIS_IO (Input-Output) IBIS_IO_OPENSINK (IO Open Sink) IBIS_IO_OPENSOURCE (IO Open Source) IBIS_O_ECL (Output_ECL) IBIS_O (Output) IBIS_OPENSINK (Open Sink) IBIS_OPENSOURCE (Open Source) IBIS_T (Terminator) IBIS_S_O (IBIS Series Output) IBIS_S_I (IBIS Series Input)

Figure 1. Various types of IBIS components

Figure 2. Property dialogue box of an IBIS component

ADS SI Simulation Q&A

Figure 3. IBIS_IO and its equivalent circuit IBIS_IO is one of the most common IBIS models. It is a component with eight pins as shown in figure 3. To make IBIS_IO work, PU and PC pins have to be biased. PD and GC pins have to be grounded. When IBIS_IO model serves as a transmitter as shown in figure 4, pin E must be enabled and pin T must be triggered with an external source. When IBIS_IO serves as a receiver, pin T and pin E are left open. Note that only Transient simulator supports IBIS models. Simulation result is shown in figure 5.

TX

RX

Figure 4. A simple IBIS simulation

Figure 5. IBIS simulation result 31

ADS SI Simulation Q&A SI_Q&A_014

Question

Could you explain how to model high speed channel? And what I have to pay attention to when modeling a channel?

Answer

In high speed digital signal transmission, a channel is electrical path from Tx IO buffer to Rx IO buffer. It may consist of IC packages, traces on PCB, connectors and cables. A simple channel can be from TX IO, PCB traces to RX IO. A complex channel such as backplane consists of components as in figure 1. Daughter card

Daughter card Connector

Connector

Backplane Figure 1. A ~20 inches long channel There are three most important characteristics you have to pay attention to in channel modeling , including: • Impedance • Loss • Delay or phase Impedance depends on geometric structure, dielectric constant and metal conductivity. Impedance mismatch causes multi reflection. It leads to signal ringing, overshoot and undershoot. Channel loss is critical for SERDES design, the main contributors to channel loss are dielectric loss and conductor loss. It is frequency dependent in general. Band-width of a channel limits maximum bit rate. For DDR, phase difference between command/address and clock or DQ and DQs must be well controlled.

ADS SI Simulation Q&A

Figure 2. Different components in a channel Components of a channel could be modeled by equation-based transmission line model, EM-based model or measurement based model. Correct modeling of each component relies on exact dimension and material parameters. When models are well defined, cascade these components to construct a full channel model like figure 2. Then, impedance and delay of a channel can be estimated by TDR simulation like in figure 3. Loss of a channel can be estimated by S parameter simulation like in figure 4. The result provides hints to improve channel for more robust and higher data rate transmission.

Figure 3. Impedance variation (left) and delay (right)

Figure 4. Insertion loss (left) and phase (right)

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ADS SI Simulation Q&A SI_Q&A_015

Which components in ADS are used in channel modeling for signal integrity design and analysis?

Answer

Components in ADS are categorized by function. There are five major categories in channel modeling. They are Lumped Components, Data Items, Tlines-Ideal, Tlines-Microstrip and TlinesMultilayer.

Data-Items

Lumped-Components

Question

Lumped-components includes resistor (R), inductor (L), capacitor (C) and other lumped components. Some short physical length structures are suitable to be modeled with R, L, C. Those structure include as bond-wire, drill, connector, die pad, etc. For instance, IBIS buffer model bond-wire with L_pkg, R_pkg and C_pkg like figure below:

Data-Items includes SNP and de-embed components. S parameter is a popular channel model. It can be extracted by measurement or by EM solver. It is usually in Touchstone format. SNP components read Touchstone files as channel models like figure below:

ADS SI Simulation Q&A

TLines-Ideal

TLIines-Ideal includes equation-based ideal transmission line models that are defined in electrical parameter, such as impedance, degree and delay like figure below:

TLines-Microstrip

TLines-Microstrip includes equation-based micro-strip line models and RF micro-strip circuits. Microstrip line models are calculated based on substrate thickness, material parameter, line width, line length and spacing.

TLines-Multilayer

TLines-Multilayer includes equation-based multi-layer transmission line models. It is to model micro-strip and strip line in single wired or parallel bus. Stack-up and material property must be assigned to each layer. Model could be exported to SPICE Welement.

Please note that channel which is composed with components of these five categories is compatible with transient, channelsim and S parameter simulator. 35

ADS SI Simulation Q&A SI_Q&A_016

Question

How to design a transmission line in ADS?

Answer

Controlled Impedance Line Designer (CILD), shown in figure 1, is a powerful tool to design transmission lines. It is used to calculate electrical characteristics of transmission lines including differential impedance, common impedance, delay, attenuation and effective electrical length. CILD supports six types of transmission lines: • • • • • •

Microstrip Single-Ended Microstrip Edge-Coupled Microstrip Broadside-Coupled Stripline Single-Ended Stripline Edge-Coupled Stripline Broadside-Coupled

Figure 1. Design a edge coupled stripline with CILD

ADS SI Simulation Q&A Then, we can build a differential pair with components in TLinesMultilayer for system performance estimation as shown in figure 2.

Figure 2. Build a differential stripline model for system estimation As sown in figure 3, CILD allows users to sweep variables including frequency, length , width, space, thickness, dielectric constant, loss tangent of each layer, etc. Simulation results as shown in figure 4 provide valuable information about impedance, delay and loss variation with variables.

Figure 3. Sweep variables

Figure 4. Charts of impedance, delay and attenuation variation 37

ADS SI Simulation Q&A SI_Q&A_017

Question

How to design controlled impedance vias with Via Drawing Utility?

Answer

Controlled impedance vias are critical for SERDES performance. To design a pair of controlled impedance vias, the drills, pads, antipads and spacing of vias must be well designed. Via Drawing Utility, shown in figure 1, is an easy-to-use tool in ADS to build complex structures of vias . We can input spacing, hole diameters, pad and anti-pad sizes of vias on each layer. Then, click Draw button to generate the vias layout as shown in figure 2.

Figure 1. Via Drawing Utility

ADS SI Simulation Q&A We can perform FEM or Momentum simulation in ADS to extract S parameters of a pair of vias. Then, TDR simulation as shown in figure 3 would be used to check impedance of the pair of vias as shown in figure 4. If the TDR result shows impedance mismatch, we can refine via structures in Via Drawing Utility till a matched impedance vias design is achieved.

Figure 2. layout and 3D view of a pair of vias

Figure 3. TDR simulation of the pair of vias

Figure 4. Examine impedance of the pair of vias 39

ADS SI Simulation Q&A SI_Q&A_018

Question

What is current return path of a transmission line?

Answer

When a signal travels along a transmission line, induced electric currents exist on the transmission line and on the ground plane beneath the transmission line simultaneously as shown in figure 1. The red arrows represent currents flowing from port 1 to port 2 along the transmission line. The blue arrows beneath the transmission line represent return currents flowing from port 2 back to port 1. The current flows form a complete current loop for signal transmission. The path that return current passes through is called current return path. Port 2

Port 1

Figure 1. Currents on transmission line and on return path Port 2

Port 1

Figure 2. A discontinuity in current return path

ADS SI Simulation Q&A If there is a slot beneath a transmission line on ground plane, it will result in a discontinuity in current return path as shown in figure 2. The return path discontinuity will cause impedance mismatch. TDR simulation could be used to check impedance mismatch as shown in figure 3. In addition, when current paths of two transmission line overlapped as shown in figure 4, crosstalk between the transmission lines will be amplified as shown in figure 5. To model transmission lines with non-ideal return paths, ADS Momentum EM solver is an effective and efficient tool.

Figure 3. Impedance mismatch caused by return path discontinuity

Figure 4. Return paths of two lines overlapped around the slot

Overlapped return paths

Normal return paths

Figure 5. Overlapped return paths amplify crosstalk 41

ADS SI Simulation Q&A SI_Q&A_019

Question

How to build a measurement-based channel model?

Answer

Vector Network Analyzer (VNA) measures multiport S parameter of Device Under Test (DUT) over a broad bandwidth in frequency domain. DUT could be sockets, connectors, cables, or PCB traces. S parameter of DUT saved in Touchstone type can be used as channel model in ADS. This model is a measurement-based model with high accuracy.

Figure 1. An example of VNA measurement setup In Touchstone filename, filename extension could be “.snp”, where “n” is the number of network ports of the device. SnP components in ADS Data Items category support Touchstone type S parameter models as shown in figure 2.

Figure 2. S4P Components in ADS

ADS SI Simulation Q&A VNA is a powerful instrument for component characterization. It can measure DUT between well calibrated reference planes. Often there are fixtures that connect reference plane of VNA to the ends of DUT as shown in figure 3. Thus, the measurement result includes effects of DUT and fixtures. De-embedding is used to remove fixture effects from measurement. ADS provides up to twelve ports de-embedding components. We can run S parameter simulation like figure 4 to get characteristic of DUT only, as shown in figure 5.

DUT

fixture

fixture

Figure 3. An example of Cable (DUT) and fixtures

Figure 4. An example of four port de-embedding

After De-embedding Before De-embedding

Figure 5. Insertion loss of DUT before and after de-embedding 43

ADS SI Simulation Q&A SI_Q&A_020

Question

What is “broadband SPICE model” and how to generate it?

Answer

For high speed digital design, S parameter is commonly used to model channel and crosstalk between channels. ADS Transient is equipped with an advanced convolution engine. User can use S parameter as channel model in Transient simulation directly as shown in figure 1.

Figure 1. ADS Transient simulation with S parameter However, for IO buffer circuit designers, the SPICE tools they use might not handle S parameter well. When S parameter is broadband and with multi-ports, simulation result might be inaccurate as shown in figure 2. To provide IO buffer circuit designers an accurate and stable model for Transient simulation in their SPICE tool, ADS provides a Broad Band SPICE Model Generator to convert S parameter to its equivalent broadband SPICE model.

Figure 2. (Left) Wrong SPICE result (Right) JBERT measurement

ADS SI Simulation Q&A To launch Broadband SPICE Model Generator, select Tools > SPICE Model Generator > Start Broadband Generator. Interface of Broadband SPICE model generator is shown in figure 3. We can select input S parameter in Touchstone or dataset format. Then, select output SPICE format to export. Supported SPICE format includes HSPICE™, SPECTRE™, SPICE2 and SPICE3. Now we can start SPICE model generation.

Figure 3. Broadband SPICE Model Generator When generation complete, the generated SPICE files will be saved in “bbspice” folder under workspace. IO buffer circuit designers can include the equivalent SPICE model in their design for Transient simulation. Data display will show the correlation between input S parameter data and its equivalent broadband SPICE model as shown in figure 4.

Figure 4. Correlation between S parameter and it’s equivalent SPICE model 45

ADS SI Simulation Q&A SI_Q&A_021

Question

What structures in a transmission line cause impedance mismatch?

Answer

ADS transmission line models are commonly used to model simple and straight transmission lines. These models are easy to use and reliable. However, these models are accurate only under specific conditions including straight line, constant width and spacing, on the same layer and complete ground plane as shown in figure 1.

Figure 1. A simple and straight differential microstrip In a real PCB design, transmission lines are often complicated as shown in figure 2. Non-uniform structures, such as vias, pads and bends, cause impedance mismatch and degrade signal integrity. Transmission line models are incapable to model these effects. EM solvers, such as ADS momentum, could be used to extract the model.

pads vias

bends

vias slot

Figure 2. A complicated differential pair

ADS SI Simulation Q&A There are three types of vias: blind vias, buried vias and through hole vias. Blind and buried vias are good for signal integrity but costly. Through hole vias are widely used in high speed designs. When a through hole via bringing a signal from top layer of a PCB down to an internal signal layer, a stub is created as shown in Figure 3. The stub will act like a shunt capacitor and will cause resonance. In theory, the longer the stub, the lower the resonance frequency.

Top Layer Internal Signal Layer

Figure 3. Stub structure in through hole vias A via is with inductance and capacitance that determine the via impedance. When impedance of via is the same as the transmission line it connected, there is no signal distortion. It can be achieved by controlling size of drills, pads and clearance holes. When a trace changes direction, it will cause impedance mismatch. In general, a sharper bend has a greater amount of impedance discontinuity. It is difficult to avoid bending a trace in a PCB layout. Therefore, to reduce the impedance change, shape of bends must be well designed. Every high speed transmission line requires a complete current return path in ground plane paralleled to the transmission line. A slot in the current return path will act as a series inductance in the transmission path and degrade signal integrity. Besides, crosstalk between traces which share the same slot will be amplified. Parasitic capacitance of pads will cause impedance mismatch too. The capacitance depends on pad size, dielectric constant and distance to ground plane. To reduce parasitic capacitance of pads, a common way is to make cutouts in the ground plane underneath the pads. 47

ADS SI Simulation Q&A SI_Q&A_022

Question

How to Import a PCB layout into ADS layout editor?

Answer

For post layout simulation, firstly, we have to import a PCB layout into ADS layout editor. Then, perform an EM simulation to get broadband frequency S parameters for further SI analysis. There are three ways to import PCB layout into ADS layout editor: import PCB in GERBER format, import PCB in ODB++ format and Import PCB with “ADS Design Flow Integration” (ADFI).

GERBER

GERBER format is a popular PCB file format. In ADS layout window, select File > Import to open “Import” window. Then, select GERBER/Drill in File type drop-down list. Finally, select all Gerber files to import as shown in figure 1.

Figure 1. Import full PCB layout in GERBER format

ODB++

A drawback of GERBER format is that it does not include net information. Therefore, we have to import full PCB layout and simplify layout manually for EM simulation. ODB++ is a good alternative PCB layout format. ODB++ includes not only net information, but also layer and component information. For example, we can select necessary nets to import as shown in figure 2.

ADS SI Simulation Q&A

Figure 2. Import DDR nets in ODB++ format

ADFI

ADS supports ADFI for Cadence™ Allegro™. We can select nets to export in Allegro as shown in figure 3. Then, import nets into ADS layout editor as shown in figure 4. In addition to nets, stack-up and materials are imported into ADS at the same time.

Figure 3. ADFI interface in Allegro

Figure 4. Import nets with ADFI tools

49

ADS SI Simulation Q&A SI_Q&A_023

Question

How to perform an Electromagnetic (EM) simulation within ADS?

Answer

Step1: Prepare a layout. Place pins at pads where components will be connected to as shown in figure 1.

Figure 1. A DDR bus layout with pins Step2: Define material properties such as dielectric constant, loss tangent and conductivity. Set up substrate stack-up in substrate editor as shown in figure 2.

Figure 2. Edit substrate stack-up in substrate editor

ADS SI Simulation Q&A Step 3: Set up simulation conditions in EM setup window as shown in figure 3. Such as EM solver, ports, frequency range, mesh density, physical model, boundary conditions, etc.

Figure 3. EM Setup window Step 4: Execute simulation. Simulation time depends on layout complexity, number of ports and frequency range. We can queue multiple simulation jobs and check simulation progress of each job in “EEsof Job Manager” as shown in figure 4.

Figure 4. “EEsof Job Manager” for simulation jobs management Step 5: When simulation finished, check simulation results in data display window as shown in figure 5.

Figure 5. Check simulation results in data display window 51

ADS SI Simulation Q&A SI_Q&A_024

Question

How to define pins and ports in ADS momentum?

Answer

Pins and ports are crucial to an accurate EM simulation. Proper pin and port assignments are preconditions to accurate and stable simulation results. For example, when modeling a trace in PCB as shown in figure 1, pins have to be assigned on pads of components as shown in figure 2. In this example, P1 and P2 are located on Tx pads; P3 and P4 are located on pads of AC coupling capacitor; P5 and P6 are located on Rx pads. There are totally six pins in this example.

Tx

Cap

Trace Ground Net

Rx Figure 1. Diagram of a PCB trace P1

P2

P3

P4

P5

Figure 2. Pin assignment

P6

ADS SI Simulation Q&A Figure 3 is the bird’s view of the example. The polygons in red are on top layer and those in green are on bottom layer. The pins have to be grouped into ports as shown in figure 4 for EM simulation. In this example, P1 and P2 are grouped as port 1; P3 and P4 are grouped as port 2; P5 and P6 are grouped as port 3. The final result will be a three port S parameters when simulation ends. We then can combine this EM-model with circuit components in schematic as show in figure 5 for SI simulation.

Figure 3. Bird’s view of the example

Figure 4. Pins are grouped into ports in Port Editor

Figure 5. Circuit-EM co-simulation 53

ADS SI Simulation Q&A SI_Q&A_025

Question

How to extract an RLC equivalent circuit of a package from S parameters?

Answer

S parameter models are easy to use. However, they provide no RLC information. We could convert an S parameter model to its equivalent RLC circuit. For example, in IC package, an RLC circuit is commonly used to describe its characteristics. Figure 1 left shows a simplified lead frame package. A single bond-wire connects a die and a pin of lead frame. Figure 1 right shows topology of an equivalent circuit to the package. A two port S parameter model of this package is shown in figure 2. Molding Compound

Bond-wire R

L

IC Die C Lead Frame

Figure 1. (left) A simplified lead frame package (right) Equivalent RLC circuit

Figure 2. Return loss and insertion loss of the package

ADS SI Simulation Q&A To extract R, L and C, a simple way is to use equations below: R=1/real(Y11) at DC L=imag(1/Y11)/(2*π*freq) at center frequency C=imag(1/Z22)/(2*π*freq) at center frequency With equations and marks in data display, we could get R, L and C as shown in figure 3.

Figure 3. Extract R, L, C with ADS equations Compare S parameters between original S parameter model and its equivalent circuit as shown in figure 4. Both results are very close as shown in figure 5.

Figure 4. A comparison between S parameters and equivalent RLC

Figure 5. Results of S parameters and equivalent RLC circuit 55

ADS SI Simulation Q&A SI_Q&A_026

Question

How to extract S parameters of a high speed connector in EMPro?

Answer

EMPro is a 3D modeling and design platform for analyzing 3D electromagnetic (EM) effects of components such as high-speed electronic packages, bondwires, connectors and PCB interconnects. We can model 3D components in EMPro graphical interface. Or, import 3D CAD files from third-party 3D modeling tools into EMPro. Figure 1 shows a 3D connector model in EMPro.

Supported CAD formats Figure 1. A 3D connector model in EMPro EMPro provides Finite Difference Time Domain (FDTD) and Finite Element Method (FEM) EM solvers for S parameters and EM field computation. Take FEM as an example, we have to input material characteristics of each part and assign ports before simulation. When simulation begins, mesh will be created as shown in figure 2. Then, FEM solver will compute S parameters iteratively until results converge. EM field and S parameters will be saved when simulation ends.

ADS SI Simulation Q&A

Figure 2. Meshes in FEM simulation EMPro provides lots of post-processing functions. For example, we can view 3D colored EM field as shown in figure 3. It provides valuable insight into how EM field propagates in model. Or, we can check S parameters on Smith chart or XY plot as shown in figure 4.

Figure 3. EM field visualization

Figure 4. S parameters shown in Smith chart and XY plot 57

ADS SI Simulation Q&A SI_Q&A_027

Question

How to export EMPro simulation results to ADS for SI simulation?

Answer

EMPro is a 3D modeling and design platform for analyzing 3D electromagnetic (EM) effects of a component structure. We can create a structure model in EMPro or import a 3D model from third party CAD tools. For example, figure 1 left shows a 3D connector model in EMPro. EMPro provides two EM solvers: FDTD (Finite Difference Time Domain) and FEM (Finite Element Method). We can extract S parameters of a model with EM solvers and show S parameters as shown in figure 1 right.

Figure 1. A connector model and its S parameter in EMPro To export S parameters of connector from EMPro to ADS for SI simulation, select File > Export > Simulation Results as emModel to open export window as shown in figure 2. Then: 1. Select “Simulation Result” to export. 2. Select “Open Access Library” to store the result. 3. Input “Cell Name” for the model. 4. Click “Create Cell” button to create the cell in ADS.

ADS SI Simulation Q&A

Figure 2. Export simulation result as a cell in EMPro

Figure 3. The cell includes an emModel view and a symbol view The cell includes an emModel view and a symbol view as shown in figure 3. S parameters of the connector are stored in emModel view. Now, we can combine connector cell with sources, receivers, lumped components, transmission line models and Eye_Probe for SI simulation as shown in figure 4.

Figure 4. Combining the connector model with other components for SI simulation

59

ADS SI Simulation Q&A SI_Q&A_028

What is the benefit of S parameter simulation? And what components are specific for S parameter simulation?

Answer

S Parameters Simulator calculates wide band S parameters of a channel. Term is used to define the impedance and location of the ports for S parameters simulation. Term has to be continuously numbered from one. Note that time domain sources, IBIS, IBIS AMI and SPICE IO models are not compatible with S parameters simulation.

Simulation-S_Param

Question

Figure 1. S Parameters Simulator and Term Component S Parameter Simulator supports not only S Parameters, but also Z Parameters and Group Delay. You can check the items which you want to examine when simulation . Z parameter is used to analyze impedance profile of power distribution network (PDN). It is useful for power integrity analysis.

Channel bandwidth and Crosstalk can be extracted from S parameter. Channel bandwidth limits maximum bit rate. Insertion loss to crosstalk ratio affects system BER. Both of channel bandwidth and crosstalk are important design factors for SI. A simple S parameter simulation of channels is shown in figure 2. The results of Insertion loss and crosstalk are shown in figure 3.

ADS SI Simulation Q&A Insertion Loss Far End Crosstalk Near End Crosstalk

Figure 2. A simple S parameter simulation

Figure 3. Insertion Loss and Crosstalk Group delay is time delay of a channel in frequency domain. In practical, equal geometrical length does not guarantee equal electrical delay. Figure 4 shows an example of such a layout. Delay mismatch between data and strobe may cause timing skew and data error. Group Delay analysis is helpful for DDR post-simulation.

Figure 4. Group Delay of DQs and Data Strobe If you want to export S parameters in Touchstone format, place a SPOutput component in the schematic and specify the file name of Touchstone file to export. The Touchstone file will be generated when simulation is done. For Batch or Sweep simulation, S parameters of each iteration would be exported in separate Touchstone files. 61

ADS SI Simulation Q&A SI_Q&A_029

What components in ADS are used for Transient analysis?

Answer

Transient simulator calculates node voltage and branch current at each time step. Transient works fine with lumped components and transistor models. Transient simulator used not to process S parameter model well because S parameter is frequency dependent. S parameter model is, however, useful in channel modeling. ADS Transient simulator enhances its advanced convolution engine for S parameter model. In ADS, you can get a reliable waveform in Transient simulation with S parameter model.

Sources-Time Domain

Simulation-Transient

Question

Time Domain sources are all compatible with Transient simulator and are useful for time domain SI analysis. For example, Step source can be used for TDR simulation. Pulse source can be used to model clock signal. VtPRBS supports various bit pattern, output resistance, de-emphasis, jitter, bit rate and PAM encoding.

Signal Integrity-IBIS

ADS SI Simulation Q&A IBIS (I/O Buffer Info Specification) is a popular IO buffer model. IBIS model supports detailed rising and falling waveform. In order to protect intellectual property, IBIS model file records currentvoltage, voltage-time data and IC package parasitic only. To make IBIS model work well, it is necessary to bias power pin, ground pin and enable pin properly. You also have to set trigger signal when IBIS model served as a transmitter.

Although TX AMI, RX AMI, Xtlk TX AMI and Xtlk RX AMI are categorized in IBIS library, they are not compatible with Transient simulator. They are compatible with ChannelSim simulator only. Some IC companies support HSPICE IO model rather than IBIS model for accuracy. To import an HSPICE model into ADS, select Tools > HSPICE Compatibility Component > Wizard. Note that ADS won’t support HSPICE encrypted model. You can select imported HSPICE model and click ‘Push Into Hierarchy’ button to view and edit HSPICE netlist.

63

ADS SI Simulation Q&A SI_Q&A_030

What are benefits of ChannelSim? What components in ADS are compatible with ChannelSim?

Answer

To evaluate performance of SERDES, it is necessary to simulate long waveform for Bit Error Rate (BER). For example, we might require 1e6 bits or even more. It may take hours to days for a transient simulation. That becomes not practical. ChannelSim is a good solution to resolve this issue. Following is a typical signal processing flow of ChannelSim: 1. Perform Transient simulation to get a channel impulse response of 1000 bits long. 2. Transmitter generates a long bit sequence, e.g. 1e6 bits long. 3. Perform convolution of the bit sequence and the impulse response to get waveform after channel. 4. Pass the waveform to receiver for signal equalization.

Simulation-ChannelSim

Question

Typically, it takes only seconds to minutes to get a result of a ChannelSim. EQU

2

1

3

Convolution EQU

Equalization

Figure 1. Signal flow of a ChannelSim

4

ADS SI Simulation Q&A Although ChannelSim accelerates simulation obviously, there is limitation. Only transmitter (Tx), receiver (Rx) models in ChannelSim library and IBIS AMI models are compatible with ChannelSim. More specifically, time-domain sources, IBIS and SPICE models are incompatible with ChannelSim. Transmitter model supports coding, de-emphasis and jitter. Receiver model supports CTLE, FFE, DFE and jitter. It makes ChannelSim flexible for SERDES channel evaluation.

Figure 2. An example of ChannelSim with Tx and Rx models SERDES IO buffer has following characteristics: • Differential signaling • Embedded clock • De-emphasis at transmitter • Equalizer and Clock Data Recovery (CDR) at receiver • Balance coding, e.g. 8b/10b coding • Multilane, Multiplexer Behavior of de-emphasis, CDR and equalizer are critical to SERDES performance. Taking effect of these blocks into account, chip provider compiles C++ code of block models to .dll file. The .dll file, plus .ibs file and .ami file constitute AMI model. Channel simulation with AMI model provides more accurate results of system performance.

Figure 3. An example of ChannelSim with IBIS AMI models 65

ADS SI Simulation Q&A SI_Q&A_031

Question

How to set up bit sequence in ADS source components?

Answer

In ADS, there are four modes in source components to generate a waveform in different bit sequence: 1. 2. 3. 4.

Maximal Length LFSR User Defined LFSR Explicit Bit Sequence Bit File

In mode 1 and 2, Linear Feedback Shift Register (LFSR) is used to generate Pseudo Random Binary Sequence (PRBS). In mode 3, we can input arbitrary bit sequence. In mode 4, source components read a text based bit file to generate a waveform. Figure 1 shows a three tap LFSR example. In this example, Tap3 and Tap1 are inputs of XOR operator, labeled as “101”. Initial value of registers is called seed. In this example, seed is “011”. Every clock cycle, Values in registers shift right, Tap1 is set as the output value of XOR. Output of Tap3 is the generated bit of LFSR.

0 XOR 1=1

Clock #1

Tap1

Tap2

Tap3

1

1

0

X

1

1

0

+ 1

Clock #2

Output

+ Figure 1. Values in registers shift right every clock cycle

ADS SI Simulation Q&A In theorem, maximal cycle length of bit sequence is 2𝑁 − 1, where N is register length. It means bit sequence will repeat itself after 2𝑁 − 1 clock cycles. Figure 2 shows state flow of the three tap LFSR. In this example, bit sequence “0111010” repeats every 23 − 1 = 7 clock cycles. In mode 1, default register length is 8, it means the bit sequence will repeat after 28 − 1= 255 clock cycles. To get a longer cycle length of bit sequence, we can set a larger register length. For example, if register length is set as 32, maximal cycle length of bit sequence will be 232 − 1= 4,294,967,295. In mode 2, we can input Taps and Seed values to generate a specific PRBS as shown in figure 3.

#1

#2

#3

#4

1

1

0

X

+ 1

1

1

0

+ 0

1

1

1

+ 1 +

0

1

1

#5

#6

#7

#8

0

1

0

1

0

1

0

0

0

1

1

0

0

+ 0 + 1 + 1 +

Figure 2. State flow of a three taps LFSR

0 1 1 1 0 1 0 0 1 1 1 0 1

Figure 3. Define Taps and Seed in “User Defined LFSR” mode 67

ADS SI Simulation Q&A SI_Q&A_032

Question

How to build an optimal and robust high speed digital design?

Answer

System analysis is a systematical approach to an optimal and robust design. It helps us answering following questions: • How a specific variable affects system performance? • Is the system robust enough? • How to minimize performance impact due to manufacturing variation? • What is an optimal design? •… ADS provides various controllers for system analysis including: • Batch • Optimization • Design of Experiment (DOE) • Sequencer • Monte Carlo • Yield & Yield Optimization • Sensitivity Unlike simulators, controllers do not calculate voltage and current. Controllers adjust variables and running simulation repeatedly until predefined conditions are met. Batch and Optimization controllers are most often used controllers for SI analysis. Batch controller performs circuit simulations repeatedly with different values of variables. The result shows how the system performs with variables. Batch controller also supports sweeping of files. For example, Reading multiple channel model files for channel simulation at one time as shown in figure 1. Then, examining statistics of eye pattern of each channel as shown in figure 2.

ADS SI Simulation Q&A

Figure 1. Sweeping five channel model files

Figure 2. Eye Height and Jitter RMS of each channel Set Design Goal

Set Variables Range

Set Algorithm

Run Optimization

Optimization is a process to minimize error function by systematically choosing values of variables within an allowed range. The error function measures the difference between the computed and desired responses. The smaller the error, the closer the system performance to the goal. For DDR design, power integrity is crucial to signal integrity. To mitigate power noise, one way is to reduce impedance of power distribution network with decoupling capacitors. Then, the question is how to define capacitance of each capacitor. Optimization controller is an effective and efficient tool. It takes seconds to minutes to find out an optimal set of decupling capacitors. Without Decaps Optimized Decaps

Optimization Flow Chart

Figure 1. An example of impedance optimization 69

ADS SI Simulation Q&A SI_Q&A_033

Question

How to perform batch simulation efficiently with Batch Simulation controller?

Answer

To understand how circuit performance is determined by component variations, a common way is to sweep variables of components in the circuit design. We can then compare results between these simulation runs to get insights of the circuit. Batch Simulation controller is an easy-to-use tool for users to set up complex sweep process as shown in figure 1. It supports “Use sweep plan” and “Use sweep module” modes. In “Use sweep plan” mode, we can input variables to sweep and the sweep range in Batch Simulation dialog box as shown in figure 2.

Figure 1. Perform a simulation with Batch Simulation controller

Figure 2. Sweep variables in “Use sweep plan” mode

ADS SI Simulation Q&A When simulation ends, results of all simulation runs could be displayed in a rectangular plot as shown in figure 3. we can examine the circuit performance variation easily. However, filenames and strings are not supported in “Use sweep plan” mode directly. A solution is to build a file list in a DataFileList component (or a string list in a StringList component) as shown in figure 4 to generate a mapping table between filenames and the index. The indexes then can be used in “Use sweep plan” mode.

Figure 3. Eye height and eye width of all simulation runs

Figure 4. DataFileList and StringList components In “Use sweep module” mode, we can build a sweep plan in a .csv file with text editor as shown in figure 5. Values, filenames and strings are supported in this mode. When simulation begins, Batch controller will set up variables based on the items listed in the file and execute simulation iteratively till all items are performed.

Figure 5. A .csv file used in “Use sweep module” mode 71

ADS SI Simulation Q&A SI_Q&A_034

Question

How to examine performance of multi-channels efficiently?

Answer

Repetitively checking performance of multi-channels could be time consuming. For example, we connect Tx_Diff and Rx_Diff to 1st channel at first as shown in figure 1. Run simulation to get performance of the 1st channel. Next, we move Tx_Diff and Rx_Diff manually to 2nd channel and run simulation to get performance of the 2nd channel. The rest of channels would be done in the same way. When channel count is large, it will take a lot of time to examine performance of all channels.

Figure 1. Checking performance of 1st channel To make it easier, we can use two switch components for channels swapping as shown in figure 2. Parameter N of switch is used to set channel swapped with the 1st channel. For example, N=2 means the 2nd channel is swapped to connect to Tx_Diff and Rx_Diff. When we let N=ix and sweep ix from 1 to 3 in Batch controller, we can get all three simulation results in one dataset. We then can display simulation results of all three channels in one chart as shown in figure 3. The switch component is a user defined model built in Verilog-A code. Code of a three-channel switch is shown in figure 4. The code could be modified to build a more complex switch.

ADS SI Simulation Q&A

Figure 2. Swap channels with switch components

Figure 3. Eye width and eye height of each channel `include "disciplines.vams" `include "constants.vams" module myswitch(in, out); electrical in,out; input [1:6] in; output [1:6] out; parameter real N=1; genvar i; analog begin for(i=1;i<=3;i=i+1) begin if(i==N) begin V(in[1],out[2*N-1]) <+ 1n * I(in[1],out[2*N-1]); V(in[2],out[2*N]) <+ 1n * I(in[2],out[2*N]); V(in[2*N-1],out[1]) <+ 1n * I(in[2*N-1],out[1]); V(in[2*N],out[2]) <+ 1n * I(in[2*N],out[2]); end else if(i!=1) begin V(in[2*i-1],out[2*i-1]) <+ 1n * I(in[2*i-1],out[2*i-1]); V(in[2*i],out[2*i]) <+ 1n * I(in[2*i],out[2*i]); end end end endmodule

Figure 4. Verilog-A code of three channel switch component 73

ADS SI Simulation Q&A SI_Q&A_035

Question

How to calculate insertion loss, return loss and crosstalk of differential pairs in mixed mode S parameters?

Answer

Mixed mode S parameters are often used to examine frequency characteristics of differential pairs including insertion loss, return loss and balanced-unbalanced mode conversion. Typically, we can convert a four-ports single ended S parameters to mixed mode S parameters with equations as shown in figure 1. Or, we can make the conversion with simulation as shown in figure 2.

Figure 1. Formulas for mixed mode S parameters calculation

Figure 2. Mixed mode S parameters simulation

ADS SI Simulation Q&A

Figure 3. Mixed mode S parameters plot The formulas would be very complex to calculate differential mode to differential mode crosstalk between pairs. We can make use of S parameter simulation as shown in figure 4 to simplify the work. For example, S(5,1) is near-end crosstalk (NEXT) from upper pair to lower pair. S(6,1) is far-end crosstalk (FEXT) from upper pair to lower pair.

Figure 4. Crosstalk in mixed mode S parameters

Figure 5. NEXT and FEXT in mixed mode S parameters 75

ADS SI Simulation Q&A SI_Q&A_036

Question

Does ADS have signal analyses like those in oscilloscopes?

Answer

Oscilloscopes are the most commonly used test instrument for SI engineers. Oscilloscopes sample incoming analog signal and store digitized waveforms in memory for post processing. We can then examine signal waveforms forward and backward on instrument screen or zoom in for details. In addition, oscilloscopes can further process waveforms to get statistics of the waveforms, such as leveling, rising time, falling time, eye pattern, eye height, eye width, jitter, etc.

Oscilloscope

Eye_Probe and EyeDiff_Probe components in ADS offer various measurement items like oscilloscopes do. We don’t need to build complex formulas to calculate waveform statistics. We specify measurement items in probes and get reliable results when simulation is done, like figure 2-4. Note that probes are only compatible with Transient and ChannelSim simulators.

Figure 1. ADS Eye_Probe and EyeDiff_Probe Components

ADS SI Simulation Q&A

Probe Measurement Items: LevelMean HeightAtBER JitterRMS RiseTime CheckMaskViolation SNR Amplitude HeightDB FallTime WidthAtBER JitterPP Bathtub Waveform Contour CrossingLevel Level1 Height Level0 Width

Figure 2. Eye Pattern, Mask and Contour

Figure 3. Timing and Voltage Bathtub

Figure 4. Eye Statistics and Height/Width at BER There are many components in a SERDES system. How do we evaluate each component? Probes are effective tools to examine how a signal changes along a transmission path as shown in figure 5. We can easily figure out bottlenecks in a system by examining eye pattern, jitter or BER.

Figure 5. Examining SERDES design with multiple eye probes 77

ADS SI Simulation Q&A SI_Q&A_037

Question

Keysight ENA option TDR is used to convert measured S parameter to TDR. How can I get TDR impedance from an S parameter in ADS?

Answer

Keysight ENA option TDR is an one box measurement solution for high speed interconnect measurement, including impedance and S parameters as shown in figure 1. Keysight ENA option TDR measures frequency domain characteristics of an interconnect in S parameter. Then, the S parameter is used to calculate time domain impedance such as in TDR by inverse Fourier transform.

Figure 1. GUI of ENA TDR option Figure 2 shows an evaluation board with a 100 Ohm differential pair of 20 cm long. Middle of the 100 Ohm differential pair is a high impedance differential pair of 3.6 cm long. We have got a four port S parameter of the evaluation board from 10MHz to 10GHz. How do we compute TDR impedance from the S parameter in ADS? High Z

Figure 2. PCB layout of evaluation board

ADS SI Simulation Q&A ADS supports two ways to convert S parameter of channel to TDR. One way is by Transient simulation as shown in figure 3. Impedance variation of channel can be calculated by the voltage across source resistor, V1 and V2: Z=

Z0×V2 (Z0 is source impedance) (V1−V2)

Figure 3. TDR simulation by Transient

Peeling

Another way is by SP-TDR front panel as shown in figure 4. The frequency domain to time domain conversion is based on inverse Fourier transform. Interface of SP-TDR is like an instrument. Buttons at left side of panel offer various functions for TDR calculation. For example, “peeling” function can mitigate multi reflection induced by impedance mismatch to get more accurate impedance. “Smooth” function can remove measurement noise to enhance signal quality.

Extrapolation Window Gate Port Extension Smooth Sweep Impulse File Writer

Figure 4. SP-TDR Front Panel

79

ADS SI Simulation Q&A SI_Q&A_038

Question

How to debug a SERDES design with jitter analysis?

Answer

Jitter is timing variation of a digital signal. EZJit+, embedded in oscilloscope, is a powerful tool for jitter analysis and Bit Error Rate (BER) estimation. EZjit+ decomposes total jitter into different types of jitter, including Random Jitter (RJ), Periodic Jitter (PJ) and Data Dependent Jitter (DDJ). We can examine jitter histogram and statistics of each jitter type in EZJit+ as shown in figure 1.

Figure 1. Jitter analysis in EZJit+ Figure 2 shows a jitter tree and where jitter comes from. It provides us insights of a SERDES design. ADS Jitter Analysis Front Panel shown in figure3 enables jitter separation measurements as EZJit+. It can perform complete jitter analysis in design phase.

ADS SI Simulation Q&A

Total Jitter

Bounded Uncorrelated Jitter Deterministic Jitter

Data Dependent Jitter

Random Jitter (Noise)

Periodic Jitter (Crosstalk)

Inter Symbol Interference (Bandwidth) Duty Cycle Distortion (Asymmetric edges)

Figure 2. Jitter tree

Figure 3. ADS Jitter Analysis Front Panel Jitter Analysis Front Panel also supports jitter spectrum. Jitter spectrum shows spectral content of total jitter. It is useful for us to figure out jitter sources by their frequency components. For example, if we suspect a source of jitter is a switching signal with frequency of 66 MHz, we can test this assumption by examining jitter spectrum for a peak at 66 MHz as shown in figure 4.

Figure 4. Jitter spectrum shows a peak at 66MHz 81

ADS SI Simulation Q&A SI_Q&A_039

Question

How to export waveform files from ADS to Infiniium for eye and jitter analyses?

Answer

Infiniium Offline is a powerful oscilloscope analysis software. It could read waveform exported from ADS and perform various digital signal analysis. To generate Infiniium compatable waveform files in ADS, place an Infiniium Binary File Output component in schematic as shown in figure 1. Then, peform ChannelSim to calcualte waveform and clock at receiver. When simulation ends, two infiniium compatible binary files, ChannelSim1_Waveform _Eye_Probe1.bin and ChannelSim1_ClockSignal_Eye_Probe1.bin, will be generated. In Infiniium software, we can read the two files and examine waveform and clock as shown in figure 2.

Figure 1. Export Infiniium compatible waveform and clock files Infiniium provides powerful analyses for high speed digital signal including eye statistics, jitter seperation and compliance testing. For example, we can view an eye pattern based on simulated waveform and clock with Serial Data Analysis as shown in figure 3. Or, we can get jitter statistics, such as jitter separation, jitter histogram, jitter spectrum and BER bathtub, with EZJIT+ as shown in figure 4.

ADS SI Simulation Q&A

Figure 2. Read ADS simulated waveform and clock files in Infiniium

Figure 3. Build an eye pattern with Serial Data Analysis

Figure 4. Analyze jitter with EZJIT+ 83

ADS SI Simulation Q&A SI_Q&A_040

Question

How to read a waveform file of csv format in ADS for SI analysis?

Answer

CSV is a file format used for storing tabular data in a simple plaintext form. To view and analyze a waveform stored in a csv file, we have to read the file into a dataset.

Data Type: 0: int 1: real 2: string 3: complex 4: boolean 5: binary 6: octal 7: hexadecimal 8: byte16

Firstly, Add a header to the csv file to be read with a text editor. Add “BEGIN BLK” on top of csv file as shown in figure 1. Then, add “% time(1) voltage(1)” in second line to label left column data as time and right column as voltage. The “(1)” after “time” and “voltage” means data in the columns are real numbers. Now, we can start to read the file into a dataset.

Figure 1. Add a header on top of csv file Start Data File Tool (dftool) from a schematic view or a data display window in ADS. Data file tool is shown in figure 2. Then: 1. Select Read data file into dataset mode 2. Select MDIF file format to read 3. Select Generic MDIF as sub-type 4. Input file name to read 5. Input name of dataset to write 6. Click Read File button 7. If succeed, the dataset will show in the list of datasets

ADS SI Simulation Q&A

Figure 2. Read a waveform file into a dataset To calculate eye statistics of a waveform, an easiest way is to output the waveform from dataset into Eye_Probe as shown in figure 3. When simulation begins, VtDataset outputs voltage waveform stored in dataset and Eye_Probe captures the waveform for eye pattern calculation. When simulation ends, we can get eye pattern and eye statistics as shown in figure 4.

Figure 3. Output a waveform stored in dataset into Eye_Probe

Figure 4. Eye pattern and eye statistics of a waveform 85

ADS SI Simulation Q&A SI_Q&A_041

Question

How to build a compliance test report of DDR4 simulation?

Answer

As bit rate increases, DDR interconnect design and analysis becomes more and more challenging than ever for SI engineers. DDR4 bit rate is up to 3200 Mbps. Traditional metrics for signal integrity, such as setup time and hold time, are insufficient. To achieve consistent results with measurements, we can take advantage of DDR4 compliance test tool in Infiniium offline oscilloscope analysis software for simulated DDR4 signal analyses.

Figure 1 shows an example of DDR4 design which models Write operation. Waveforms of DQ and DQS as shown in figure 2 are captured at pins of DRAM. These waveforms are also written into files in .h5 format. We can then read the files in DDR4 compliance test tool as shown in figure 3 for compliance calculation. Figure 4 shows the compliance report when calculation ends.

Figure 1. An example of DDR4 design

ADS SI Simulation Q&A

Figure 2. Simulated DQ and DQS waveforms

Figure 3. DDR4 compliance test tool

Figure 4. DDR4 compliance test report 87

ADS SI Simulation Q&A SI_Q&A_042

Question

What are architectures of high speed SERDES transmitter and receiver?

Answer

Figure 1 shows typical physical layer architecture of SERDES Transmitter (Tx) and receiver (Rx). Tx includes encoding, parallel to serial, de-emphasis and differential driver. Rx includes differential receiver, Continuous Time Linear Equalizer (CTLE), Feed Forward Equalizer (FFE), clock recovery circuit, Decision Feedback Equalizer (DFE), serial to parallel and decoding.

Tx Encoding

Differential Receiver

Parallel to Serial

CTLE/FFE

De-Emphasis

DFE

Differential Driver

Serial to Parallel

D+

D-

Rx

Clock Recovery Circuit

Decoding

Channel Figure 1. Block diagram of SERDER Tx/Rx architectures

ADS SI Simulation Q&A In ADS, Tx_Diff and Rx_Diff components could be used to model Tx and Rx for high speed SERDES system planning. In Tx_Diff, there are function tabs including: • Waveform: Bit rate, Vhigh, Vlow and slew rate • Bit Pattern: LFSR, user defined sequence and bit file • Encoder: 8b/10b, 64b/66b, 128b/130b and 128b/132b • EQ: Taps, dB • Electrical: source impedance • Jitter: DCD, PJ and RJ In Rx_Diff, there are function tabs including: • EQ: CTLE, FFE and DFE • Electrical: load impedance • Jitter: RJ and amplitude noise Both FFE and DFE support three adaptive equalization methods as shown in figure 2. The three adaptive algorithms are: • LMS (Least Mean Square) • RLS (Recursive Least Squares) • ZF (zero forcing)

Figure 2. Equalization method setup window System level simulation is important when building a high speed SERDES system. Tx_diff and Rx_diff are useful components when planning a high speed SERDES system. We can adjust parameters in Tx_diff/Rx_diff components easily and perform ChannelSim simulation to examine system performance, such as BER and jitter, in minutes. 89

ADS SI Simulation Q&A SI_Q&A_043

Question

What is Inter Symbol Interference (ISI)?

Answer

Loss of a transmission line is frequency dependent. In general, loss increases as frequency increases. Conductor loss and dielectric loss of substrate are main contributors to loss of a transmission line. To estimate loss of a transmission line, we can assign material properties of substrate and physical size of a transmission line as shown in figure 1. Performing an S Parameter simulation, we will get insertion loss versus frequency as shown in figure 2.

Figure 1. Insertion loss simulation of a transmission line

Figure 2. Frequency dependent insertion loss of a transmission line

ADS SI Simulation Q&A We excite a 100ps impulse to a transmission line as shown in figure 3. In figure 4, the left diagram shows slew rate of output impulse response becoming slower. Compare spectrum of impulse with impulse response, we can see that loss of high frequency components of the impulse response is greater than loss of low frequency components as shown in the right diagram of figure 4.

Figure 3. Impulse response simulation Input Impulse

Output Impulse Response

Figure 4. Impulse/impulse response (left) and their spectrum (right) Label one Unit Interval (UI) on the output impulse response. Center of the symbol could be at peak of the symbol as shown in figure 5. We can then find that interference labeled in red regions penetrating to adjacent symbols. It explains what Inter-SymbolInterference means. ISI is the most critical factor impacting performance of a SERDES design.

Figure 5. Interference penetrating to adjacent symbols 91

ADS SI Simulation Q&A SI_Q&A_044

Question

How does pre-emphasis work to improve a high speed digital signal?

Answer

When a high speed digital signal travels through a lossy channel, the signal edges deteriorate with the loss of high frequency signal components as shown in right diagram of figure 1. It results in inter-symbol-interference (ISI) and a closing eye. To mitigate high frequency loss, one way is to use a pre-emphasis circuit in the transmitter (TX). Pre-emphasis circuit operates by boosting high frequency energy every time a transition occurs as shown in left diagram of figure 2 left. It compensates high frequency loss of signal at receiver (RX) and improves signal quality as shown in right diagram of figure 2.

TX

RX

Figure 1. High frequency loss results in signal deterioration at RX

TX

RX

Figure 2. High frequency compensation with pre-emphasis

ADS SI Simulation Q&A unit delay

C0

C1

unit delay

C2

Figure 3. Three taps pre-emphasis circuit architecture A pre-emphasis circuit can be constructed from a multi-taps finite impulse response (FIR) filter as shown in figure 3. We can set up tap values (C0, C1, C2) to adjust boosting levels. In ADS, Tx_Diff and Tx_SingleEnded components allow users to input tap values as shown in figure 4. Figure 5 shows eye diagrams with pre-emphasis disabled and pre-emphasis enabled. We can see that eye of the signal gets improved with pre-emphasis.

Figure 4. Set up pre-emphasis in Tx_Diff component

Figure 5. pre-emphasis disabled (left) pre-emphasis enabled (right) 93

ADS SI Simulation Q&A SI_Q&A_045

Question

How does Continuous Time Linear Equalizer (CTLE) work to improve a high speed digital signal?

Answer

CTLE is an analog filter in a receiver (RX). It could be an active or a passive circuit. When a high speed digital signal propagates through a lossy channel, RX CTLE is used to boost high frequency components of the signal to compensate high frequency channel loss. We used to model behavioral of a CTLE by a transfer function. For example, transfer function of USB3.0 CTLE for long channel is: 𝐻 𝑠 =

𝐴𝑑𝑐 𝜔𝑝1 𝜔𝑝2 𝑠 + 𝜔𝑧 ∙ 𝜔𝑧 (𝑠 + 𝜔𝑝1 )(𝑠 + 𝜔𝑝2 )

Where 𝐴𝑑𝑐 =0.667 𝜔𝑧 =2π× 650MHz 𝜔𝑝1 =2π× 1.95GHz 𝜔𝑝2 =2π× 5GHz Figure 1 shows transfer function of the CTLE:

Figure 1. Transfer function of USB3.0 CTLE for long channel

ADS SI Simulation Q&A Figure 2 shows step response of the CTLE. We can see that signal level at transition edge are boosted by CTLE. In ADS, Rx_Diff and Rx_SingleEnded components allow users to input poles and zeros of CTLE transfer function as shown in figure 3. Left diagram of figure 4 shows eye with CTLE disabled. Right of figure 4 shows eye with CTLE enabled. We can see that eye of the signal gets improved with CTLE.

Figure 2. Step response of the CTLE

Figure 3. Set-up poles and zeros of the CTLE transfer function

Figure 4. Eyes with CTLE disabled (left) and CTLE enabled (right) 95

ADS SI Simulation Q&A SI_Q&A_046

Question

How does Feed Forward Equalizer (FFE) work to improve a high speed digital signal?

Answer

An FFE is a tapped delay line circuit that produces a delayed and weighted sum of an input signal. FFE is widely used in a SERDES receiver (RX) to mitigate Inter-Symbol-Interference (ISI) caused by a lossy channel. Figure 1 shows a three-taps FFE example. Tap values C0, C1 and C2 are optimized to minimize ISI.

Input Impulse Response

TX

Channel

RX

unit delay

C0 -0.11

unit delay

C1 0.65

C2 -0.24 Output Impulse Response

Figure 1. A three taps FFE example

---------Input Impulse Response Output Impulse Response

Main Symbol

Pre-Symbol

1UI

1UI

Post-Symbol

Figure 2. Output impulse response of FFE has zero interference at pre-symbol and post-symbol sampling points

ADS SI Simulation Q&A In this example, tap values are -0.11, 0.65 and -0.24. The first tap is used to minimize pre-ISI. The second tap is used to adjust main signal level. The third tap is used to minimize post-ISI. Note tap values here are normalized, where |C0|+|C1|+|C2|=1. The output impulse response of the DFE has zero interference at sampling points of pre-symbol and post-symbol as shown in figure 2. In a channel simulation as shown in figure 3, Rx_SingleEnded and Rx_Diff components allow users to enable “optimized initial tap calculations” as shown in figure 4. When simulation ends, optimal tap values will be written into a text file. Left diagram of Figure 5 shows eye patterns of FFE disabled and right diagram of figure 5 shows eye pattern with FFE enabled. We can see that eye pattern gets improved with FFE.

Figure 3. A Channel Simulation

Figure 4. Enable optimization for tap values of the FFE

Figure 5. Eye with FFE disabled (left) Eye with FFE Enabled (right) 97

ADS SI Simulation Q&A SI_Q&A_047

Question

How does Decision Feedback Equalizer (DFE) work to improve a high speed digital signal?

Answer

DFE is commonly used in SERDES receiver (RX) to remove Inter Symbol Interference (ISI) caused by a lossy channel. A DFE includes a Finite Impulse Response (FIR) filter, a summer and a slicer for symbol decision. Figure 1 shows a three taps DFE example. The pro of DFE is that it can cancel ISI without noise amplification. The con is that it can’t correct precursor ISI.

0100… summer C2 -0.033

FIR

slicer

C1 -0.073 Latch

C0 -0.223 Latch

Latch

Figure 1. A three taps DFE example

0.223 0.073

ISI Cancelled 0.033

Figure 2. Input impulse (left), output impulse response (right)

ADS SI Simulation Q&A Firstly, ISI from previous symbols are calculated with FIR. Then, the interference would be subtracted from incoming signal. Finally, slicer makes a symbol decision and output the symbol back to FIR. Tap values are selected to minimize ISI. In this example, tap values are -0.223, -0.073 and -0.033. Figure 2 shows that interference at sampling points of post symbols are removed. In a channel simulation as shown in figure 3, Rx_SingleEnded and Rx_Diff components allow users to enable “optimized initial tap calculations” for DFE as shown in figure 4. When simulation ends, optimal tap values will be written into a text file. Left diagram of Figure 5 shows eye patterns of DFE disabled and right diagram of figure 5 shows eye pattern with DFE enabled. We can see that eye pattern gets improved with DFE.

Figure 3. A Channel Simulation

Figure 4. Enable optimal DFE taps calculation

Figure 5. Eye with DFE disabled (left), Eye with DFE Enabled (right) 99

ADS SI Simulation Q&A SI_Q&A_048

Question

What are high frequency characteristics of a real capacitor?

Answer

Capacitors are widely used in power distribution network (PDN) designs. Equivalent circuit of a real capacitor is an ideal capacitor in series with an inductor and a resistor as shown in figure 1. At low frequency, behavior of a real capacitor is close to an ideal capacitor as shown in figure 2. As frequency going higher to self resonant frequency, the capacitor behavior deviates from an ideal capacitor. When frequency is higher than self resonant frequency, the capacitor is more like an inductor rather than a capacitor. Therefore, it is important to understand self resonant frequency of a capacitor before using the capacitor in PDN designs.

Figure 1. Equivalent circuit of a real capacitor 1 2𝜋𝑓 × 𝐶𝑎𝑝

𝑍 ≈ 2𝜋𝑓 × 𝐸𝑆𝐿

log|Z|

𝑍 ≈

Real capacitor 𝑍 ≈ 𝐸𝑆𝑅

Ideal capacitor

Self resonant frequency

log|f| Figure 2. Frequency characteristics of a real capacitor

ADS SI Simulation Q&A Impedance parameters or Z parameters are properties used to describe behavior of a linear electrical network, such as PDN. Z parameters simulation in ADS is an useful tool to examine frequency response of a capacitor. For example, three TDK™ 1005X7R type capacitors of capacitance 1nF, 4.7nF and 100nF are simulated as shown in figure 3. Simulated Z parameters of the three capacitors are shown in figure 4. Generally, self resonant frequency and ESR of a high capacitance capacitor is smaller than that of a low capacitance capacitor. It is important to note that different capacitor types of the same capacitance might have different ESL and ESR. We have to be careful when replacing a capacitor with another type capacitor in a PDN design.

Figure 3. Z Simulation of 1nF, 4.7nF and 100nF capacitors

1 nF 100 nF

4.7 nF

Figure 4. Z parameters of 1nF, 4.7nF and 100nF capacitors. 101

ADS SI Simulation Q&A SI_Q&A_049

Question

How to import vendor component libraries and use those components in a design?

Answer

To get accurate simulation results in an SI simulation, it is necessary that all components in the design are accurate. At high frequency, every component has its own parasitic effects. These effects impact simulation results. For example, Equivalent Series Resistance (ESR) and Equivalent Series Inductance (ESL) are important parasitic effects of a real capacitor. Figure 1 shows a Z parameter simulation of an ideal 0.1uF capacitor, a Murata™ GRM0806X75 0.1uF capacitor and a TDK™ 1005X7R 0.1uF capacitor. Although these three capacitors have the same capacitance of 0.1uF, the high frequency behaviors are very different as shown in figure 2.

Figure 1. Z simulation of ideal, Murate and TDK 0.1uF capacitors ADS Vendor Component Libraries webpage as shown in figure 3 lists all libraries provided by component vendors. These vendor components are wideband accurate and updated regularly. We can click link to visit vendor’s official website and download latest version of component library for SI design.

ADS SI Simulation Q&A

Murata

Ideal TDK

Figure 2. Z parameters of ideal, Murata and TDK 0.1uF capacitors

Figure 3. ADS Vendor Component Libraries webpage In ADS main window, select DesignKits > Unzip Design Kit to install a component library. Then, we can use the components of the library as well as ADS native components in a schematic. An ADS workspace might include multiple vendor component libraries. To view included libraries, select DesignKits > Manage Libraries to open the Manage Libraries window as shown in figure 4. We can add or remove libraries in this window.

Figure 4. Viewing included libraries in Manage Libraries window 103

ADS SI Simulation Q&A SI_Q&A_050

Question

How to model a power distribution system?

Answer

A power distribution system delivers power from a Voltage Regulator Module (VRM), through a Power Distribution Network (PDN) to IC chips in an electrical system. A block diagram of an example power distribution system is shown in figure 1. It is for a 1.8 volt VRM delivering power to a IC chip. This chip includes five circuit blocks: digital core, analog core, digital PLL, analog PLL and band-gap. The PDN connects the VRM with the five blocks. To avoid voltage fluctuation in PDN, there are multiple decoupling capacitors deployed in power distribution network as shown in figure 2. In addition to decoupling capacitors, EMI filters, ferrite beads and inductors are commonly used to block high frequency noise in a power distribution system.

1.8V VRM

DVdd - Digital Core Avdd - Analog Core PVdd - Digital PLL PLVdd - Analog PLL BGVdd - Band-gap

EMI Filter EMI Filter

DVDD

PVDD

EMI Filter

BGVDD

EMI Filter

AVDD

IC CHIP

PLVDD

Figure 1. Block diagram of an example PDN

ADS SI Simulation Q&A

Figure 2. Decoupling capacitors and inductors deployed on a PDN Figure 3 shows PCB layout of the PDN. In general, PCB layout of a PDN is complicated. To analyze a power distribution system in ADS, we have to extract S parameters of the PDN with momentum-RF EM solver. Then, we can combine S parameters of the PDN with components such as voltage sources, decoupling capacitors, etc. to model the power distribution system as shown in figure 4.

Figure 2. Figure 3. 3D view of a PDN PCB layout

S Parameters of PDN

Figure 4. Modeling a power distribution system in ADS 105

ADS SI Simulation Q&A SI_Q&A_051

Question

How to analyze impedance of a Power Distribution Network (PDN)?

Answer

Impedance of a PDN is defined as that seen from power terminals of an IC chip. If impedance is higher than target impedance, voltage fluctuation at the power terminals will be out of safe range. It could damage the chip and even crash the system. Therefore, impedance is important when designing a PDN. Figure 1 shows a block diagram of a power distribution system for an IC chip. The chip includes five circuit blocks and these five blocks share the same VRM through a PDN. Figure 2 shows model of the power distribution system. To analyze impedance seen from terminals of the five blocks, Term components are connected to terminal ports of the five blocks in the PDN.

Z

IC Chip

DVdd - Digital Core Avdd - Analog Core PVdd - Digital PLL PLVdd - Analog PLL BGVdd - Band-gap

Figure 1. An example of power distribution system In S parameters simulator, enable Z-parameters calculation as shown in figure left. Then, we can perform simulation to get impedance profiles seen from terminals of the five blocks as shown in figure 3 and figure 4. In general, Z impedance profiles are plotted on an XY chart in log-log scale.

ADS SI Simulation Q&A

S Parameters of PDN

Figure 2. Examine impedance of a PDN with Term components In power integrity design, decoupling capacitors (decap) are commonly used to minimize impedance of a PDN. Figure 3 shows impedance of the PDN with all decaps disabled. The impedance can’t meet target impedance requirement at high frequency. Figure 4 shows impedance of the PDN with all decaps enabled. We can see that impedance are minimized and meet target impedance requirement across frequency band.

Target Impedance

Figure 3. Impedance profile of the PDN with all decaps disabled

Target Impedance

Figure 4. Impedance profile of the PDN with all decaps enabled 107

ADS SI Simulation Q&A SI_Q&A_052

Question

How to select decoupling capacitors to meet target impedance of a PDN efficiently?

Answer

In a general power distribution system design, several to dozens decoupling capacitors are used to minimize impedance of the PDN. Large capacitors are used to minimize impedance at low frequency band. Small capacitors are used to minimize impedance at high frequency band. Figure 1 shows an example PDN with twenty seven decoupling capacitors mounted. The problem is how to find out an optimal combination of capacitors to make impedance of PDN achieving target impedance requirement efficiently?

S Parameters of PDN

Figure 1. An example PDN with all decaps to be tuned Optimization is an effective and efficient tool to resolve the problem. To perform optimization, we have to select Discrete Optimization Settings mode of every capacitor to be tuned. In addition, we have to set up goals in GOAL components as shown in figure 2. For example, mag(Z33) < 0.3 means impedance seem from power terminal 3 is expected to be less than 0.3 Ohm after optimization. Multiple goals are allowable in optimization.

ADS SI Simulation Q&A

Figure 2. Optimization controller and Goals Click optimization button will open Optimization Cockpit as shown in figure 3. All capacitors are tuned by optimization engine iteratively to achieve goals as closer as possible. Optimization process takes seconds to minutes in general. When optimization ends, we can update variables to schematic and examine the optimized results in data display. Figure 4 shows the impedance profiles before and after optimization.

Figure 3. Optimization Cockpit

Target Impedance

Target Impedance

Figure 4. Impedance profiles before and after optimization 109