V Semester B.E. (E&C) Degree Examination, January 2013 (Y2K6 Scheme) EC 503 : DIGITAL SYSTEM DESIGN USING HDLS Time : 3 Hours
Max. Marks : 100
Instruction : Answer any five full questions selecting at least two from each Part. PART – A 1. a) What are PLDs ? Differentiate between FPGAs and CPLDs.
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b) With the example explain Entity and Architecture in VHDL.
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c) Write a VHDL code for 4 : 1 multiplexer using with signal select statement.
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d) Differentiate between signals and variables.
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2. a) Write a VHDL code to implement the sequence
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1 → 3 → 5 → 4 → 11 → 9 → 1 repeat b) Write a Structural Description for Full adder using two Half adders.
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c) What are Packages and Libraries in VHDL ?
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3. a) Write a function to convert 4-bit Binary to Integer.
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b) With the state graph of Binary multiplier control, write the behavioral model for 4×4 Binary multiplier.
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c) What are the difference between signals and variables ?
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4. a) Design and explain the operation of Array Multiplier.
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b) With the block diagram explain the operation of multiplication of two floating point numbers.
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PART – B 5. a) Write a SM chart to implement the function Y = A + BC i) By checking the expression directly ii) By checking individual variables. b) Design and explain the operation of Dice Game using SM chart and hence write the VHDL code. c) Realize the Boolean Expression for the SM chart shown below.
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6. a) Differentiate between Moore and Mealy State Machine.
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b) Write a VHDL Description for four bit up/down counter.
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c) Write a VHDL description for four bit shift register in the following modes of operation. i) SISO ii) SIPO iii) PIPO
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7. a) Write a VHDL model for Static RAM structure. b) Write an SM chart for simplified 486 Bus interface.
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8. a) Design BCD to Excess-3 code inverter using state machine and implement using ROM structure. 12 b) Implement the following functions using PLA. F0 = ∑ m(0, 1, 4, 6) F1 = ∑ m(2, 3, 4,6, 7 ) F2 = ∑ m(0, 1, 2, 6) F3 = ∑ m(2, 3, 5, 6, 7 )
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6. a) Design a twisted ring counter using 4 bit shift register. 4. b) Design and implement a synchronous BCD counter using JK flipflops. 10. c) Design a MOD â 11 ...
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