PG – 412

*PG412*

IV Semester M.Sc. Degree Examination, June/July 2014 ELECTRONIC SCIENCE EL-401 : VLSI Technology Time : 3 Hours

Max. Marks : 80

Instructions : 1) Part – A : Answer all questions. 2) Part – B : Answer any four full questions. PART – A

(4×5=20)

1. Compare CMOS and BiCMOS technologies. 2. Compare the performance of an NMOS inverter with a CMOS inverter. 3. Define sheet resistance. Determine the resistance of the transistors in a CMOS inverter. 4. Write a note on CMOS domino logic circuits. 5. Why is testing important in ICs ? Write a note on design for testability. PART – B 6. a) Using band diagrams explain what is meant by inversion layer in MOS transistors.

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b) Give the expression for threshold voltage. Explain each term.

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c) For a p substrate doping Na = 1015 cm–3, calculate the threshold voltage. DATA: ε r (silicon) = 12, ε r (oxide) = 4, tox = 90A°, ni = 1.5*1010 cm–3, ε 0 = 8.85*10–14 F/cm.

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7. a) Sketch the CMOS transistor level schematic for computing the function

y = (A + B).C . Draw the stick diagram.

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b) Give the truth table of a 4-input multiplexer. Draw the circuit with transmission gate.

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c) What are design rules ? Explain λ based design rules. What are the merits and demerits of λ based rules ?

4

P.T.O.

PG – 412

-2-

*PG412*

8. a) Explain clearly how inverters are cascaded to drive large capacitive loads. Calculate the delay for a chain of N CMOS inverters. b) An off chip capacitance of 3pF is to be driven by CMOS inverters. Calculate the number of stages. Draw the circuit and clearly indicate the dimensions of the transistors. Assume Cg = 0.06 pF. Calculate the delay.

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9. a) From first principle determine the effect of scaling on the following : i) Current density ii) Gates/unit area iii) Power dissipation/gate iv) Power dissipation/unit area.

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b) Determine the substrate doping scaling factor for devices working at low voltages.

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c) What is sub-threshold current ? Explain the effect of sub-threshold current on scaling.

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10. a) Explain the terms controllability, observability and fault coverage. b) Explain the scan path method of testing sequential circuits. 11. Write short notes on any three : a) Latch up in CMOS circuits b) Construction and working of a pMOS enhancement transistor c) CMOS inverter delay estimation d) Fabrication of CMOS inverter using p-well process e) Important ground rules for a successful design. ———————

7 8 (3×5=15)