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USN 1)
Seventh Sernester
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egree Exa rni n atiblf}-uilUffi Iy
DSP Algorithms and
20
Architecture fu{ax. Marks:i00
Time: 3 hrs.
-b. List the major architecturai
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With a neat block diagram explain about the saturation logic and its use. (06 Marks) Briefly explain about the 4 x 4 Braun multiplier with its structure" In n x n paratrletr multiplier structure how many adders are required? (08 Marks) With a neat block diagrarn, explain address generation unit oflDSP systern. (86 Marks)
c" 3 a. b.
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of
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motarala fixed point DSP devices"
TMS320C54XX processor with
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a neat (05
block
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Consider that AR3 is selected as the pointer for the circular buffer. The va;'ious rogister contents are Btr:40, AR-?: 1020H, ARO:0025H. Find: i) star't and en
Explain the operation of serial input/outputs ports and hard ware timer of TMS320C54XX on chip peripherals. Differentiate between MAC and MACD instruction by way of expiaining
b. c. By means of a figure, show the pipeline
them.
{SB
Marks}
(s4 klarks)
operation of the foliowing sequetlce of TMS320C54XX instruction. Assurne initial value of AR3 is 80h and the values. siored in memory locations 80h, 81h, 82h as 1,2 and 3
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Describe the rrultiplice/address unit
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Compare architectural features of TMS320C25
diagram.
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Explain the decimation and interpolation with equation. Let x(n) : 13, 2, -2, A,71. It is interpolated using an interpolation filter bp : [0.5, 1, 0.5] urith interpolation factar-Z" Determine the interpolation sequence. {S8 Marhs)
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PART A
An analog signal is sampled at the rate of 8 KF{2, if 512 samples of the signal are used to compute DFT, X(k), determine the analog and digital &equency spacing between adjacent X(k) elements. .Also determent aniilog and digitaX frequencies corr,lsFonding to k: 6t,.
g.
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m
Note: Answer any FIVE fwll qwestionso selectimg atlesst TWO questions fronc esck part"
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PART'= B What do you mean by Q-notations used in DSP aXgorithn'l implementation? What are the values represented by 16 bit numbers N : 4000h, in Qq5, Qz and Q6 natations? {08 Marks) Write an assembly language program fcr TMS32054XX processor to rnuitiply two Q15 numbers to produce Qrs resuit. {S5 Marks} With the help of a block diagram, explain the implementation of an FIR filter in TMS320C54XX processor. Show the memorSr organization for the filter impleraentation.
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(s7 Marksi
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a. b.
Why zero padding is done before computing the DFT? (02 Marks) Explain an 8-point DIT-DFT implementation structure based on the butterfly on the
c.
Determine optimum scaling factor to prevent over
(08 Marks) (10 Marks)
a. b.
Draw the I/o interface tirning diagram for read-write-read sequence of operation. (06 Marks) Design an interfa.ce to connect a 64kx16 flash memory to a TMS320C54XX device. The processor address bus is Ao to Ars. (06 Marks) What are intemrpts? I{ow inter:upts are handled by the C54XX DSP processor? (sB Marks)
b.
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co
Describe with a suitable diagram a digital model for production of speech
signal.
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Expiain with a neat diagram, the synchronous serial interface between the C54XX and a CODEC device, {05 PIarks) Explain the operation of pulse position rnodulation (PPM) to encode two biomedical signais.
g.
8a.
flow.
lo
c.
TMS320C54XX.
2 af2
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(08 Marks) (0d Marks)
