Dynamics of a Logarithmic Transimpedance Amplifier Arindam Basu∗, Kofi Odame† and Paul Hasler‡ School of Electrical and Computer Engineering Georgia Institute of Technology, Atlanta, Georgia 30332–0250 Email: ∗ [email protected];†[email protected]; ‡ [email protected] Abstract— We analyze the dynamics of a logarithmic transimpedance amplifier that are not explainable from its smallsignal model. The amplifier was used both to measure pixel currents in an imager as well as currents from a floating gate array for accurate programming. We explain the marked asymmetry between the up-going and down-going current steps intuitively using circuit concepts and then based on phase-plane analysis. This analysis also helps develop a method of reducing the huge delay to down-going current steps.

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I. L OGARITHMIC T RANSIMPEDANCE A MPLIFIER

1-4244-0921-7/07 $25.00 © 2007 IEEE.

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High dynamic range current processing generally requires some form of compression at the front-end to ease the design of the following stages or sometimes just to make the interfacing physically possible, logarithmic compression being most popular. The traditional implementation of this logarithmic IV conversion is done by a passing the current into a diode, a BJT, or MOSFET operating in its subthreshold, exponential region of operation. The problem with these elements is that the small signal bandwidth at low currents is limited, since the Gm of these elements is set by the input current. The approach then becomes one of using an amplifier in a feedback loop, as in Fig. 1, thus increasing the bandwidth by the amplifier gain, A from Gm /C to AGm /C. Fig. 1 shows the structure of our common-drain logarithmic amplifier similar to [1], [2]. M1-M5 form a basic differential amplifier which can be replaced by any other amplifier like a folded-cascode. The NMOS M6 in the feedback path operates in subthreshold giving the logarithmic transimpedance property. Another diode connected MOS can be added in series with M6 to increase the sensitivity of the output. The amplifier tries to hold the input node to a constant voltage forcing the input current to flow through the feedback transistor and speeding the response. But interestingly enough, it is seen that the amplifier cannot really speed up the response to large down-going current steps while the up-going step is fast, a result not predicted by small-signal analysis. In this paper, we explain this marked asymmetry in step response and also suggest methods of alleviating this problem. It should be noted that in many applications the signal the amplifier faces is a large current step. For example, while scanning through pixels in an imager, transition from a bright to a dark pixel represents this condition. In that case the settling time of this transimpedance stage sets the maximum clock frequency that could be used which underlines the importance of this analysis. In section II, we present an intuitive explanation of this phenomenon based on circuit concepts.Section III, explains

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(b) Fig. 1: Logarithmic Transimpedance Amplifier: (a) The NMOS in the feedback operates in subthreshold region giving the logarithmic compression of currents. The amplifier holds the input node nearly constant speeding up the response. (b) A measured step response showing that the down-going step is much slower than the up-going step.

the same results from a large signal analysis of this structure using phase-plane method. In section IV, we present possible solutions to remove the unwanted delay. Finally we present the conclusions in the last section. II. I NTUITIVE A NALYSIS An intuitive explanation of the problem is obtained by noticing that the step response of the source follower(commondrain) is essentially asymmetric. When there is a sudden increase in the input current(at a rate faster than amplifier’s bandwidth), the voltage at the input node of the amplifier(Vin) reduces initially as CS provides the extra current. The amplifier slews and charges its output at the rate of Iref /CL and pulls up the input node via the source follower action of the feedback transistor. On the other hand when there is a sudden decrease in input current, Vin increases initially as

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Fig. 2: Parametric Analysis(a) Step responses obtained when input current steps from 100nA to I1, with I1 varying from 10pA to 100pA. Iref is fixed at 128nA. (b) Responses obtained when input current steps from 100nA to 10pA with Iref fixed at 128nA. CF varies from 10fF to 100fF. (c) Step responses obtained when input current steps from 100nA to 10pA with CL fixed at 300f. Iref varies from 128nA to 500nA. (d) Responses obtained when input current steps from 100nA to 10pA with Iref fixed at 128nA. CL varies from 10fF to 100fF.

CS gets charged by the source follower. The amplifier then starts discharging CL by Iref . But even if this rate is fast, the amplifier can at most shut off the feedback transistor and cannot provide extra pull-down current. Vin can reduce to its equilibrium value only when CS is discharged by Iin as the feedback transistor is OFF. But the input current is very low which means that the time required to settle is very long in this case.

Miller capacitance at the input also increases correspondingly. Fig. 2(c) demonstrates that increasing Iref helps in reducing the undershoot by increasing the capacitive current due to enhanced slew rate. Fig. 2(d) shows the effect of varying CL . Lower values of CL translate to a higher slew rate leading to a larger feedthrough current to Vin resulting in faster settling. In the next section we present a more rigorous mathematical explanation of this asymmetry from a phase-plane analysis.

The presence of CF helps the response because it provides a high frequency capacitive feed-through current reducing the change at Vin . Thus it acts as a path parallel to the transistor active at high frequencies. But this acts as a Miller-capacitor, appearing as ACF at the input when the amplifier enters linear region, reducing the small signal bandwidth for all cases considerably. Fig. 2(a) shows the difference in the rate of increase of Vout when the lower current value is varied indicating that the delay in the output reaching steady-state is indeed due to charging of CS +ACF .

To obtain the large signal equations for the system in fig. 1, we model the amplifier as a Gm stage with characteristics given by :

Fig. 2(b) shows that putting CF helps prevent the undershoot as the capacitive feedthrough current, CF dVout /dVin increases. However the final settling time increases as the

where κ is the inverse of subthreshold slope of a MOS [3], UT is equal to kT /q and Iref is the tail current in the amplifier. We consider κ to be 1 in the following analysis for simplicity.

III. P HASE P LANE A NALYSIS

Iout = Iref tanh((κ/2UT )(Vref − Vin )),

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Fig. 3: Step response based on simplified differential equations: (a)Phase portrait and temporal response of the system under down-going step showing long settling time (b) Phase portrait and temporal response to up-going step is much faster.

The nodal equations for this system are: Vout −Vin dVin d(Vout − Vin ) = CF + I0 e UT − Iin (2) dt dt
 Vref − Vin dVout d(Vin − Vout ) = CF + Iref tanh CL dt dt 2UT (3)

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Let the input current step be from Iin1 to Iin2 and define Iin0 = √ Iin1 Iin2 , M = Iin1 /Iin2 and c = (Iref /CL )(CS /Iin0 ). For dimensionless formulation of the problem, we make the following substitutions: x=

δVin δVout t × Iin0 ;y = ;τ = , UT UT CS × UT

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where δV represents the change in variable V from its steady state value. We first consider CF to be 0 and then consider its effect as a perturbation to the solution. Also, as typically the step change in current is much faster than the amplifier’s response, we consider that at t=(0+) the current in the transistor is at its previous value while the current source has changed its value. Under the above assumptions, the simplified node equations

(considering change in absolute variable values) become: 1 dx = M × ey−x − (5) dτ M dy = −c × tanh(x/2) (6) dτ For a down-going step M is a large number while it is a small fraction for an up-going step. c represents in a small-signal sense how far the amplifier’s output pole is compared to the input pole. (0,-2ln(M)) is a stable fixed point. The system starts from the origin. For an up-going step x becomes negative initially while the opposite occurs for the down-going case. Now, for the up case the exponential in (3) brings it back to x=0 quickly. But for the down going step the phase point can approach x=0 only at the rate 1/M as the minimum value of the exponential tends to zero. Fig. 3 (a) and (b) show the temporal response and phase portrait for the two steps obtained from MATLAB based on the differential equations. The parameter values were c=30 and M =.05 for the up-going step and M = 20 for the down-going one. The behavior near the fixed point can be obtained from the eigenvalues of the Jacobian. Now, if we introduce CF , the node equations become:   CS (CF + CL ) 1 dx y−x = − Me − dτ CII M CF CS Iref tanh(x/2) (7) CII Iin0

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CS (CS + CF ) Iref dy =− tanh(x/2) − dτ CII Iin0   CS CF 1 M ey−x − CII M

where CII is CF CS + CF CL + CL CS . We can see that now due to the coupling of the input and output nodes through CF , the minimum value of the derivative of x is no longer limited to 1/M. But also the additional term in the equation for dy dτ slows the output. CF thus acts like a damping to the response. It can be seen that the reason for the delay is that the exponential in (6) is not an odd function. In other words it can only have a large positive value and not a negative one. Thus the solution would be to use an element which has an I-V relation like a sinh() so that a symmetry can be maintained in the two transitions.

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We analyzed the dynamics of a common-drain logarithmic transimpedance amplifier in this paper. The response to a down-going current step was found to be much slower than the up-going one, the reason being that the I-V relation of the source-follower stage in the feedback was asymmetric. Thus the amplifier could not affect the settling of the input node for down-going steps. A method to alleviate this problem is found in using an additional element in the feedback with I-V characteristics similar to an antiparallel diode pair.

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(b) Fig. 4: Bidirectional Element: (a) An element with an expansive non-linearity is shown. It is PMOS with gate connected to drain and bulk connected to source. Its measured I-V characteristics are like that of anti-parallel diodes. One terminal was at 2V while the other was swept. (b) Schematic of the amplifier with the bidirectional element added in feedback across the amplifier. 1.95 No feedback Bidirectional feedback

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As mentioned in the previous section, the main problem responsible for the asymmetry is that the amplifier cannot control both charging and discharging of the input node. So we require an element in feedback that can source and sink currents. Also it should not affect the I-V conversion over a reasonable range of inputs. An antiparallel diode pair fits this requirement. A compact implementation of such a functionality is also shown in [1] which uses the parasitic BJT in a CMOS process. It is a PMOS with gate-drain and bulksource terminals connected. Thus when the potential difference across its ends is small, both the MOS and the BJT are off. When the potential difference increases sufficiently, one of them starts conducting depending on the polarity of the potential. Fig. 4(a) shows the schematic of this element and its measured I-V relation where one end was set to 2V and the voltage at the other end was swept. Two of these elements are used to increase the voltage range for which it is off. This element was also placed in feedback along with the normal common-drain NMOS across the input-output of the gain stage as shown in Fig. 4(b). Fig. 5 compares two step responses with and without this element which demonstrates the advantage of this approach. But it should be noted that this results in more noise and error in the current measurement, specially at the lower end. Another approach is to use a common-drain PMOS also in feedback so that the transimpedance amplifier can process bi-directional currents.

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Fig. 5: Speedup of down-going step:Step responses obtained when input current steps from 100nA to 10pA with CL =300f and CS =10fF. One case has a bi-directional element in feedback to provide extra current in transient.

R EFERENCES [1] T. Delbruck and C.A. Mead, ”Adaptive photoreceptor with wide dynamic range,” IEEE International Symposium on Circuits and Systems, Vol. 4, pp. 339-342, June 1994. [2] J. Kramer, ”An integrated Optical Transient Sensor,” IEEE Trans. on Circuits and Systems II, vol.49, no. 9, pp. 612-28, Sept. 2002. [3] Y. Tsividis, Operation and Modeling of the MOS Transistor, 2nd ed. Boston,MA:McGraw-Hill, 1998.

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