PROJECT REPORT ON

MULTI UTILITY SENSOR NETWORK HARDWARE DESIGN SUBMITTED BY

ANURAG CHUGH RICHA TEWARI ROHAN RAGHUNATH

CHARUTA AMBARDEKAR SHWETA ARVIND SARAF

UNDER THE GUIDANCE OF

ASST. PROF. MR. ABHAY H. KSHIRSAGAR DEPARTMENT OF ELECTRONICS VIVEKANAND EDUCATION SOCIETY’S INSTITUTE OF TECHNOLOGY, CHEMBUR – 71 UNIVERSITY OF MUMBAI 2005 - 2006

Vivekanand Education Society’s Institute of Technology Project Report On

Multi Utility Sensor Network Hardware Design Submitted by

Anurag Chugh Charuta Ambardekar Richa Tewari Rohan Raghunath Shweta Arvind Saraf Under the Guidance of

Asst. Prof. Mr. Abhay H. Kshirsagar In partial fulfillment of the requirement of the degree of bachelor of engineering in electronics of the University of Mumbai, Maharashtra state Department of Electronics VES Institute of Technology, University of Mumbai 2005 – 2006

Vivekanand Education Society’s

INSTITUTE OF TECHNOLOGY Sindhi Society, Chembur, Mumbai-400 071

CERTIFICATE OF APPROVAL OF PROJECT WORK

This

is

to

Certify

that

Mr Anurag Chugh has satisfactorily carried out the project work entitled Multi Utility Sensor Network (Hardware Design) in partial fulfillment of the B.E. Degree in Electronics of the University of Mumbai, Maharashtra state during 2005-2006

PRINCIPAL

PROJECT GUIDE

HEAD OF DEPARTMENT

EXAMINER

Project Report on

Multi-Utility Sensor Network Hardware Design

MUSN: Hardware Design

A Tribute to Deep S. Bhattacharjee Deep S. Bhattacharjee was a brilliant and one of the finest students of Vivekanand Education Society's Institute of Technology, where he was pursuing his Bachelor of Engineering (B.E.) in Computer Engineering. A very sincere and hardworking student by nature, Deep always excelled in studies and was a topper of his class consistently. He was very jolly and always ever ready to help his friends and colleagues in their times of need. Unfortunately, Deep left us in a tragic accident during the floods of 26th July 2005. This project is an earnest tribute by his friends to a life which our world was blessed with for so tragically short a time. Our heartfelt prayers are with his family and friends on this occasion of unspeakable grief. May his soul rest in peace!

ii

MUSN: Hardware Design

Acknowledgements For guiding us throughout and supporting us relentlessly, our most sincere thanks to Abhay Kshirsagar Sir, Assistant Professor, Electronics Department and Prof. K.G. Balakrishnan, Assistant Professor, IT Department. Our sincere thanks to Mr. Dhananjay V. Gadre, Asst. Professor, NSIT, Delhi for showing us the way and pushing us in the right direction. We are grateful to him for sharing his profound knowledge and resources for AVR micro controller. Many thanks to the Principal and Management of Vivekanand Education Society’s Institute of Technology for helping us stage our project at ‘ELECRAMA 2006’. And special word of thanks to Vivekananda Education Society’s Institute of Technology’s Development Laboratory In-charge, Mr. V.M. Misra, for perennially keeping us on our toes and giving us some fantastic moments to cherish, both during and after ‘ELECRAMA 2006’. Also, our heartfelt thanks to our Laboratory In-charges, Chandrashekhar Sir, Rajesh Sir, Purohit Sir and Chandane Sir, for helping us with all the necessary laboratory resources, throughout the development phase of ‘Multi Utility Sensor Network’.

Anurag Chugh Charuta Ambardekar Richa Tewari Rohan Raghunath Shweta Arvind Saraf D-16 Final Year Electronics, 2005-06

iii

MUSN: Hardware Design

Contents LIST OF FIGURES......................................................................................................................................VI LIST OF TABLES.....................................................................................................................................VIII 1

GENERAL OVERVIEW ..................................................................................................................... 2 1.1 INTRODUCTION ............................................................................................................................... 3 1.2 STRUCTURE OF THE NETWORK ........................................................................................................ 4 1.2.1 RS-485 Bus................................................................................................................................ 4 1.2.2 Sensor Nodes............................................................................................................................. 5 1.2.3 RS-232 to RS-485 Bridge .......................................................................................................... 6 1.2.4 Host Computer.......................................................................................................................... 6 1.3 PROJECT DIVISION .......................................................................................................................... 6 1.3.1 Hardware Implementation ........................................................................................................ 6 1.3.2 Embedded Software Implementation......................................................................................... 7 1.3.3 Host Software Implementation.................................................................................................. 7

2

RS-485 NETWORKS AND SERIAL COMMUNICATIONS.......................................................... 8 2.1 INTRODUCTION ............................................................................................................................... 9 2.2 FEATURES OF RS-485 NETWORKS ................................................................................................ 11 2.3 ELECTRICAL CHARACTERISTICS OF RS-485 NETWORKS .............................................................. 12 2.3.1 Balanced Lines........................................................................................................................ 12 2.3.2 Termination............................................................................................................................. 13 2.3.3 Inside Circuitry ....................................................................................................................... 14 2.3.4 Voltage Requirements ............................................................................................................. 15 2.3.5 Current Requirements............................................................................................................. 15 2.3.6 Speed....................................................................................................................................... 16 2.3.7 Modes...................................................................................................................................... 17 2.3.7.1 Full Duplex ........................................................................................................................ 17 2.3.7.2 Half Duplex ........................................................................................................................ 18 2.3.8 Internal Protection Circuitry .................................................................................................. 19 2.3.9 Available RS-485 Transceiver ICs .......................................................................................... 19 2.4 SERIAL COMMUNICATIONS ........................................................................................................... 21 2.4.1 Formats and Protocols ........................................................................................................... 21 2.4.1.1 Synchronous Format .......................................................................................................... 22 2.4.1.2 Asynchronous Format ........................................................................................................ 22 2.4.2 UARTs..................................................................................................................................... 24 2.4.3 Transmitting a byte serially .................................................................................................... 24 2.5 RS-232 LINKS .............................................................................................................................. 26 2.5.1 DTE and DCE......................................................................................................................... 27 2.5.2 RS-232 Signal Lines................................................................................................................ 27 2.5.3 Electrical Specifications of RS-232 Signaling ........................................................................ 29 2.5.4 RS-232 Transceiver ICs .......................................................................................................... 30 2.5.5 Comparison between RS-232 and RS-485 .............................................................................. 32 2.5.6 Converting between RS-232 and RS-485 ............................................................................... 32

3

THE AVR MICROCONTROLLER ................................................................................................. 34 3.1 INTRODUCTION ............................................................................................................................. 35 3.2 GENERAL FEATURES OF AVR MICROCONTROLLERS .................................................................... 35 3.3 CHOICE OF MICROCONTROLLER ................................................................................................... 36 3.3.1 Factors involved in choosing .................................................................................................. 36 3.3.1.1 Pin count ............................................................................................................................ 36 3.3.1.2 On board Calibrated RC Oscillator................................................................................... 36 3.3.1.3 Program Memory ............................................................................................................... 37 3.3.1.4 USART................................................................................................................................ 37 3.3.1.5 Analog to Digital Converter............................................................................................... 37 3.3.1.6 EEPROM............................................................................................................................ 37 3.3.1.7 Timer/Counters .................................................................................................................. 37

iv

MUSN: Hardware Design 3.3.1.8 Other Peripherals............................................................................................................... 37 3.3.1.9 Cost .................................................................................................................................... 37 3.4 THE ATMEGA8 MICROCONTROLLER ............................................................................................ 38 3.4.1 Feature List............................................................................................................................. 38 3.4.2 Pin Configuration ................................................................................................................... 39 3.4.3 Block Diagram........................................................................................................................ 40 3.4.4 Pin Descriptions ..................................................................................................................... 41 3.4.5 Architectural Overview (AVR CPU Core) .............................................................................. 42 3.4.6 I/O Ports ................................................................................................................................. 44 3.4.6.1 Ports as General Digital I/Os ............................................................................................ 45 3.4.7 AVR USART ............................................................................................................................ 47 3.4.8 Analog-to-Digital Converter................................................................................................... 52 3.4.8.1 The Prescaler and Conversion Timing............................................................................... 54 3.4.8.2 ADC Input Channels .......................................................................................................... 56 3.4.8.3 ADC Voltage Reference ..................................................................................................... 56 3.4.8.4 Analog Input Circuitry ....................................................................................................... 57 4

HARDWARE DESIGN ...................................................................................................................... 58 4.1 DESIGN OF SENSOR NODE ............................................................................................................. 59 4.1.1 Design of the First Prototype of the Sensor Node................................................................... 60 4.1.2 Design of the First Prototype of the RS-232 to RS-485 Bridge............................................... 64 4.1.3 Power Supply for the Network ................................................................................................ 64 4.1.4 Faults encountered with the First Prototypes ......................................................................... 65 4.1.4.1 Faults in the RS-485 Network wiring itself ........................................................................ 65 4.1.4.2 Faults in the Sensor Node Design ...................................................................................... 65 4.1.4.3 Faults in the RS-232 to RS-485 Bridge Design .................................................................. 66 4.1.5 Design of the Second Prototype of the Sensor Node ............................................................... 66 4.1.6 Design of the Second Prototype of the RS-232 to RS-485 Bridge.......................................... 69 4.1.7 Design of the Final Sensor Node ............................................................................................ 72 4.1.8 Oscilloscope Traces ................................................................................................................ 75

5

APPLICATIONS OF MULTI-UTILITY SENSOR NETWORK................................................... 77 5.1 INTRODUCTION ............................................................................................................................. 78 5.2 VOTING PADS ............................................................................................................................... 78 5.2.1 Implementation ....................................................................................................................... 79 5.3 HOME MONITORING ..................................................................................................................... 81 5.3.1 Implementation ....................................................................................................................... 81 5.3.2 Sensors interfaced................................................................................................................... 83 5.3.2.1 Mercury Switch .................................................................................................................. 83 5.3.2.2 Light Dependant Resistor................................................................................................... 84 5.3.2.3 LM35 Temperature Sensor................................................................................................. 85 5.3.2.4 Humidity Sensor ................................................................................................................. 87 5.3.2.5 Motion Detector (Passive Infrared + Microwave)............................................................. 89 5.3.2.6 Gas Leakage Detector........................................................................................................ 91 5.3.2.7 Infrared Proximity Sensor (Active) .................................................................................... 93 5.3.2.8 Smoke Detector .................................................................................................................. 93

6

ELECRAMA EXPERIENCE AND FUTURE SCOPE .................................................................. 95 6.1 THE ELECRAMA EXPERIENCE ....................................................................................................... 96 6.2 FUTURE SCOPE ............................................................................................................................. 97 6.2.1 Voting Pads............................................................................................................................. 97 6.2.1.1 Increasing Capacity ........................................................................................................... 97 6.2.1.2 Fastest finger first .............................................................................................................. 97 6.2.1.3 Product Engineering .......................................................................................................... 98 6.2.1.4 Use of better Bus standards: CAN/Ethernet..................................................................... 100 6.2.2 Building Monitoring and Control ......................................................................................... 101 6.2.3 Industrial Monitoring and Control ....................................................................................... 102

REFERENCES ........................................................................................................................................... 103 INDEX ......................................................................................................................................................... 104

v

MUSN: Hardware Design

List of Figures FIGURE 1 BASIC STRUCTURE OF OUR NETWORK ................................................................................................. 4 FIGURE 2 RS485 NETWORK IMPLEMENTATION USING MAX485/DS75176 HALF DUPLEX DRIVERS .................... 10 FIGURE 3 DAISY CHAINING ............................................................................................................................... 11 FIGURE 4 BALANCED LINE ................................................................................................................................ 12 FIGURE 5 AN RS-485 DRIVER’S OUTPUT REFERENCED TO GROUND. LINE B (BOTTOM) IS INVERSE OF LINE A (TOP) ..................................................................................................................................................... 12 FIGURE 6 TERMINATING AND BIASING ............................................................................................................... 13 FIGURE 7 CIRCUITRY INSIDE AN RS-485 DRIVER AND RECEIVER. ........................................................................ 15 FIGURE 8 RELATION BETWEEN CABLE LENGTH AND BIT RATE. TRADING DATA RATE FOR CABLE LENGTH IS THE UNFORTUNATE CONSEQUENCE OF FINITE PROPAGATION DELAY ON THE TRANSMISSION LINE. .................... 17 FIGURE 9 A FULL DUPLEX RS-485 LINK ............................................................................................................ 18 FIGURE 10 IN THE FULL DUPLEX, MULTI-NODE LINK, NODE 0 TRANSMITS TO ALL OTHER NODES ON ONE PATH, AND RECEIVES FROM ALL OTHER NODES ON THE OTHER PATH. ......................................................................... 18 FIGURE 11 HALF DUPLEX OPERATION .............................................................................................................. 19 FIGURE 12 AN EXTRACT FROM MAX485 DATASHEET......................................................................................... 20 FIGURE 13 TYPICAL SYNCHRONOUS AND ASYNCHRONOUS TRANSMISSION........................................................... 21 FIGURE 14 EACH END OF THE LINK USES A CLOCK OF 16 TIMES THE BIT RATE TO DETERMINE WHEN TO SEND AND READ EACH BIT........................................................................................................................................ 25 FIGURE 15 ELECTRICAL SPECIFICATIONS OF RS-232......................................................................................... 30 FIGURE 16 CHIPS LIKE MAX232 AND MAX233 MAKE IT EASY TO INTERFACE 5V LOGIC TO RS-232 .................... 31 FIGURE 17 THE CIRCUIT CONVERTS BETWEEN RS 232 AND TTL AND TTL TO RS 485.......................................... 33 FIGURE 18 PIN CONFIGURATION OF PDIP PACKAGE OF ATMEGA8 ................................................................... 39 FIGURE 19 BLOCK DIAGRAM OF ATMEGA8 MICROCONTROLLER ........................................................................ 40 FIGURE 20 THE AVR CPU CORE .................................................................................................................... 43 FIGURE 21 I/O PIN EQUIVALENT SCHEMATIC .................................................................................................... 44 FIGURE 22 GENERAL DIGITAL I/O .................................................................................................................... 45 FIGURE 23 USART BLOCK DIAGRAM ................................................................................................................ 48 FIGURE 24 CLOCK GENERATION LOGIC, BLOCK DIAGRAM ................................................................................ 49 FIGURE 25 ANALOG TO DIGITAL CONVERTER BLOCK SCHEMATIC OPERATION ................................................... 53 FIGURE 26 ADC PRESCALER ............................................................................................................................ 54 FIGURE 27 ADC TIMING DIAGRAM, SINGLE CONVERSION ................................................................................. 55 FIGURE 28 ADC TIMING DIAGRAM, FREE RUNNING CONVERSION ..................................................................... 55 FIGURE 29 ANALOG INPUT CIRCUITRY .............................................................................................................. 57 FIGURE 30 BLOCK DIAGRAM OF THE SENSOR NODE ........................................................................................... 60 FIGURE 31 SCHEMATIC OF THE FIRST PROTOTYPE OF THE SENSOR NODE ............................................................ 61 FIGURE 32 PCB LAYOUT FOR THE FIRST PROTOTYPE OF THE SENSOR NODE ..................................................... 62 FIGURE 33 THE FIRST PROTOTYPE SENSOR NODE .............................................................................................. 62 FIGURE 34 THE WHOLE NETWORK ASSEMBLED USING THE FIRST PROTOTYPE SENSOR BOARD .............................. 63 FIGURE 35 TERMINATION AND BIASING OF THE NETWORK WAS ACHIEVED USING THE ABOVE CIRCUIT .................. 63 FIGURE 36 FIRST PROTOTYPE OF THE RS-232 TO RS-485 BRIDGE ..................................................................... 64 FIGURE 37 12 VOLT 2 AMPERE SWITCHED MODE POWER SUPPLY USED FOR THE NETWORK ............................... 65 FIGURE 38 SCHEMATIC OF THE SECOND PROTOTYPE OF THE SENSOR NODE ...................................................... 67 FIGURE 39 PCB LAYOUT OF THE SECOND PROTOTYPE SENSOR NODE ............................................................... 68 FIGURE 40 THE SECOND PROTOTYPE SENSOR NODE ......................................................................................... 68 FIGURE 41 BLOCK DIAGRAM OF SECOND PROTOTYPE OF RS-232 TO RS-485 BRIDGE ....................................... 69 FIGURE 42 SCHEMATIC OF THE SECOND PROTOTYPE OF THE RS-232 TO RS-485 BRIDGE .................................. 70 FIGURE 43 PCB LAYOUT OF THE SECOND PROTOTYPE RS-232 TO RS-485 BRIDGE ........................................... 71 FIGURE 44 THE SECOND PROTOTYPE RS-232 TO RS-485 BRIDGE ..................................................................... 71 FIGURE 45 THE SCHEMATIC OF THE FINAL SENSOR BOARDS .............................................................................. 73 FIGURE 46 THE PCB LAYOUT OF THE FINAL SENSOR BOARDS ........................................................................... 74 FIGURE 47 THE FINAL SENSOR BOARDS ............................................................................................................. 74 FIGURE 48 OSCILLOSCOPE TRACE SHOWING THE A AND B SIGNALS OF THE RS-485 NETWORK. THE CENTRAL SIGNAL WHICH IS A-B WAS OBTAINED BY UNG THE OSCILLOSCOPE’S MATH FEATURES ................................ 75 FIGURE 49 OSCILLOSCOPE TRACE SHOWING THE TRANSMISSION (PARTIAL) OF A PACKET ON THE RS-485 BUS. THE TRANSMITTED PACKET IS “A012KQ”. EACH CHARACTER IS TRANSMITTED STARTING WITH LSB. THE SYMBOLS S AND D IN THE FIGURE INDICATE THE START AND STOP BITS RESPECTIVELY. ............................................. 76

vi

MUSN: Hardware Design FIGURE 50 THE VOTING PAD NETWORK ............................................................................................................ 79 FIGURE 51 THE VOTING PAD NETWORK IN ACTION ............................................................................................ 80 FIGURE 52 SCREEN SHOT OF THE WINDOWS BASED HOST COMPUTER RUNNING THE VOTING PAD APPLICATION CODED IN JAVA USING THE ECLIPSE IDE ................................................................................................. 80 FIGURE 53 SMART HOME DEMONSTRATION ....................................................................................................... 82 FIGURE 54 SMPS FOR POWERING THE SENSOR NODES DIRECTLY FROM AC MAINS .............................................. 82 FIGURE 55 MERCURY SWITCH IN THE OFF STATE ............................................................................................... 83 FIGURE 56 MERCURY SWITCH IN THE ON STATE ................................................................................................. 83 FIGURE 57 LDRS IN VARIOUS FLAVOURS ........................................................................................................... 84 FIGURE 58 LIGHT DEPENDANT RESISTOR AS INTERFACED TO THE SENSOR NETWORK .......................................... 84 FIGURE 59 TYPICAL CONNECTIONS OF A LDR................................................................................................. 85 FIGURE 60 EXTRACT FROM LM34 DATASHEET .................................................................................................. 85 FIGURE 61 LM35 SENSOR ................................................................................................................................ 86 FIGURE 62 LM35 INTERFACED TO THE NETWORK .............................................................................................. 86 FIGURE 63 HUMIDITY SENSOR CONFIGURATION ................................................................................................ 87 FIGURE 64 THE HUMIDITY SENSOR ................................................................................................................... 89 FIGURE 65 THE INTERNALS OF THE MOTION DETECTOR .................................................................................... 90 FIGURE 66 PHOTO OF THE MOTION DETECTOR ................................................................................................. 90 FIGURE 67 GAS LEAKAGE DETECTOR ................................................................................................................ 91 FIGURE 68 GAS LEAKAGE DETECTOR CONNECTIONS ......................................................................................... 91 FIGURE 69 PHOTO OF THE GAS LEAKAGE DETECTOR ........................................................................................ 92 FIGURE 70 INFRARED PROXIMITY SENSOR ......................................................................................................... 93 FIGURE 71 SMOKE DETECTOR .......................................................................................................................... 94 FIGURE 72 KBC STUDIO .................................................................................................................................. 97 FIGURE 73 SUGGESTED ENCLOSURES ............................................................................................................... 98 FIGURE 74 PUSH BUTTON SWITCHES WITH LEDS .............................................................................................. 99 FIGURE 75 TWISTED PAIR ................................................................................................................................. 99 FIGURE 76 SUGGESTED CONNECTORS............................................................................................................. 100 FIGURE 77 TYPICAL FLOOR PLAN FOR BUILDING MONITORING AND CONTROL ................................................ 101

vii

MUSN: Hardware Design

List of Tables TABLE 1 AVAILABLE RS-485 TRANSCEIVER ICS ............................................................................................ 20 TABLE 2 WITH EVEN PARITY, THE DATA BITS PLUS THE PARITY BIT CONTAIN AN EVEN NUMBER OF 1 S. WITH ODD PARITY; THE DATA BITS PLUS THE PARITY BIT CONTAIN AN ODD NUMBER OF 1 S. .......................... 23 TABLE 3 COMPARISON BETWEEN RS-232 AND RS-485 SIGNALING TECHNIQUES ............................................ 32 TABLE 4 PIN DESCRIPTIONS ............................................................................................................................ 41 TABLE 5 PORT PIN CONFIGURATIONS .............................................................................................................. 46 TABLE 6 EQUATIONS FOR CALCULATING BAUD RATE REGISTER SETTING ..................................................... 50 TABLE 7 EXAMPLES OF UBRR SETTINGS FOR COMMONLY USED OSCILLATOR FREQUENCIES ....................... 51 TABLE 8 TYPICAL ADC CONVERSION TIMES ................................................................................................... 56 TABLE 9 PACKET FORMAT ............................................................................................................................... 81 TABLE 10 HUMIDITY SENSOR SPECIFICATIONS ............................................................................................... 87 TABLE 11 LOOK UP TABLE : STANDARD SPECIFICATIONS CORRESPONDING TO RELATIVE HUMIDITY .............. 88 TABLE 12 SPECIFICATIONS OF THE GAS LEAKAGE DETECTOR ........................................................................ 91 TABLE 13 INDICATORS ON THE GAS LEAKAGE DETECTOR .............................................................................. 92

viii

MUSN: Hardware Design

1 General Overview

2

MUSN: Hardware Design

1.1 Introduction Technological advances in electronics and communications has enabled the development of low-cost, low power, multifunctional sensor nodes. These sensor nodes are capable of data collection, data processing and can communicate over long distances, leveraging the idea of sensor networks. Sensor networks have significantly improved over traditional sensors and have become an indispensable tool in various fields such as industry, entertainment, military, health, etc. A sensor network consists of a large number of sensor nodes that can be deployed either inside the measurand or very close to it. These nodes may be deployed in remote locations and thus allow for remote monitoring of various parameters. The sensor nodes are fitted with onboard processors. Thus the nodes carry out simple calculations and transmit only the required and partially processed data. The above-described features enable sensor networks to be used for wide range of applications. In health, for example, sensor networks can be deployed to monitor and assist disabled patients. In military, the rapid deployment and fault tolerant characteristics of sensor networks make them a very promising sensing technique for military command and control. Other commercial applications include voting pads for game shows, home security, inventory management, monitoring product quality, monitoring disaster-prone areas. The sensor nodes are usually strategically placed in the sensor field. Each of these nodes has the capability to collect and route data back to the host monitoring system. Data are routed back using a multidrop network. This network reduces the number of wires required to connect field devices to the host. Our multi-utility sensor network aims at satisfying the following criteria 1. 2. 3. 4. 5. 6. 7.

Cost effectiveness Easy procurability of components High immunity to noise Ease of operation, flexibility and user friendly GUI Ease of reconfiguration for other applications Scalability Rudimentary built-in processing capability

The focus of the Hardware Design Team was to develop and test the sensor nodes for this network. The team was also responsible for interfacing the sensors to these nodes. The sensor node PCBs were designed using Eagle PCB Layout Editor. Multiple versions of the sensor nodes were made and tested until satisfactory performance and reliability levels were achieved. Procurement of components was also the Hardware Team’s Responsibility.

3

MUSN: Hardware Design

1.2 Structure of the network

Figure 1 Basic Structure of our Network

The network consists of the following components: 1. 2. 3. 4.

1.2.1

RS-485 Bus Sensor Nodes RS-232 to RS-485 Bridge Host computer

RS-485 Bus

RS-485 Bus is a 3-wire interface that can be used to implement multi-drop networks. When a network needs to transfer small blocks of information over long distances, RS-485 is often the interface of choice. The network nodes can be PCs, micro controllers, or any devices capable of asynchronous serial communication. Compared to Ethernet and other network interfaces, RS-485’s hardware and protocol requirements are simpler and cheaper. The RS-485 standard is flexible enough to provide a choice of drivers, receivers, and other components depending on the cable length, data rate, number of nodes, and the need to conserve power. Several vendors offer RS-485 transceivers with various combinations of features. Also, there are options for methods of terminating and biasing the line and controlling the driver enable inputs.

4

MUSN: Hardware Design

1.2.2

Sensor Nodes

The Sensor Node is the main workhorse of the system. At its heart lies the ATmega8 micro controller that is a high performance RISC controller with a built-in USART, Analog to Digital Converter (ADC) and Self Programming Capabilities. It can communicate with other nodes and the host over the RS-485 Bus. MAX485 level converter is used to convert the signals between TTL and RS-485 levels. The Sensor Node uses its ADC to sample data from its sensors and convert them to digital format. This collected sensor data is then processed by the ATmega8 micro controller. The result of this processing is sent over the network to the host. The following sensors maybe used with the network: 1. Infrared/Capacitive/Inductive Proximity Sensor for counting objects on the Assembly Line 2. Single chip Temperature sensor or PT100 based Temperature sensor 3. Power supply monitoring ICs 4. Humidity Sensors 5. Gas Sensors (Carbon Monoxide, Nitrogen Oxide) 6. Calibrated Strain Gauge based Load Cells (For measuring weight) 7. Accelerometer (for measuring acceleration) 8. Tilt Switches (Mercury Switches) 9. Hall effect switch IC 10. Hall Effect Vane Switch 11. Opto-interrupters 12. LVDTs 13. Shaft Encoders 14. Reed Switches 15. Flame Sensors (UV Sensors) 16. Any other sensors which are available pre-calibrated or don’t require calibration

5

MUSN: Hardware Design

1.2.3

RS-232 to RS-485 Bridge

It is used to connect the RS-485 Bus to the Host computer via the RS-232 communications ports. It consists of a MAX232 level converter, which converts RS-232 signals from the computer to TTL levels. These TTL signals are further converted to RS485 signals using the MAX485/DS75176 driver ICs. An AVR ATmega8 micro controller is used to monitor the incoming and outgoing data from the Host computer and switches the MAX485 between the transmitting and receiving mode accordingly. Multiple RS-232 to RS-485 Bridges can be used at either end of the network to increase network reliability and fault tolerance. It means that the networks can withstand breaks in the RS-485 medium (twisted pair) by querying the nodes from multiple points on the network. This requires multiple RS-232 Ports on the Host computer.

1.2.4

Host Computer

The Host computer is the link between the network and the external world. It is a Windows based system with multiple RS-232 serial ports and it communicates with the RS-485 Network using the RS-232 to RS-485 Bridges. The Host computer needs a Java Runtime Environment (JRE) to run various network applications. The Host computer monitors the network and acquires the data from the Sensor Nodes using a well-defined protocol. It processes these data and stores them in the database. For the Home Monitoring application, it dynamically displays the current data being read from the sensors. The Voting Pad application records the votes cast by users and displays a graph suggesting the statistics. The Host computer also provides data to the database server where all the records are maintained.

1.3 Project Division The project was divided in three modules and three teams worked in simultaneously on these modules.

1.3.1

Hardware Implementation

The physical existence of the network itself is ensured by the hardware implementation. This includes designing the circuits and the layouts for the Sensor Nodes and the RS-232 to RS-485 Bridges. Various features considered while designing are status-LEDs, on board ISP programming, on board crystal, reset circuitry, etc. EMC design issues are considered as high-speed data transfer is involved. The circuits and the layouts have been designed in Eagle 4.11, a well-known CAD software. The necessary circuitries for the sensors are also developed.

6

MUSN: Hardware Design

1.3.2

Embedded Software Implementation

The focus of using embedded software is to develop the intelligence for the Sensor Nodes. The software development for the onboard AVR micro controllers, which collect and process sensor data, is done using Embedded C Language. WinAVR 2005 is used to write programs and AVRStudio 4.11 is used to download the programs on to the micro controllers. Programming for applications is as varied as Industrial Process Monitoring, Home Monitoring and Voting Pads has been done. Communication between the Sensor Network and the Host Computer follows a self-developed protocol. The calibration of sensors is also done based on the available data for the sensors.

1.3.3

Host Software Implementation

The host computer runs software for acquiring data from the network. The software running on the host computer is written in Java. Eclipse IDE was used during the creation of the software. The library used for implementing serial communications in Java was RX/TX. The database server runs MySQL server 5.0 and takes data from the Host computer. It provides this data to the Web Server. The database server handles all details of the data chronologically and is responsible for providing the latest data to the user. The Web server runs a PHP based application that is Ajax enabled. The PHP application takes the details from the database server and passes it on to the client machines in graphical format. Ajax is used to reduce the load on the Web server as new data is sent to the client at regular intervals to reduce bandwidth requirements. On receiving the data from the web server, the JavaScript at the client side updates the graphs and views in the browser. The PHP application is also capable to communicate with a java daemon on the host machine to directly control and communicate with the network. This report covers the Hardware Design of the Multi Utility Sensor Network

7

MUSN: Hardware Design

2 RS-485 Networks and Serial Communications

8

MUSN: Hardware Design

2.1 Introduction RS485 bus is a 3-wire interface which can be used to implement multi-drop networks. When a network needs to transfer small blocks of information over long distances, RS-485 is often the interface of choice. The network nodes can be PCs, microcontrollers, or any devices capable of asynchronous serial communications. Compared to Ethernet and other network interfaces, RS-485’s hardware and protocol requirements are simpler and cheaper. The RS-485 standard is flexible enough to provide a choice of drivers, receivers, and other components depending on the cable length, data rate, number of nodes, and the need to conserve power. Several vendors offer RS-485 transceivers with various combinations of features. Also, there are options for methods of terminating and biasing the line and controlling the driver enable inputs. The interface popularly known as RS-485 is an electrical specification for multipoint systems that use balanced lines. RS-485 is similar to RS-422, but RS-422 allows just one driver with multiple receivers whereas RS-485 supports multiple drivers and receivers. The specification document (TIA/EIA-485-A) defines the electrical characteristics of the line and its drivers and receivers. There are brief suggestions relating to terminations and wiring, but there’s no discussion of connector pin outs or software protocols (as there is for RS-232). An RS-485 network can have up to 32 unit loads, with one unit load equivalent to an input impedance of 12k. By using high-impedance receivers, you can have as many as 256 nodes. An RS-485 link can extend as far as 4000′ and can transfer data at up to 10 Mbps, but not both at the same time. At 90 kbps, the maximum cable length is 4000′, at 1 Mbps it drops to 400′, and at 10 Mbps it drops to 50′. For more nodes or long distances, you can use repeaters that regenerate the signals and begin a new RS-485 line. Although the RS-485 standard says nothing about protocols, most RS-485 links use the familiar asynchronous protocols supported by the USARTs in PCs and other computers. A transmitted word consists of a start bit followed by data bits, an optional parity bit, and a stop bit. We have implemented the RS485 Network using MAX485/DS72176 Driver ICs. We have used a twisted pair of wires as the RS485 Medium as shown in Figure 2. The network has been implemented in a daisy chain fashion as shown in Figure 3. The Daisy Chain topology allows for efficient management of termination of reflections on the bus. 120 Ohm resistors are used for termination of the bus on either end.

9

MUSN: Hardware Design

Figure 2 RS485 Network Implementation using MAX485/DS75176 Half Duplex Drivers

10

MUSN: Hardware Design

Figure 3 Daisy Chaining

2.2 Features of RS-485 Networks Low Cost The drivers and receivers are inexpensive and require just a +5v power supply to generate the required minimum 1.5v minimum difference at the differential outputs. In contrast, RS-232’s minimum output of ± 5v requires dual supplies or an expensive interface chips that can generate the supplies. Networking Ability Instead of being limited to two devices, RS-485 is a multi-drop interface that can have multiple drivers and receivers. Long Links An RS-485’s link can stretch as long as 4000 feet as compared to RS-232’s 50 to 100 feet. Fast Bit rates can be as high as 10 Mbps. The bit rate and cable length are related. Lower bit rate allows higher cable lengths

11

MUSN: Hardware Design

2.3 Electrical Characteristics of RS-485 Networks 2.3.1

Balanced Lines

The main reason why RS-485 can transmit over long distances is because of the use of balanced lines. Each signal has a dedicated pair of wires with voltage on one of the wires equal to negative, or complement of the voltage on the other. The receiver responds to the difference between the voltages.

Figure 4 Balanced Line

The biggest advantage of the balanced lines is their immunity to noise. Another term for this type of transmission is differential signaling. TIA/EIA 485 designates the two lines as a differential pair as A and B. At the driver a TTL logic high input causes line A to be more positive than line B. While a TTL logic low input causes line B to be more positive than line A. At the receiver, if the input A is more positive that input B, the TTL logic high else logic low. Referenced on the receiver’s ground, each input must be within the range -7V to +12V. This allows for differences in ground potential between the driver and the receiver. The maximum differential input (VA-VB) is no more than ± 6V.

Figure 5 An RS-485 Driver’s output referenced to ground. Line B (Bottom) is inverse of Line A (Top)

12

MUSN: Hardware Design

2.3.2

Termination

If the network cable used is long enough for the transmission-line effects to arise, terminating techniques must be used. The technique used most commonly for termination of RS-485 links is shown in Figure 6.

Figure 6 Terminating and Biasing

The circuit has two 120-Ω terminating resistors connected in parallel, at or just beyond the final node at each end of the link. One end of the link also has two 560-W biasing resistors. The terminations reduce voltage reflections that can cause the receiver to misread logic levels. The receiver sees reflected voltages as output switches, and the line settles from its initial current to its final current. The termination eliminates reflections by making the initial and final currents equal. The initial current is a function of the line’s characteristic impedance, which is the input impedance of an infinite open line. The value varies with the wires’ diameters, the spacing between them, and the insulation type. For digital signals (which consist mainly of frequencies greater than 100 kHz), the characteristic impedance is mostly resistive; the inductive and capacitive components are small. A typical value for 24-AWG twisted pair is 120 Ω. The final current is a function of the line termination, the receivers’ input impedance, and the line’s series impedance. In a typical RS-485 line without a termination, the initial current is greater than the final current because the characteristic impedance is less than the receivers’ combined input impedance. On a line without a termination, the first reflection occurs when the initial current reaches the receiver. The receiver’s input can absorb only a fraction of the current. The rest reflects back to the driver. As the current reverses direction, its magnetic field collapses and induces a voltage on the line. As a result, the receiver initially sees a greater voltage than what was transmitted. When the reflected voltage reaches the driver, which has a lower impedance than the line, the driver absorbs some of the reflection and bounces

13

MUSN: Hardware Design

the rest back to the receiver. This reflection is of opposite polarity to the first reflection and causes the receiver to see a reduced voltage. The reflections bounce back and forth like this for a few rounds before they die out and the line settles to its final current. If the line terminates with a resistor equal to the line’s characteristic impedance, there are no reflections. When the initial current reaches the termination, it sees exactly what it was expecting—a load equal to the line’s characteristic impedance. The entire transmitted voltage drops across the load. In a network with two parallel terminations, the drivers drive two lines with each ending at a termination. The biasing resistors hold the line in a known state when no drivers are enabled. Most RS-485 transceivers have internal biasing circuits, but adding a termination defeats their ability to bias the line. A typical internal circuit is a 100-kW pullup from line A to V+, and a 100-kW pulldown from line B to ground. With no termination and when no drivers are enabled, the biasing resistors hold line A more positive than line B. When you add two 120-W terminations, the difference between A and B shrinks to a few millivolts, much less than the required 200 mV. The solution is to add smaller resistors in parallel with the internal biasing so that a greater proportion of the series voltage drops across the termination. The size of the biasing resistors is a tradeoff. For a greater voltage difference and higher noise immunity on an idle line, use smaller values. For lower power consumption and a greater differential voltage on a driven line, use larger values. When the receiver is disabled, the receiver’s output is high impedance. If the output doesn’t connect to a input with an internal pullup, adding a pullup here ensures that the node doesn’t see false start bits when its receiver is disabled. To comply with the specification, all of the nodes must share a common ground connection. This ground maybe isolated from earth ground. The ground wire provides a path for the current that results from small imbalances in the balanced line. If the A and B outputs balance exactly with equal, opposite currents, the two currents in the ground wire cancel each other out and the wire carries no current at all. In real life, components don’t balance perfectly; one driver will be a little stronger and one receiver will have a slightly larger input impedance.

2.3.3

Inside Circuitry

Figure 7 shows the internal circuits of the RS-485 driver and receiver. The components shown are same as the equivalent circuit in the data sheets for Texas Instrument’s 75179B. Other RS-485 chips may differ in details, but the overall operation remains the same. The schematic shows the driver’s outputs and the receiver’s input and output circuits, along with the path current takes when the link transmits a TTL logic 1. A logic 1 at the driver’s TTL input causes transistors Q1 and Q4 to switch on, and Q2 and Q3 to switch off. The voltage on line A causes Q6 to switch on. Current flows to Q6 and returns to the driver via the ground wire. In a similar way, the low voltage on line B causes Q7 to switch on, and current flows from Q7 into Q4, returning via the ground wire. Line A is more positive than line B, and the result is a logic high at the receiver’s TTL output.

14

MUSN: Hardware Design

Figure 7 Circuitry inside an RS-485 driver and receiver.

Each driver’s current forms a complete loop from driver to receiver then back to the driver. A ground wire or other ground connection provides a return path for both signals. But because the ground currents are equal and opposite, they cancel each other and the actual current in the ground wire is near zero. If the link has multiple receivers each behaves like the one shown. If the link has termination resistors, current flows in these as well. For a logic 0, the situation is reverse. Q2, Q3, Q5 and Q8 switch on, the others switch off and the current in the wire flows in the opposite direction.

2.3.4

Voltage Requirements

RS-485 interfaces typically use a single 5V power supply but the logic levels at the drivers and the receivers aren’t 5V TTL or CMOS logic voltages. For a valid output, the difference between A and B must be at least 1.5V.

2.3.5

Current Requirements

The total current used by an RS-485 link varies with the impedances of the components in the link including the drivers, cable, receivers and termination components. A low output impedance at the driver and low impedance cable enables fast switching and ensures that the receiver sees the largest signal possible. A high impedance at the receiver decreases the current in the link and increases the battery life in battery powered links. The 15

MUSN: Hardware Design

termination components, when used, have the greatest effect on the amount of current used by the link. Many RS-485 links have a 120 ohm resistor across the differential lines at each of the link’s two ends. The parallel combination of these is 60 ohms. The terminations create a low resistance path from the driver with a logic high output, through the terminations, and into the driver with a logic low output. On short, slow links you may be able to eliminate the termination entirely and greatly reduce power consumption. When there is no termination, the receiver’s input impedance has the greatest effect on the total series resistance. The total input impedance varies with the number of enabled receivers and their input impedance. An RS-485 bus transceiver can drive 32 unit loads. When the received voltage is as much as +12V greater than the receiver’s signal ground, a unit-load receiver draws no more than 1 milliampere. When the received voltage is as much as 7V less than the receiver’s ground, a unit load receiver draws no more than -0.8 milliampere. For this the receiver must have an input impedance of 12000 ohms between each differential input and supply voltage or ground, depending on the direction of the current flow.

2.3.6

Speed

An RS-485 link can be as fast as 10 Mbps or 4000 feet, but not both at the same time. Longer cables require slower bit rates. Over long distances the cable capacitance slows the signal transitions. At rates up to 90 Kbps, RS-485 and RS 422 support cable lengths of up to 4000 feet. At faster rates the maximum allowed cable length drops to around 400 feet at 1 Mbps and 50 feet at 10 Mbps. The graph assumes an AWG #24 unshielded, terminated twisted pair.

16

MUSN: Hardware Design

Figure 8 Relation between cable length and bit rate. Trading data rate for cable length is the unfortunate consequence of finite propagation delay on the transmission line.

2.3.7 2.3.7.1

Modes Full Duplex

The RS-485 interface is designed to use in multi-point systems, with one or more generators and receivers. Most RS-485 links are half duplex, where multiple drivers and receivers share a signal path. But you can also use RS-485 in a full duplex link where each direction has its own signal path. Swapping an RS-232 link for a full duplex RS-485 link is completely transparent to the software or the firmware that uses the link. You can use the exact same programming for both, though RS-485 supports higher bit rates and the hardware allows longer links . This is a simple solution when you want to create long distance, full duplex links between microcontrollers. The RS-485 interface chips are also smaller, cheaper and simpler than converting to RS-232. You can also use RS 422 interface chips for this type of links.

17

MUSN: Hardware Design

Figure 9 A full duplex RS-485 link

Figure 10 shows that it is also possible to use full duplex with multiple drivers and receivers. One arrangement is in a master slave network where a master node (node 0 in the figure) has control of the network and grants the other’s permission to transmit.

Figure 10 In the full duplex, multi-node link, Node 0 transmits to all other nodes on one path, and receives from all other nodes on the other path.

2.3.7.2

Half Duplex

Many RS-485 links are half duplex, with multiple drivers and receivers sharing a signal path. When a link has three or more nodes, it usually makes sense to have just one signal path and allow one node at a time to transmit. Having two data paths is convenient when there are just two devices, because each can transmit at any time without worrying about whose turn it is. But with more than one driver at the same pair of wires, there’s no guarantee that the signal path will be free when a driver wants to transmit, and figuring out when it’s OK to use each of two signal paths just adds more complications (except in the master/slave networks like the one just described in he previous section).

18

MUSN: Hardware Design

Figure 11 Half Duplex Operation

2.3.8

Internal Protection Circuitry

In a half-duplex link, only one driver in a link should be enabled at a time. But no matter how carefully a network is designed, it has multiple drivers, there’s a chance that two or more drivers will be enabled at once. When this occurs, if the drivers try to pull the lines to opposite states, the result is unpredictable voltages and high currents. All RS-485 interface chips include current limiting and thermal shutdown to protect the chips if more than one driver is enabled at once. The current limiting restricts the output current of the drivers.

2.3.9

Available RS-485 Transceiver ICs

There are many other RS-485 interface chips from a variety of manufacturers and with different features and abilities. Table 1 lists some of the options. Figure 12 is an extract from the MAX485 Datasheet showing its pin configuration.

19

MUSN: Hardware Design Table 1 Available RS-485 Transceiver ICs

Figure 12 An extract from MAX485 Datasheet

20

MUSN: Hardware Design

2.4 Serial Communications 2.4.1

Formats and Protocols

The computers in a serial link may be of different types, but all must agree on convention, and rules for the data they exchange. This agreement helps to ensure that every transmission reaches its destination and that each computer can understand the messages sent to it. In a serial link, the transmitter, or driver, sends bits one at a time, in sequence. A link with just two devices may have a dedicated path for each direction or it may have a single path shined by both, with the transmitters taking turns. When there are three or more devices, all usually share a path, and a network protocol determines when each can transmit.

Figure 13 Typical Synchronous and Asynchronous Transmission

One signal required by all serial links is a clock, or timing reference, to control the flow of data. The transmitter and receiver use a clock to decide when to send and read each bit. Two types of serial-data formats are synchronous and asynchronous, and each uses clocks in different ways.

21

MUSN: Hardware Design

2.4.1.1

Synchronous Format

In a synchronous transmission, all devices use a common clock generated by one of the devices or an external source. The clock may have a fixed frequency or it may toggle at irregular intervals. All transmitted bits are synchronized to the clock. In other words, each transmitted bit is valid at a defined time after a clock transition (rising or falling edge). The receiver uses the clock transitions to decide when to read each incoming bit. The exact details of the protocol can vary. For example, a receiver may latch incoming data on the rising or falling clock edge, or on detecting logic high or low level. Synchronous formats use a variety of ways to signal the start and end of a transmission, including Start and Stop bits and dedicated chip-select signals. Synchronous interfaces are useful for short links, with cables of 15 feet or less or even between components on a single circuit board. For longer links, synchronous formats are less practical because of the need to transmit the clock signal, which requires an extra line and is subject to noise. 2.4.1.2

Asynchronous Format

In asynchronous (also called unsynchronous and non-synchronous) transmissions, the link doesn't include a clock line, because each end of the link provides its own clock. Each end must agree on the clock's frequency, and all of the clocks must match within a few percent. Each transmitted byte includes a Start bit to synchronize the clocks, and one or more Stop bits to signal the end of a transmitted word. The RS-232 ports on PCs use asynchronous formats to communicate with modems and other devices. Although all RS-232 interface call also transfer synchronous data, asynchronous links are much more common. Most RS-485 links also use asynchronous communications. An asynchronous transmission may use any of several common formats. Probably the most popular is 8-N-1, where the transmitter sends each data byte as 1 Start bit, followed by 8 data bits, beginning with bit 0 (the LSB, or least significant bit), and ending with 1 Stop bit. The N in 8-N-1 indicates that the transmissions don't use a parity bit. Other formats include a parity bit as a simple form of error checking. Parity can be Even, Odd, Mark, or Space. Table 2 illustrates Even and Odd parity. With Even parity, the parity bit is set or cleared so that the data bits plus the parity bit contain all even number of 1s. With Odd parity, the bit is set or cleared so that these bits contain an odd number of 1s. An example format using parity is 7-E-1. The transmitter sends 1 Start bit, 7 data bits, 1 parity bit, and 1 Stop bit. Here again, both ends of the link must agree on the format. The receiver examines the received data and informs the transmitter of an error if a result isn't the expected value. Mark and Space parity are forms of Stick parity: with Mark parity, the parity bit is always l, and with Space parity, it's always 0. These are less useful as error indicators, but one use for them is in the 9-bit networks. These networks use a parity bit to indicate whether a byte contains an address or data.

22

MUSN: Hardware Design

Other, less common formats use different numbers of data bits. Many serial ports support anywhere from 5 to 8 data bits, plus a parity bit. Table 2 With Even parity, the data bits plus the parity bit contain an even number of 1 s. With Odd parity; the data bits plus the parity bit contain an odd number of 1 s.

A link's bit rate is the number of bits per second transmitted or received per unit of time, usually expressed as bits per second (bps). Baud rate is the number of possible events, or data transitions, per second. The two values are often identical because in many links, including those described in this book, each transition period represents a new bit. Over phone lines, high-speed modems use phase shifts and other tricks to encode multiple bits in each data period, so the baud rate is actually much lower than the bit rate. All of the bits required to transmit a value from Start to Stop bit form a word. The data bits in a word form a character. In some links, the characters actually do represent text characters (letters or numbers), while in others the characters are binary values that have nothing to do with text. The number of characters transmitted per second equals the bit rate times the number of bits in a word. Adding one Start and one Stop bit to a byte increases the transmission time of each byte by 25 percent (because there are 10 bits per byte instead of just A). With 8-N-I format, a byte transmits at 1/10 the bit rate: a 9600 bitsper-second link transmits 960 bytes per second. If the receiver requires a little extra time to accept received data, the transmitter may stretch the Stop bit to the width of 1.5 or 2 bits. The original purpose of the longer Stop bit was to allow time for mechanical teletype machines to settle to an idle state.

23

MUSN: Hardware Design

2.4.2

UARTs

Fortunately, the programming required to send and receive data in asynchronous formats is simpler than expected. PCs and many microcontrollers have a component called a UART (universal asynchronous receiver/transmitter) that handles most of the details of sending and receiving serial data. In PCs, the operating system and programming languages include support for programming serial links without having to understand every detail of the UART's architecture. To open a link, the application selects a data rate and other settings and enables communications at the desired port. To send a byte, the application writes the byte to the transmit buffer of the selected port, and the UART sends the data, bit by bit, in the requested format, adding the Stop. Start, and parity bits as needed. In a similar way, received bytes are automatically stored in a buffer. The UART can trigger an interrupt to notify the CPU, and thus the application, of incoming data and other events. Some microcontrollers don't include a UART, and sometimes you need more UARTs than the microcontroller has. In this case, there are two options: add an external UART, or simulate a UART in program code. Parallax's Basic Stamp is an example of a chip with a UART implemented in code. Atmel’s AVR Series of microcontroller have built-in UARTs. ATmega8 has a single UART where as ATmega128 has 2 UARTs. A USART (Universal Synchronous/Asynchronous Receiver/Transmitter) is a similar device that supports both synchronous as well as asynchronous transmissions.

2.4.3

Transmitting a byte serially

Understanding the details of how a byte transmits isn't strictly necessary in order to design, program, and use a serial link, but the knowledge can be useful in troubleshooting and selecting a protocol and interface for a project. Figure 13 (B) showed how a byte transmits in 8-N-I format. When idle, the transmitter's output is logic 1. To signal the beginning of a transmission, the output sends logic 0 for the length of one bit. This is the Start bit. At 300 bps, a bit is 33 milliseconds, while at 9600 bps, it's 0.1 millisecond.

24

MUSN: Hardware Design

Figure 14 Each end of the link uses a clock of 16 times the bit rate to determine when to send and read each bit.

After the Start bit, the transmitter sends the 8 data bits in sequence, beginning with Bit 0, the least-significant bit (LSB). The transmitter then sends a logic 1, which functions as the Stop bit. The output remains at logic 1 for at least the width of one bit. Immediately following this, or at any time after, the transmitter may send a new Start bit to announce the beginning of a new byte. At the receiving end, the transition from logic 1 to the Start bit's logic 0 signals that a byte is arriving and determines the liming for detecting the following bits. The receiver measures the logic state of each bit near the middle of the bit. This helps ensure that the receiver reads the bits correctly even if the transmitting and receiving clocks don't match exactly. Some interfaces, such as RS-232, use inverted voltages from those shown: the Stop bit is a negative voltage and the Start bit is positive. The UART typically uses a receive clock that is 16 times the bit frequency: if the data rate is 300 bits per second, the receive clock must be 4800 bits per second. As Figure 14 shows, after detecting the transition that signals a start bit, the UART waits 16 clock cycles for the Start bit to end, then waits 8 more cycles to read bit 0 in the middle of the bit. It then reads each of the following bits 16 clock cycles after the previous one. If the transmitting and receiving clocks don't match exactly, the receiver will read each successive bit closer and closer to an edge of the bit. To read all of the bits in a 10-bit word correctly, the transmit and receive clocks should vary no more than about three percent. Any more than this, and by the time the receiver tries to read the final bits, the timing may be off by so much that it will read the bits either before they've begun or after they've finished. However, the clocks only need to stay in sync for the length of a word, because each word begins with a new Start bit that resynchronizes the clocks.

25

MUSN: Hardware Design

Because of the need for accurate timing, asynchronous interfaces require a stable timing reference. Most are controlled by a crystal or ceramic resonator. For best results, the frequency of the reference should allow even division by the frequencies the receive clocks use for standard bit rates. In PCs, the standard UART clock frequency is 1.8432 Mhz. Division by 16 gives 115.200, which is the top bit rate the UART supports. In a microcontrollers, the chip's main timing crystal usually serves as a reference for hardware timers that control the UART's clock. In the 8051 family, the hardware timers run at 1/12 the crystal frequency. With a crystal of 11.0592 Mhz, the fastest UART time is 921,600 Hz, which allows a bit rate of 57,600 bps. As a way of eliminating errors due to noise, some UARTs, like the 8051 microcontroller's, take three samples in the middle of each bit, and use the logic level that matches two or more of the samples.

2.5 RS-232 Links RS-232 is one of the most popular computer interfaces of all time. It's the workhorse that has been built into just about every PC as well as many other types of computers from microcontrollers to mainframes, and the devices they connect to. RS-232's most common use is to connect to a modem, but other devices with RS-232 interfaces include printers, data-acquisition modules, test instruments, and control circuits. You can also use RS-232 as a simple link between computers of any type. These days, there are faster and more sophisticated interfaces, but RS-232 continues to be popular because the hardware and programming requirements are simple and inexpensive and because so many existing devices already have the interface built-in. Other choices include descendants of RS-232 that are faster or cheaper, while remaining compatible with RS-232 in many ways. RS-232 is designed to handle communications between two devices, with a distance limit of 50 to 100 feet, depending on the bit rate and cable type. Because RS-232 ports are so common, another popular use is to connect to an adapter that converts the interface to another type. For example, a simple circuit converts an RS-232 port to RS485, which can connect to multiple devices and can use much longer links. RS-232 links use unbalanced lines. Although a state of unbalance sounds like something to be avoided, in this context it just refers to electrical characteristics of the signals on the lines. In an unbalanced line, the signal voltage is applied to one wire, and all signal voltages are referenced to a common ground. Another term for this type of interface is single-ended. In most respects, the standard serial port on PCs conforms to the RS-232 standard. The Telecommunications Industry Association (TIA) publishes the document that defines the signal functions, pin locations, and other characteristics of the interface.

26

MUSN: Hardware Design

2.5.1

DTE and DCE

The RS-232 standard calls the terminal end of the link the Data Terminal Equipment, or DTE. It calls the modem end the Data Circuit-terminating Equipment, or DCE. It doesn't matter which device in a link is the DTE and which is the DCE, but a link must have one of each. The type determines which signals are inputs and which are outputs at the connector. All of the signal names are from the perspective of the DTE. For example, TD (transmit data) is an output on a DTE and an input on a DCE, while RD (receive data) is an input on a DTE and an output on a DCE. With few exceptions, serial ports on PCs are configured as DTEs, and all modems' serial ports are DCEs. Most other peripherals are DCEs, but there are exceptions, including many serial printers. When necessary, a simple adapter will convert one type of interface to the other.

2.5.2

RS-232 Signal Lines The three essential signals for 2-way RS-232 communications are these: • • •

TD : Carries data from the DTE to the DCE. Also called TX and TXD. RD : Carries data from the DCE to the DTE. Also called RX and RXD. SG : Signal ground. Also called GND and SGND.

The other signals arc optional control signals intended for communicating about the readiness of a device, or the presence of a ringing or carrier signal on a phone line. There are two pairs of handshaking signals: DTR/DSR and RTS/CTS. Each pair has uses defined by the standard. There are several ways to describe the state of RS-232 and other control signals. A signal with a valid positive voltage may be described as On, asserted, or True to indicate that it's in its active state. For example, when DTR is True, the data terminal is ready. To bring the signal True, the controlling device raises the line. A signal with a valid negative voltage may be described as Off, de-asserted, or False to indicate that it's in its inactive state. For example, when DTR is False, the data terminal is not ready. To bring the signal False, the controlling device lowers the line. In the following descriptions, the word terminal is used to refer to the DTE and modem to refer to the DCE.

27

MUSN: Hardware Design

The DTR/DSR handshake is intended for providing information about the status of the phone line or other communications channel connected to the modem. The terminal raises DTR (data terminal ready) to request the modem to connect to the communications channel. In response, the modem raises DSR (data set ready) to indicate that it's connected. DSR is False when the modem is not connected to the communications channel (on detecting a disconnect, for example) or on detecting a fault. The terminal may also raise DTR in response to RI (ring indicator), to tell the modem to answer a call. In some links, DTR and DSR are raised on power-up and just indicate that the equipment is present and powered. The RTS/CTS handshake provides additional information about whether a device is ready to receive data. There arc two common uses for the signals. In the first, and original, use, the signal pair provides a full handshake. When the terminal has data to send, it raises RTS (request to send). In response, the modem raises CTS (clear to send) to indicate that it's ready to receive. When the transmission is finished, the terminal may lower RTS. The modem should then continue processing whatever data it has received and lower CTS when it's ready to respond to the next RTS. When RTS is False, the terminal should wait for CTS to be False before raising RTS to request a new transmission. In the opposite direction, in a half-duplex link, the modem may transmit to the terminal only when RTS is False. In the other protocol used by these signals, each device uses its output independently to let the other know when it's OK to send data. CTS has the same function: it indicates whether the DCE is ready to receive data. But RTS is redefined as the DTE's Ready for Receiving. Each device checks the opposite end's signal before transmitting. The latest version of TIA/EIA-232 includes this definition, which has long been in popular use. RI (ring indicator) is True when a ringing signal is present on the communications channel. The signal is True when the audible ring is present. and False in the pauses between rings. The final control signal is CD (carrier detect). The modem raises CD when it detects a signal of the expected frequency on the phone lines, indicating that a connection has been established to a remote modern. SG (signal ground) is the common ground used by all of the signals.

28

MUSN: Hardware Design

2.5.3

Electrical Specifications of RS-232 Signaling

RS-232 logic levels are indicated by positive and negative voltages, rather than by the positive-only signals of SV TTL and CMOS logic. At an RS-232 data output (TD), a logic 0 is defined as equal to or more positive than +5V, and a logic 1 is defined as equal to or more negative than -5V. In other words, the signals use negative logic, where the more negative voltage is logic 1. The control signals use the same voltages, but with positive logic. A positive voltage indicates that the function is On, or asserted, and a negative voltage indicates that the function is Off, or not asserted. RS-232 interface chips invert the signals. On a UART's Output pin, a logic 1 data bit or an Off control signal is near SV, which results in e negative voltage at the RS-232 interface. A logic-0 data bit or On control signal is near 0V, resulting in a positive voltage at the RS-232 interface. Because an RS-232 receiver may be at the end of a long cable, by the time the signal reaches the receiver, its voltage may have attenuated or have noise riding on it. To allow for this, the minimum required voltages at the receiver are less than at the driver. An input more positive than +3V is a logic 0 at RD, or On at a control input. An input more negative than 3V is a logic 1 at RD, or Off at a control input. According to the standard, the logic level of an input between -3V and +3V is undefined. The noise margin, or voltage margin, is the difference between the output and input voltages. RS-232's large voltage swings result in a much wider noise margin than 5V TTL logic. For example, even if an RS-232 driver's output is the minimum +5V, it can attenuate or have noise spikes as large as 2V at the receiver and still be a valid logic 0. Many RS232 outputs have much wider voltage swings; -9 and ±12V are common. These in turn give much wider noise margins. The maximum allowed voltage swing is ±15V, though receivers must handle voltages as high as ±25V without damage. Two other terms used in relation to RS-232 arc Mark and Space, Space is logic 0, and Mark is logic 1. These refer to the physical marks and spaces made by the mechanical recorders used years ago to log binary data. Figure 15 shows a graphical description the RS-232 Signaling levels.

29

MUSN: Hardware Design

Figure 15 Electrical Specifications of RS-232

2.5.4

RS-232 Transceiver ICs

Many microcontrollers have asynchronous serial ports, but their inputs and outputs use 5V logic rather than RS-232 voltages. Interfacing 5V logic to an RS-232 port requires converting to and from RS-232 levels. By 5V logic, we mean the logic levels used by TTL or CMOS logic chips powered by a single +5V power supply, with signal voltages referenced to ground. With TTL logic, a logic-low output must be no higher than 0.4V, and a logic-low input must be no higher than 0.8V. A logic-high output must be at least 2.4V, while a logic-high input must be at least 2V. Using these levels, an interface may have 0.4V of noise without causing errors. Most CMOS chips define logic levels differently and have wider noise margins. A logic-low CMOS output is no higher than 0.1 V, and a logic-low input may be as high as 20% of the power supply, or 1 V with a 5V supply. A logic-high output is at least 4.9V, and a logic-high input must be at least 70% of the power supply, or 3.5V with a 5V supply. A simple way to translate from 5 V logic to RS-232 is to use one of the many chips designed for this purpose. Maxim Semiconductor was the first to offer RS-232 interface chips that require only a +5V power supply. Many other companies, including Linear Technology. Harris Semiconductor, Texas Instruments, Dallas Semiconductor, and National Semiconductor, now have similar chips, as well as dozens of derivatives for just

30

MUSN: Hardware Design

about every conceivable configuration. The chips may be listed in catalogs and data hooks under Linear, Interface, or Special Function ICs. The original MAX232 Figure 16 includes two drivers that convert TTL inputs to RS-232 outputs, and two receivers that accept RS-232 inputs and translate them to CMOS compatible Outputs. The drivers and receivers also invert the signals. The chip contains two charge-pump voltage converters that act as tiny, unregulated power supplies that enable loaded RS-232 outputs of ±7V or better. Four external capacitors store energy for the supplies. The recommended value for the capacitors is 1 μF or larger. If you use polarized capacitors, take care to get the polarities correct when you put the circuit together. The voltage at pin 6 is negative, so its capacitor's + terminal connects to ground. Because the outputs can be as high as 10V, be sure the capacitors are rated for a WVDC of at least 15V. (Most are.)

Figure 16 Chips like MAX232 and MAX233 make it easy to interface 5V logic to RS-232

31

MUSN: Hardware Design

2.5.5

Comparison between RS-232 and RS-485 Table 3 compares the RS-232 and RS-485 Signaling techniques. Table 3 Comparison between RS-232 and RS-485 Signaling techniques

2.5.6

Converting between RS-232 and RS-485

Because RS-232 is so popular many RS-485 interfaces are created by converting RS-232 signals to RS-485. If a PC has a free RS-232 port then adding an external converter is cheaper and easier then buying and installing an RS-485 card. Some microcontroller cards also have RS-232 built in though in these cases it is usually simpler to bypass RS-232 by removing the interface chip and wire the RS-485 interface directly to the microcontroller’s port pins. Figure 17 shows one way to convert RS-232 to RS-485. The interface uses three RS-232 lines: TD transmits data, RD receives data and RTS controls direction. A MAX 233 converts RS-232 signals to TTL levels, and the TTL signals connect to a 75176B that provides the RS-485 interface. When RTS is low, the enable inputs of the ‘176 are high and TD can transmit to the RS-485 link. When RTS is high, the enable inputs are low and RD can receive data from RS-485 link. The circuit shown below has very poor performance under the Microsoft Windows. Windows doesn’t control the serial port handshaking lines very well. As compared with MS-DOS, it is very poor in its timing. This meant that it would cause unnecessary delays between switching the RS-485 Transceiver between the receiving and transmitting modes. The host software which has been created to control and collect the data from the sensor network needs the Java Runtime Environment (JRE) to run. MS-DOS is a very old operating system and is incompatible with JRE. So allowances had to be made for making the system compatible with Microsoft Windows (JRE compatible) which is currently the most popular operating system amongst PC users. Hence we had to resort to designing our own circuit to convert between RS-232 and RS-485 Signaling levels. Details about this circuit have been covered later on.

32

MUSN: Hardware Design

Figure 17 The circuit converts between RS 232 and TTL and TTL to RS 485.

33

MUSN: Hardware Design

3 The AVR Microcontroller

34

MUSN: Hardware Design

3.1 Introduction The AVR is a series of High Performance Microcontrollers from Atmel. The superior features of the AVR microcontrollers have been nicely summed up in the following quotes reproduced from Atmel’s website. “Atmel's AVR® microcontrollers have a RISC core running single cycle instructions and a well-defined I/O structure that limits the need for external components. Internal oscillators, timers, UART, SPI, pull-up resistors, pulse width modulation, ADC, analog comparator and watch-dog timers are some of the features you will find in AVR devices.” “AVR instructions are tuned to decrease the size of the program whether the code is written in C or Assembly. With on-chip in-system programmable Flash and EEPROM, the AVR is a perfect choice in order to optimize cost and get product to the market quickly.”

3.2 General features of AVR Microcontrollers The following list gives an overview of the general features pf the AVR microcontrollers. • • • • • • • • • • • • • • • • • • • • • •

High performance Low power consumption High code density Outstanding memory technology High integration True RISC architecture Harvard architecture True single cycle execution 20 MIPS at 20Mhz 32 general purpose registers 1.8 - 5.5 volts operation Sleep controller with a variety of operation modes Fast wake-up from low-power modes Software controlled operation frequency Single cycle execution and high code density Architecture designed for C 32 general registers C-like addressing modes 16- and 32-bit arithmetic support Linear address maps Self-programming Flash EEPROM for parameter storage

35

MUSN: Hardware Design

• o o o • • •

Full integration on single die Flash EEPROM SRAM In-System Programming In-System Debugging In-System Verification

There are a wide variety of AVR microcontrollers available: • Devices range from 1 to 256KB of Flash Memory • Pin count range from 8 to 100 • Full code compatibility among all members of the AVR series • Pin/feature compatible families are available • Single set of development tools for all members of the series

3.3 Choice of Microcontroller 3.3.1

Factors involved in choosing

We have chosen to use the ATmega8 microcontroller. Following factors were considered while choosing this microcontroller for this project: 3.3.1.1

Pin count

Since the aim of project was to take the intelligence of the sensor network to the sensor itself, hence the number of I/O required was very less since it was expect that only 3-4 sensors and 3-4 actuators would be interfaced to a single node. ATmega8 is a 28 pin device with 23 programmable I/O pins. Higher end microcontroller with more number of I/O pins would have increased the cost whereas the lower end microcontrollers in the AVR series had insufficient number of pins for interfacing multiple sensors to a single node. 3.3.1.2

On board Calibrated RC Oscillator

Although we have used external crystals, an on board oscillator would prove useful in case of decreasing component cost. Eliminating external crystal would limit the maximum throughput of the network (decreased baud rate) which would suffice for small sensor networks which do not generate much data in a give amount of time. An internal oscillator also helps in the debugging process. All Mega series of AVR microcontroller have internal oscillators

36

MUSN: Hardware Design

3.3.1.3

Program Memory

ATmega8 has 8 Kb of Flash Memory for Program storage. This is sufficient for accommodating the complete program code for a single sensor node interfaced to multiple sensors and actuators. The lesser amount of program memory on lower end microcontrollers from the AVR Series might not have been able to accommodate the sensor node program. 3.3.1.4

USART

ATmega8 has an onboard interrupt driven USART. The onboard hardware USART simplifies the serial communication process by eliminating the need for implementing the same using software 3.3.1.5

Analog to Digital Converter

Most sensors give and analog voltage output proportional to the physical parameter measured. ATmega8 has 6 onboard ADC channels (4 with 10 bit resolution, 2 with 8 bit resolution). The ADC is successive approximation type. Other higher end AVR microcontrollers have more ADC channels but since the number of sensors required to be interfaced to a single node was not more than 3-4 , we choose to stick to ATmega8. 3.3.1.6

EEPROM

ATmega8 has 512 bytes of EEPROM which is enough for storing node IDs and Look Up Tables for analog sensors interfaced to the node. 3.3.1.7

Timer/Counters

ATmega8 has two 8-bit and one 16-bit counters. These were useful for sensors with pulse outputs such as object counters. The timers were also used for recording the time elapsed between two events. 3.3.1.8

Other Peripherals

ATmega8 has many other peripherals which are useful for our purpose. Some of these were: Brown out detection, PWM output channels (3 nos.), Boot loading, Watchdog timer with separate onboard oscillator, Power on reset, sleep mode etc. All these features helped in eliminating the number of external components required for a single node. 3.3.1.9

Cost ATmega8 is very cheaply and easily available in India.

37

MUSN: Hardware Design

3.4 The ATmega8 Microcontroller The ATmega8 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega8 achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed.

3.4.1

Feature List The following list describes the specific features of ATmega8 Microcontroller: • •

•

•

•

High-performance, Low-power AVR® 8-bit Microcontroller Advanced RISC Architecture o 130 Powerful Instructions – Most Single-clock Cycle Execution o 32 x 8 General Purpose Working Registers o Fully Static Operation o Up to 16 MIPS Throughput at 16 MHz o On-chip 2-cycle Multiplier Nonvolatile Program and Data Memories o 8K Bytes of In-System Self-Programmable Flash o Endurance: 10,000 Write/Erase Cycles o Optional Boot Code Section with Independent Lock Bits ƒ In-System Programming by On-chip Boot Program ƒ True Read-While-Write Operation o 512 Bytes EEPROM Endurance: 100,000 Write/Erase Cycles o 1K Byte Internal SRAM o Programming Lock for Software Security Peripheral Features o Two 8-bit Timer/Counters with Separate Prescaler, one Compare Mode o One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode o Real Time Counter with Separate Oscillator o Three PWM Channels o 8-channel ADC in TQFP and MLF package ƒ Six Channels 10-bit Accuracy ƒ Two Channels 8-bit Accuracy o 6-channel ADC in PDIP package ƒ Four Channels 10-bit Accuracy ƒ Two Channels 8-bit Accuracy o Byte-oriented Two-wire Serial Interface o Programmable Serial USART o Master/Slave SPI Serial Interface o Programmable Watchdog Timer with Separate On-chip Oscillator o On-chip Analog Comparator Special Microcontroller Features o Power-on Reset and Programmable Brown-out Detection o Internal Calibrated RC Oscillator

38

MUSN: Hardware Design

• • • • • • • • •

3.4.2

o External and Internal Interrupt Sources o Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Powerdown, and Standby I/O and Packages o 23 Programmable I/O Lines o 28-lead PDIP, 32-lead TQFP, and 32-pad MLF Operating Voltages o - 5.5V (ATmega8L) o - 5.5V (ATmega8) Speed Grades 0 - 8 MHz (ATmega8L) 0 - 16 MHz (ATmega8) Power Consumption at 4 Mhz, 3V, 25°C Active: 3.6 mA Idle Mode: 1.0 mA Power-down Mode: 0.5 μA

Pin Configuration Figure 18 shows the pin configuration of ATmega8 microcontroller.

Figure 18 Pin Configuration of PDIP package of ATmega8

39

MUSN: Hardware Design

3.4.3

Block Diagram Figure 19 shows the internal block diagram of ATmega8 microcontroller.

Figure 19 Block Diagram of ATmega8 microcontroller

40

MUSN: Hardware Design

3.4.4

Pin Descriptions

The following table describes the functions of each pin of ATmega8 microcontroller. Table 4 Pin Descriptions

VCC

Digital supply voltage.

GND

Ground.

Port B (PB7..PB0) XTAL1/ XTAL2/TOSC1/TOSC2

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Depending on the clock selection fuse settings, PB6 can be used as input to the inverting Oscillator amplifier and input to the internal clock operating circuit. Depending on the clock selection fuse settings, PB7 can be used as output from the inverting Oscillator amplifier. If the Internal Calibrated RC Oscillator is used as chip clock source, PB7..6 is used as TOSC2..1 input for the Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set. PORTB pins also serve as the Serial Peripheral Interface. InSystem Programming is done through these pins.

Port C (PC5..PC0)

Port C is an 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running.

_______________

If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical characteristics of PC6 differ from those of the other pins of Port C. If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pin for longer than the minimum pulse length will generate a Reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a Reset.

PC6/R E S E T

Port D (PD7..PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will

41

MUSN: Hardware Design source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running.

_______________

RESE T

Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running.

AVCC

AVCC is the supply voltage pin for the A/D Converter, Port C (3..0), and ADC (7..6). It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. Note that Port C (5..4) use digital supply voltage, VCC.

AREF

AREF is the analog reference pin for the A/D Converter.

3.4.5

Architectural Overview (AVR CPU Core)

This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able access memories, perform calculations, control peripherals, and handle interrupts. Figure 20 shows the block diagram of the AVR CPU Core. In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the Program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the Program memory. This concept enables instructions to be executed in every clock cycle. The Program memory is In-System Reprogrammable Flash memory. The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash Program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. The Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR

42

MUSN: Hardware Design

instructions have a single 16-bit word format. Every Program memory address contains a 16- or 32-bit instruction. Program Flash memory space is divided in two sections, the Boot program section and the Application program section. Both sections have dedicated Lock Bits for write and read/write protection. The SPM instruction that writes into the Application Flash memory section must reside in the Boot program section.

Figure 20 The AVR CPU Core

During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are executed). The Stack Pointer SP is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the Status Register. All interrupts have a separate 43

MUSN: Hardware Design

Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F.

3.4.6

I/O Ports

All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). Each output buffer has symmetrical drive characteristics with both high sink and source capability. The pin driver is strong enough to drive LED displays directly. All port pins have individually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have protection diodes to both VCC and Ground as indicated in Figure 21.

Figure 21 I/O Pin Equivalent Schematic

44

MUSN: Hardware Design

All registers and bit references in this section are written in general form. A lower case “x” represents the numbering letter for the port, and a lower case “n” represents the bit number. However, when using the register or bit defines in a program, the precise form must be used (i.e., PORTB3 for bit 3 in Port B, here documented generally as PORTxn). Three I/O memory address locations are allocated for each port, one each for the Data Register – PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. The Port Input Pins I/O location is read only, while the Data Register and the Data Direction Register are read/write. In addition, the Pull-up Disable – PUD bit in SFIOR disables the pull-up function for all pins in all ports when set. 3.4.6.1

Ports as General Digital I/Os

The ports are bi-directional I/O ports with optional internal pull-ups. Figure 22 shows a functional description of one I/O port pin, here generically called Pxn.

Figure 22 General Digital I/O

Each port pin consists of 3 Register bits: DDxn, PORTxn, and PINxn. The DDxn bits are accessed at the DDRx I/O address, the PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/O address.The DDxn bit in the DDRx Register selects the

45

MUSN: Hardware Design

direction of this pin. If DDxn is written logic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin. If PORTxn is written logic one when the pin is configured as an input pin, the pullup resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to be configured as an output pin. The port pins are tri-stated when a reset condition becomes active, even if no clocks are running. If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled ({DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the SFIOR Register can be set to disable all pull-ups in all ports. Switching between input with pull-up and output low generates the same problem. The user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn} = 0b11) as an intermediate step. Table 5 summarizes the control signals for the pin value. Table 5 Port Pin Configurations

46

MUSN: Hardware Design

3.4.7

AVR USART

The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly-flexible serial communication device. The main features are: • • • • • • • • • • • •

Full Duplex Operation (Independent Serial Receive and Transmit Registers) Asynchronous or Synchronous Operation Master or Slave Clocked Synchronous Operation High Resolution Baud Rate Generator Supports Serial Frames with 5, 6, 7, 8, or 9 Databits and 1 or 2 Stop Bits Odd or Even Parity Generation and Parity Check Supported by Hardware Data OverRun Detection Framing Error Detection Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete Multi-processor Communication Mode Double Speed Asynchronous Communication Mode

A simplified block diagram of the USART Transmitter is shown in Figure 23. CPU accessible I/O Registers and I/O pins are shown in bold. The dashed boxes in the block diagram separate the three main parts of the USART(listed from the top): Clock generator, Transmitter and Receiver. Control Registers are shared by all units. The clock generation logic consists of synchronization logic for external clock input used by synchronous slave operation, and the baud rate generator. The XCK (transfer clock) pin is only used by synchronous transfer mode. The Transmitter consists of a single write buffer, a serial Shift Register, Parity Generator and control logic for handling different serial frame formats. The write buffer allows a continuous transfer of data without any delay between frames. The Receiver is the most complex part of the USART module due to its clock and data recovery units. The recovery units are used for asynchronous data reception. In addition to the recovery units, the Receiver includes a parity checker, control logic, a Shift Register and a two level receive buffer (UDR). The Receiver supports the same frame formats as the Transmitter, and can detect Frame Error, Data OverRun and Parity Errors.

47

MUSN: Hardware Design

Figure 23 USART Block Diagram

The clock generation logic generates the base clock for the Transmitter and Receiver. The USART supports four modes of clock operation: normal asynchronous, double speed asynchronous, Master synchronous and Slave Synchronous mode. The UMSEL bit in USART Control and Status Register C (UCSRC) selects between asynchronous and synchronous operation. Double speed (Asynchronous mode only) is controlled by the U2X found in the UCSRA Register. When using Synchronous mode (UMSEL = 1), the Data Direction Register for the XCK pin (DDR_XCK) controls whether the clock source is internal (Master mode) or external (Slave mode). The XCK pin is only active when using Synchronous mode. Figure 24 shows a block diagram of the clock generation logic.

48

MUSN: Hardware Design

Figure 24 Clock Generation Logic, Block Diagram

Internal clock generation is used for the asynchronous and the Synchronous Master modes of operation. The description in this section refers to Figure 24. The USART Baud Rate Register (UBRR) and the down-counter connected to it function as a programmable prescaler or baud rate generator. The down-counter, running at system clock (fosc), is loaded with the UBRR value each time the counter has counted down to zero or when the UBRRL Register is written. A clock is generated each time the counter reaches zero. This clock is the baud rate generator clock output (= fosc/(UBRR+1)). The Transmitter divides the baud rate generator clock output by 2, 8, or 16 depending on mode. The baud rate generator output is used directly by the Receiver’s clock and data recovery units. However, the recovery units use a state machine that uses 2, 8, or 16 states depending on mode set by the state of the UMSEL, U2X and DDR_XCK bits. Table 6 contains equations for calculating the baud rate (in bits per second) and for calculating the UBRR value for each mode of operation using an internally generated clock source.

49

MUSN: Hardware Design

Table 6 Equations for Calculating Baud Rate Register Setting

For standard crystal and resonator frequencies, the most commonly used baud rates for asynchronous operation can be generated by using the UBRR settings in Table 7. UBRR values which yield an actual baud rate differing less than 0.5% from the target baud rate, are bold in the table. Higher error ratings are acceptable, but the Receiver will have less noise resistance when the error ratings are high, especially for large serial frames. The error values are calculated using the following equation:

50

MUSN: Hardware Design

Table 7 Examples of UBRR Settings for Commonly Used Oscillator Frequencies

51

MUSN: Hardware Design

3.4.8

Analog-to-Digital Converter The onboard ADC on ATmega8 has the following features: • 0.5 LSB Integral Non-linearity • ± 2 LSB Absolute Accuracy • 65 - 260 μs Conversion Time • Up to 15 kSPS at Maximum Resolution • 6 Multiplexed Single Ended Input Channels • Optional Left Adjustment for ADC Result Readout • 0 - VCC ADC Input Voltage Range • Selectable 2.56V ADC Reference Voltage • Free Running or Single Conversion Mode • Interrupt on ADC Conversion Complete • Sleep Mode Noise Canceler

The ATmega8 features a 10-bit successive approximation ADC. The ADC is connected to an 8-channel Analog Multiplexer which allows eight single-ended voltage inputs constructed from the pins of Port C. The single-ended voltage inputs refer to 0V (GND). Note that ADC channels ADC4 and ADC5 are limited to 8-bit accuracy. Channels ADC[3:0] and ADC[7:6] offer full 10-bit accuracy. The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is held at a constant level during conversion. A block diagram of the ADC is shown in Figure 25 . The ADC has a separate analog supply voltage pin, AVCC. AVCC must not differ more than ± 0.3V from VCC. Internal reference voltages of nominally 2.56V or AVCC are provided On-chip. The voltage reference may be externally decoupled at the AREF pin by a capacitor for better noise performance. The ADC converts an analog input voltage to a 10-bit digital value through successive approximation. The minimum value represents GND and the maximum value represents the voltage on the AREF pin minus 1 LSB. Optionally, AVCC or an internal 2.56V reference voltage may be connected to the AREF pin by writing to the REFSn bits in the ADMUX Register. The internal voltage reference may thus be decoupled by an external capacitor at the AREF pin to improve noise immunity. The analog input channel is selected by writing to the MUX bits in ADMUX. Any of the ADC input pins, as well as GND and a fixed bandgap voltage reference, can be selected as single ended inputs to the ADC. The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference and input channel selections will not go into effect until ADEN is set. The ADC does not consume power when ADEN is cleared, so it is recommended to switch off the ADC before entering power saving sleep modes.

52

MUSN: Hardware Design

Figure 25 Analog to Digital Converter Block Schematic Operation

The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and ADCL. By default, the result is presented right adjusted, but can optionally be presented left adjusted by setting the ADLAR bit in ADMUX. If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the Data Registers belongs to the same conversion. Once ADCL is read, ADC access to Data Registers is blocked. This means that if ADCL has been read, and a conversion completes before ADCH is read, neither register is updated and the result from the conversion is lost. When ADCH is read, ADC access to the ADCH and ADCL Registers is re-enabled. The ADC has its own interrupt which can be triggered when a conversion completes. When ADC access to the Data Registers is prohibited between reading of ADCH and ADCL, the interrupt will trigger even if the result is lost. A single conversion

53

MUSN: Hardware Design

is started by writing a logical one to the ADC Start Conversion bit, ADSC. This bit stays high as long as the conversion is in progress and will be cleared by hardware when the conversion is completed. If a different data channel is selected while a conversion is in progress, the ADC will finish the current conversion before performing the channel change. In Free Running mode, the ADC is constantly sampling and updating the ADC Data Register. Free Running mode is selected by writing the ADFR bit in ADCSRA to one. The first conversion must be started by writing a logical one to the ADSC bit in ADCSRA. In this mode the ADC will perform successive conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not. 3.4.8.1

The Prescaler and Conversion Timing

By default, the successive approximation circuitry requires an input clock frequency between 50 kHz and 200 kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the input clock frequency to the ADC can be higher than 200 kHz to get a higher sample rate. The ADC module contains a prescaler, which generates an acceptable ADC clock frequency from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA. The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low.

Figure 26 ADC Prescaler

When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion starts at the following rising edge of the ADC clock cycle. A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry. The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conversion and 13.5 ADC clock cycles after the start of an first conversion. When 54

MUSN: Hardware Design

a conversion is complete, the result is written to the ADC Data Registers, and ADIF is set. In single conversion mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a new conversion will be initiated on the first rising ADC clock edge. In Free Running mode, a new conversion will be started immediately after the conversion completes, while ADSC remains high.

Figure 27 ADC Timing Diagram, Single Conversion

Figure 28 ADC Timing Diagram, Free Running Conversion

The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary register to which the CPU has random access. This ensures that the channels and reference selection only takes place at a safe point during the conversion. The channel and reference selection is continuously updated until a conversion is started. Once the conversion starts, the channel and reference selection is locked to ensure a sufficient sampling time for the ADC. Continuous updating resumes in the last ADC clock cycle before the conversion completes (ADIF in ADCSRA is set). Note that the conversion starts on the following rising ADC clock edge after ADSC is written. The user is thus advised not to write new channel or reference selection values to ADMUX until one ADC clock cycle after ADSC is written.

55

MUSN: Hardware Design Table 8 Typical ADC Conversion times

If both ADFR and ADEN is written to one, an interrupt event can occur at any time. If the ADMUX Register is changed in this period, the user cannot tell if the next conversion is based on the old or the new settings. ADMUX can be safely updated in the following ways: • • •

When ADFR or ADEN is cleared. During conversion, minimum one ADC clock cycle after the trigger event. After a conversion, before the Interrupt Flag used as trigger source is cleared.

When updating ADMUX in one of these conditions, the new settings will affect the next ADC conversion. 3.4.8.2

ADC Input Channels

When changing channel selections, the user should observe the following guidelines to ensure that the correct channel is selected: In Single Conversion mode, always select the channel before starting the conversion. The channel selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the conversion to complete before changing the channel selection. In Free Running mode, always select the channel before starting the first conversion. The channel selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the first conversion to complete, and then change the channel selection. Since the next conversion has already started automatically, the next result will reflect the previous channel selection. Subsequent conversions will reflect the new channel selection. 3.4.8.3

ADC Voltage Reference

The reference voltage for the ADC (VREF) indicates the conversion range for the ADC. Single ended channels that exceed VREF will result in codes close to 0x3FF. VREF can be selected as either AVCC, internal 2.56V reference, or external AREF pin. AVCC is connected to the ADC through a passive switch. The internal 2.56V reference is generated from the internal bandgap reference (VBG) through an internal amplifier. In either case, the external AREF pin is directly connected to the ADC, and the reference voltage can be made more immune to noise by connecting a capacitor between the AREF pin and ground. VREF can also be measured at the AREF pin with a high impedant voltmeter. Note that VREF is a high impedant source, and only a capacitive load

56

MUSN: Hardware Design

should be connected in a system. If the user has a fixed voltage source connected to the AREF pin, the user may not use the other reference voltage options in the application, as they will be shorted to the external voltage. If no external voltage is applied to the AREF pin, the user may switch between AVCC and 2.56V as reference selection. The first ADC conversion result after switching reference voltage source may be inaccurate, and the user is advised to discard this result. 3.4.8.4

Analog Input Circuitry

The analog input circuitry for single ended channels is illustrated in Figure 29. An analog source applied to ADCn is subjected to the pin capacitance and input leakage of that pin, regardless of whether that channel is selected as input for the ADC. When the channel is selected, the source must drive the S/H capacitor through the series resistance (combined resistance in the input path). The ADC is optimized for analog signals with an output impedance of approximately 10 kΩ or less. If such a source is used, the sampling time will be negligible. If a source with higher impedance is used, the sampling time will depend on how long time the source needs to charge the S/H capacitor, with can vary widely. The user is recommended to only use low impedant sources with slowly varying signals, since this minimizes the required charge transfer to the S/H capacitor. Signal components higher than the Nyquist frequency (fADC/2) should not be present for either kind of channels, to avoid distortion from unpredictable signal convolution. The user is advised to remove high frequency components with a low-pass filter before applying the signals as inputs to the ADC.

Figure 29 Analog Input Circuitry

57

MUSN: Hardware Design

4 Hardware Design

58

MUSN: Hardware Design

4.1 Design of sensor node The Sensor Node is the main workhorse of the system. It has to satisfy the following functional requirements. •

• • •

• • • • • • •

A carefully chosen microcontroller serving as the central intelligence for the node. The microcontroller should have built-in peripherals like USART, ADC, EEPROM and PWM for cost effectiveness. The microcontroller should be power efficient. The microcontroller must be capable of boot loading over the network. A carefully chosen RS-485 Transceiver for communication with the host computer and other nodes. Connectors for easy connection to the network in a daisy chain fashion. On board regulator for supplying 5 volts to the microcontroller, transceiver and the sensors connected to it. A separate regulator supplying 12 volts might be needed for sensors requiring 12 volts supply. There should be an option for sourcing power from the following sources: o From power lines distributed with RS-485 network itself o From Mains power lines if present in vicinity o From local battery Option for insertion of line terminating and biasing resistors. Option for External Crystals. External standard crystals could be used to decrease baud rate error at higher speeds. Connectors for easy connection of sensors and actuators to the board. LEDs for indication of dataflow to and from the network. The Sensor board should be sturdy and must withstand wear and tear. Power on reset circuitry. Connector for In-System Programming of the microcontroller.

We have chosen to operate the RS-485 Network in Half Duplex mode to decrease the number of wires required and to make the network easily scalable to multi master system. The RS-485 Network itself requires many points to be considered while designing. The Six main rules for designing RS-485 Networks are: • • • • • •

Use the slowest drivers possible for the bit rate. Terminate long lines with their characteristic impedance. Wire the nodes in a bus topology. Bias inactive links. Use twisted-pair cable. Limit common-mode voltages.

59

MUSN: Hardware Design

We had chosen the node microcontroller as ATmega8. The block diagram showing the requirements of the sensor node is shown in Figure 30.

Figure 30 Block diagram of the Sensor Node

Keeping the above points in mind, we designed the first generation of the sensor nodes as follows:

4.1.1

Design of the First Prototype of the Sensor Node

The first generation of the sensor nodes were designed specifically for testing out the basic structure of the network. Keeping this in mind, we designed the nodes for a specific application which was the most simple to implement: The voting pads network. The voting pads network like those used for audience poll in game shows like “Who wants to be a Millionaire?” have very simple requirements. In this case instead of sensors, four switches are interfaced to the microcontroller. Four LEDs are also connected to the microcontroller indicate the selected option. An acknowledge LED indicates whether the _____

selected option has been read by the host or not. The RE/DE signal of the MAX485 / DS75176 transceiver was controlled by the ATmega8 microcontroller it self. DB9 connectors were used to connect the node to the network in a daisy chain fashion. The actual network links were created using serial cable commonly available in the market. The network carried four signals: A, B, Gnd and +12 volts. The +12 volts signal was required to power the nodes whereas the A, B signals served as the actual carrier of the data signals. The Gnd signal served as the common ground for all the nodes. The Gnd signal acted as the return path for the power supply and also served as a reference for voltages on the A and B data signals. The onboard voltage regulator (7805) was used to derive +5 volts for the microcontroller and associated circuitry on board the node. DIP switches were also added to the node circuit with the intention of setting the node address. The schematic and layout were designed using The Eagle PCB Layout editor. The PCB which was created was single sided so that it could be etched easily in out colleges’ PCB lab. The schematic, PCB Layout and photos of this prototype have been shown below.

60

MUSN: Hardware Design

Figure 31 Schematic of the first prototype of the sensor node

61

MUSN: Hardware Design

Figure 32 PCB Layout for the First Prototype of the Sensor Node

Figure 33 The First Prototype sensor node

62

MUSN: Hardware Design

Figure 34 The whole network assembled using the first prototype sensor board s

Figure 35 Termination and biasing of the network was achieved using the above circuit

63

MUSN: Hardware Design

4.1.2 Design of the First Prototype of the RS-232 to RS-485 Bridge The first prototype of the RS-232 to RS-485 Bridge involved an ATmega128 microcontroller which has two USARTs. One of the USARTs was interfaced to the Host Computer using the MAX232 transceiver IC. The other USART was interfaced to the _____

network using the MAX485 / DS75176 transceiver IC. The RE/DE signal was connected to one of the port pins of the microcontroller. The USARTs were put into interrupt driven mode. The ATmega128 was programmed to act as a relay between the RS-485 network _____

and the Host Computer. It passed on data from USART to the other while toggling the RE /DE signal as required. Since only one bridge was required, the circuit was hand soldered as shown below.

Figure 36 First prototype of the RS-232 to RS-485 Bridge

4.1.3

Power Supply for the Network

All prototype versions of our network distributed power to the nodes using the same power supply. The power supply used was off the shelf 12 Volt 2 Ampere power supply which converted 230 volts AC to +12 volts DC. The power supply was a switch mode converter with over current shutdown. The RS-232 to RS-485 Bridge was mounted on this power supply itself and this acted as the entry point of DC power to the network. The photo of the power supply is given below:

64

MUSN: Hardware Design

Figure 37 12 volt 2 ampere Switched Mode Power Supply used for the Network

4.1.4

Faults encountered with the First Prototypes

We encountered many faults with the first prototype of the network. These are listed as below: 4.1.4.1

Faults in the RS-485 Network wiring itself

We used off the shelf available serial cables for wiring up the network. These wires are not twisted. Hence the A and B signals weren’t twisted and so the noise induced might have been enough to cause errors in the data transmission. We had assumed that since these cables had the internal wires tightly bound together, they would serve as good carriers since the A and B signals would be placed close to each other all the time. This together with the fact that non twisted pairs caused a mismatch between the characteristic impedance and termination resistance led to data transmission errors which forced us to decrease the speed to 9600 bps. Many other factors which were responsible for the unreliability and slow speed of the network are analyzed below. 4.1.4.2

Faults in the Sensor Node Design The following faults were identified in the sensor nodes (Voting pads): •

• • • •

DB9 connectors were used for interfacing the node to the network. These proved to be very cumbersome since they were created for RS-232 links and not for RS-485 links. The off the shelf serial cables used with them were not twisted. Most differential signaling networks do not use DB9 connectors. Absence of decoupling capacitors causes noise to get coupled from the power supply lines into the data lines. Absence of ISP connectors delayed the development and testing process Absence of Tx and Rx LEDs made debugging difficult. There was no option of adding and external crystal for generating accurate clock reference for the USART.

65

MUSN: Hardware Design

• • •

4.1.4.3

_____

Absence of pull down resistor on the RE/DE signal of the MAX485 transceiver. The DIP switches used were of inferior quality. No room for adding terminating and biasing resistors on the extreme nodes itself Faults in the RS-232 to RS-485 Bridge Design

The RS-232 to RS-485 Bridge consisted of ATmega128 which is only available in packages meant for surface mount soldering. Since we did not follow proper Electro-Static Discharge (ESD) prevention precautions while soldering, many of them got damaged beyond repair. We had used ordinary soldering irons to solder ATmega128 which are also a cause of damage to these microcontrollers. ATmega128 also cost 5 times more than ATmega8 thereby making the cost of the Bridge circuit highly prohibitive.

4.1.5

Design of the Second Prototype of the Sensor Node

In the second prototype we were able to eliminate all the above listed faults. Again we focused on getting the basic network up and running by designing the nodes specifically for the voting pads application. In the new design we incorporated the following features: • • • • • •

Decoupling capacitors at the input and output of the voltage regulator External 3.6864 Mhz crystal oscillator External power on reset circuitry RJ45 connectors for interfacing with the network ISP connectors for smooth development process Rx/TX LEDs for easy debugging

• • •

Pull down resistor on the RE/DE signal of the MAX485 transceiver No DIP switches (EEPROM was used for storing the IDs) Option for adding terminating/biasing resistors on board

_____

Besides the above features, we also used the CAT5 cables for wiring the network. CAT5 cables consists of 4 twisted pairs of wires. One of these pairs was used for the A and B signals while the other pairs were used for power supply and ground signals (in multiple). The Schematic, PCB Layout and Photos of the Second Prototype boards are as follows:

66

MUSN: Hardware Design

Figure 38 Schematic of the Second Prototype of the Sensor Node

67

MUSN: Hardware Design

Figure 39 PCB Layout of the Second Prototype Sensor Node

Figure 40 The Second Prototype Sensor Node

68

MUSN: Hardware Design

4.1.6 Design of the Second Prototype of the RS-232 to RS-485 Bridge The Second Prototype of the Bridge was totally redesigned using the ATmega8 microcontroller. In the second prototype ATmega8 microcontroller controlled the direction of flow of data between the network and the Host Computer. ATmega8 has relaxed handling precautions and hence isn’t affected much by ESD. ATmega8 is also very cheap as compared to ATmega128. The block diagram of this new bridge is given below. ATmega 8

_____

RE /DE DI

RO

MAX232

TXD

B

MAX485

RS485 N/W

A

RXD

Computer

Figure 41 Block Diagram of Second Prototype of RS-232 to RS-485 Bridge _____

In the new bridge, a pull down resistor on RE/DE signal of the MAX485 transceiver keeps the bridge and hence the Host Computer always in the receiving mode. All data that flows on the network is received by the computer via the bridge in the following order: RS-485 Network → MAX485 Transceiver → MAX232 Transceiver → Host Computer

As we can see, while receiving the data from the network, ATmega8 remains isolated and does not interfere with the data flow. If the host computer needs to send the data to a node on the network, it sends out the data serially on its TXD line. This data is first received by ATmega8 via its own RXD line and then passed on to the MAX485 transceiver for transmission via its own TXD line. _____

While doing this, ATmega8 enables the transmitter of MAX485 by asserting the RE/DE signal . The ATmeag8’s USART is operated in the interrupt driven mode. Here ATmega8 merely acts as a buffer between the Host Computer and the Network. The flow of data while the Host is transmitting is as below: Host Computer → MAX232 Transceiver → ATmega8→ MAX485 Transceiver → RS-485 Network

The Schematic, PCB Layout and Photo of the Second Prototype of the bridge are shown below. This bridge used RJ45 connectors for interfacing to the network

69

MUSN: Hardware Design

Figure 42 Schematic of the Second Prototype of the RS-232 to RS-485 Bridge

70

MUSN: Hardware Design

Figure 43 PCB Layout of the Second Prototype RS-232 to RS-485 Bridge

Figure 44 The Second Prototype RS-232 to RS-485 Bridge

71

MUSN: Hardware Design

4.1.7

Design of the Final Sensor Node

Using the second prototype of the sensor node, we were able to achieve error free speeds of up to 115200 bits per second without any delay between the packets. After our success with the second prototypes we went on to upgrade our design to generate “multiutility” nodes. These nodes had connectors for interfacing sensors too. They could be used for Voting Pad network and other applications such as home monitoring and industrial monitoring as well. They were more sturdier and were etched on pass through double sided glass epoxy boards. Their basic circuit was the same as the those of the second prototype boards with only the addition of connecters for interfacing the sensors. Terminal blocks were used for interfacing the node to the network. This board and external crystal of 6.144 Mhz and were operated at speeds of 38400 bps. Since 6.144 Mhz is not a valid multiple of 115200 Hz, the boards had to be tested for such higher speeds y replacing the 6.144 MHz crystal with 3.6864 MHz crystals. The results of these tests were successful. The bridge circuit used with these sensor nodes was the same as the second prototype Bridge circuit but with the RJ45 connector replaced by terminal blocks. The Schematic, PCB Layout and Photo of these nodes are as follows:

72

MUSN: Hardware Design

Figure 45 The Schematic of the final Sensor Boards

73

MUSN: Hardware Design

Figure 46 The PCB Layout of the final Sensor Boards

Figure 47 The final Sensor Boards

74

MUSN: Hardware Design

4.1.8

Oscilloscope Traces

The following figures show the oscilloscope traces obtained using the final boards running at 38400 bps.

Figure 48 Oscilloscope trace showing the A and B signals of the RS-485 network. The central signal which is A-B was obtained by ung the oscilloscope’s math features

75

MUSN: Hardware Design

Figure 49 Oscilloscope trace showing the transmission (partial) of a packet on the RS-485 bus. The transmitted packet is “a012KQ”. Each character is transmitted starting with LSB. The symbols s and d in the figure indicate the start and stop bits respectively.

76

MUSN: Hardware Design

5 Applications of Multi-Utility Sensor Network

77

MUSN: Hardware Design

5.1 Introduction Our Multi-Utility Sensor Network can be put to many uses. Some of them are Listed below: • • • • •

Voting Pads for popular TV Game shows or Executive Meetings Input consoles for the “Fastest finger first” rounds in popular TV Game Shows Home Monitoring and Control System Building Monitoring and Control System Industrial Monitoring and Control System

Due to lack of time, we have implemented (for demonstration) only a few of the above applications, namely, Voting Pads and Home Monitoring System. We have added suggestions on ways to turn our project into a complete product for the voting pad network. Also possible ways of extending the network to implement consoles for “ fastest finger first” have been suggested. The Future Scope Section also covers the implementation of the network using Ethernet for Building Monitoring and Control system.

5.2 Voting Pads ‘Kaun Banega Crorepati’ a game show adapted from the popular British version “Who wants to be a Millionaire” is perhaps the most popular television show in India. The show is filmed in front of a studio audience of about 200 civilians who are arranged in circular tiers around a pit in which the action takes place. Ten contestants play Fastest Finger First and the winner makes it to the hotseat. Once in the hotseat, the contestant is asked increasingly difficult general knowledge questions by the host. Questions are multiple choices: four possible alternatives are given to the contestant and he must choose the correct one. If at any point the contestant is unsure of the answer to a question, they can use one of three ‘lifelines’. Out of those three lifelines one of them is ‘Audience Poll’. The studio audience is asked to vote on their keypads, and the contestant is shown a bar chart of their answers, which indicates the trends in voting. A network of keypads used during such an audience poll, is one of the utilities of our sensor network. Some of the properties of the keypad are as follows: • • • •

The keypads consist of 4 push buttons for selecting one of the four choices. One of 4 LEDs indicates the selected answer. An acknowledge and a power LED is optional. Failure of one keypad does not cause the whole network to fail.

78

MUSN: Hardware Design

5.2.1

Implementation

The current implementation of the network comprises of nodes consisting of an ATMega8 microcontroller and a MAX485/DS75176 RS485 Transceiver. They are connected to a single RS 485 bus by using a daisy chain topology. The second prototype of the Sensor Nodes (and RS-232 to RS-485 Bridge) which were solely designed for this voting pad application were used for implementing this network. The host software was coded in Java using the Eclipse IDE. The photos of the implementation of the voting pad network are shown in Figure 50 and Figure 51. The Screenshot of the host software created for the voting pad network is shown in Figure 52. The network speed was set at 115200 bps. Table 9 shows the packet format used

Figure 50 The Voting Pad Network

79

MUSN: Hardware Design

Figure 51 The Voting Pad Network in action

Figure 52 Screen shot of the Windows based host computer running the Voting Pad application coded in Java using the Eclipse IDE

80

MUSN: Hardware Design

Table 9 Packet format

Field Synchronization field

Length 8 bits

Source identification

8 bits

Destination identification

8 bits

Number of data bytes

8 bits

Data bytes

0-255 bytes

Explanation A synchar ‘a’ is used by the PC to initiate communication with the microcontroller Each node on the network is assigned an ID. The source ID indicates the identity of the transmitting entity and the destination ID indicates the identity of receiving entity. In MUSN the PC is assigned an ID ‘0’ and the nodes are assigned numbers between 1-9 This indicates the number of data bytes in the packet The actual data in the packet

5.3 Home Monitoring Home Monitoring System is a collective term for information and communicationtechnology in homes, where the components are communicating through a local network. Smart home technology is the integration of technology and services through home networking for better quality of living with applications in the areas of home automation, information & communication, home security and entertainment. Crucial in this definition is the word, "integration". The various home networks connect and integrate the many sensors (all kinds of input), actuators (all kinds of equipment which do something) and the intelligent central unit. The technology may be used for monitoring, setting off alarms and executing actions, according to programmed criteria. In a home monitoring system one may integrate: • • • • •

5.3.1

Safety alarms Environmental control systems Communication linked to the telephone or the Internet Energy-control-systems for adjusting heating at all hours Entertainment for eg. television, film and music

Implementation

In our demonstration we have integrated the Safety alarms and environmental control system. The photos of the small scale model used for the demonstration purposes is show in Figure 53. Four sensor nodes (final version) were used for the demonstration purposes. The power supply for the smart house was distributed along with the network data cables. In the actual implementation, the nodes (and its connected sensors) will draw power from the mains lines using miniature Switch Mode Power Supplies (Figure 54). 81

MUSN: Hardware Design

Figure 53 Smart Home Demonstration

Figure 54 SMPS for powering the sensor nodes directly from AC mains

82

MUSN: Hardware Design

5.3.2

Sensors interfaced

The following sensors were interfaced for the purposes of demonstration of the Home monitoring application: 5.3.2.1

Mercury Switch

Tilt Switch (Mercury Switch) comprises of a glass bulb with a drop of the liquid metal mercury, and two wire 'contacts' which are molded in.The mercury switch can be used to detect all sorts of 'motion', but in a special way. Since the mercury is liquid, it is affected by gravity, and will flow to the lowest point in the glass bulb. If the 'contacts' are below 'horizontal', the mercury will flow to that end and create an electrical connection between the two 'contacts'. The mercury switch is very useful for all sorts of applications, from water level sensing to mailbox open/closed. In our project, we have used it to detect opening/closing of door in the smart house application. It is normally very accurate, care must be taken to ensure that it cannot be jarred strongly causing it to 'false trigger'.

Figure 55 Mercury Switch in the off state

Figure 56 Mercury Switch in the on state

83

MUSN: Hardware Design

5.3.2.2

Light Dependant Resistor

We use a Light Dependant Resistor (LDR) to detect intensity of incident light. An LDR is an input transducer (sensor) which converts brightness (light) to resistance. In our application the LDR is used to measure the ambient lighting inside a room It is made from cadmium sulphide (CdS) and the resistance decreases as the brightness of light falling on the LDR increases. We can interface this LDR to ADC pin of the ATmega8 microcontroller. The status shown is either ‘light on’ or ‘light off’ depending on the intensity of incident light. The threshold can be set via the host software. This ambient light information can be used to control the states of electrical lighting via the sensor network. We used a 12.2 kΏ (2.2kΏ + 10kΏ pot) in series with the LDR to form a voltage divider for getting the Analog output.

Figure 57 LDRs in various flavours

Figure 58 Light Dependant Resistor as interfaced to the sensor network

84

MUSN: Hardware Design

Figure 59 Typical connections of a LDR

5.3.2.3

LM35 Temperature Sensor

The LM35 series are precision integrated-circuit temperature sensors, whose output voltage is linearly proportional to the Celsius (Centigrade) temperature. The LM35 thus has an advantage over linear temperature sensors calibrated in ° Kelvin, as the user is not required to subtract a large constant voltage from its output to obtain convenient Centigrade scaling. The LM35 does not require any external calibration or trimming to provide typical accuracies of ±1⁄4°C at room temperature and ±3⁄4°C over a full −55 to +150°C temperature range. Low cost is assured by trimming and calibration at the wafer level. The LM35’s low output impedance, linear output, and precise inherent calibration make interfacing to readout or control circuitry especially easy. It can be used with single power supplies, or with plus and minus supplies. As it draws only 60 µA from its supply, it has very low self-heating, less than 0.1°C in still air. The LM35 is rated to operate over a −55° to +150°C temperature range, while the LM35C is rated for a −40° to +110°C range (−10° with improved accuracy). The LM35 series is available packaged in hermetic TO-46 transistor packages, while the LM35C, LM35CA, and LM35D are also available in the plastic TO-92 transistor package. The LM35D is also available in an 8-lead surface mount small outline package and a plastic TO-220 package.

Figure 60 Extract from LM34 Datasheet

85

MUSN: Hardware Design

Features: • • • • • • • • • • •

Calibrated directly in ° Celsius (Centigrade) Linear + 10.0 mV/°C scale factor 0.5°C accuracy guarantee able (at +25°C) Rated for full −55° to +150°C range Suitable for remote applications Low cost due to wafer-level trimming Operates from 4 to 30 volts Less than 60 µA current drain Low self-heating, 0.08°C in still air Nonlinearity only ±1⁄4°C typical Low impedance output, 0.1 W for 1 mA load

Since the temperature range for this sensor is from +2-+150 degree Celsius, it can be used for home monitoring applications. We have interfaced the LM35 sensor via the onboard ADC of ATmega8.

Figure 61 LM35 Sensor

Figure 62 LM35 Interfaced to the network

86

MUSN: Hardware Design

5.3.2.4

Humidity Sensor

The humidity sensor used is of the SY-HS 220 series. As per the datasheet, a look up table is fed into the microcontroller, onto which this humidity sensor is connected. Depending upon the current humidity level a corresponding voltage appears at the Vout terminal, and microcontroller accordingly sets the humidity. This reading is then displayed on the host computer.

Figure 63 Humidity Sensor Configuration

Table 10 Humidity Sensor Specifications

87

MUSN: Hardware Design

Table 11 Look up table : Standard specifications corresponding to relative humidity

%RH SPECIFICATIONS HS-220 30 990 Ώ 35 1160 Ώ 40 1300 Ώ 45 1490 Ώ 50 1650 Ώ 55 1820 Ώ 60 1980 Ώ 65 2150 Ώ 70 2310 Ώ 75 2480 Ώ 80 2640 Ώ 85 2810 Ώ 90 2970 Ώ 95 -%RH SPECIFICATIONS SPECIFICATIONS SPECIFICATIONS 10°C 25°C 40°C 20 0.012 mV 0.017 mV 0.019 mV 30 40 50 60 70 80 90

0.042 mV 0.128 mV 0.330 mV 0.601 mV 0.808 mV 0.919 mV 0.972 mV

0.053 mV 0.156 mV 0.382 mV 0.602 mV 0.794 mV 0.904 mV 0.958 mV

0.053 mV 0.153 mV 0.355 mV 0.573 mV 0.768 mV 0.884 mV 0.946 mV

Rt = 50kΏ at 25 °C Rt = 108.3kΏ at 10 °C Rt = 24.46kΏ at 20 °C

88

MUSN: Hardware Design

Figure 64 The Humidity Sensor

5.3.2.5

Motion Detector (Passive Infrared + Microwave)

The motion detector used here DP-550 detector that combines a passive infrared (PIR) and a microwave (MW) sensor. The alarm signal is transmitted when both sensors detect the motion at the same time. A ‘high’ is obtained at the output of the detector, and the microcontroller is triggered. This sensor is mounted near the ‘Safe’ in the home, where reliability in intrusion detection has to be superior. The detector consists of an Infrared sensor which forms the basis of the working of this detector. The sensor is made of a crystalline material that generates a surface electric charge when exposed to heat in the form of infrared radiation. When the amount of radiation striking the crystal changes, the amount of charge also changes and can then be measured. Hence whenever there is motion in front of this sensor, the red led will lit, as it detects this motion. Specifications: 1. 2. 3. 4. 5. 6. 7. 8. 9.

Power supply- 9 ~ 16 VDC, 12 VDC typical Current Drain- 30mA @ 12 VDC Infrared Sensor- Dual Element, pyroelectric Microwave Sensor-DRO,Patch Antenna Alarm period-1.5~2.5 seconds Alarm output-NC/NO, 30 VDC, 0.2A max Tamper protection-NC,screw release activated Mounting height-1.8~3.6 meter Detectable Speed-0.1~3 meters per second

89

MUSN: Hardware Design

Figure 65 The internals of the Motion Detector

Figure 66 Photo of the Motion Detector

90

MUSN: Hardware Design

5.3.2.6

Gas Leakage Detector

The Gas Leakage detector used here is of the SL-88 family. This household gas leaking detector with advanced low-current gas sensitivity components, enables detect the gas leaked in time, then sends out the alarm correctly.

Figure 67 Gas Leakage Detector

Figure 68 Gas Leakage Detector Connections

Table 12 Specifications of the Gas Leakage Detector

Induced gas Power input Operating current Alarm density Buzzer level Operating temperature Stableness Repetition Alarm density error Alarm pattern Size

Coal gas/ Natural gas/ LPG 220v 50hz (household) 50ma – 400ma 10% LEL ≥ 70db/m -10°c ~+55°c ≤ ± 5% LEL ≤ ±5% LEL ≤ ±5% LEL Flash and sound alarm Shut off Gas valve/Network alarm signal 120 x 70 x 44 mm (lh-88)

91

MUSN: Hardware Design

Table 13 Indicators on the Gas Leakage Detector

RED LED FLASH YELLOW LED FLASH YELLOW LED ON YELLOW LED OFF GREEN LED FLASH GREEN LED ON GREEN LED OFF

Gas leak Valve controller open Valve controller unconnected or error Valve controller close Running the inside sensor Working normally Power off or sensor deployed

Figure 69 Photo of the Gas Leakage Detector

92

MUSN: Hardware Design

5.3.2.7

Infrared Proximity Sensor (Active)

Infrared proximity sensors work by sending out a beam of IR light, and then computing the distance to any nearby objects from characteristics of the returned (reflected) signal. Proximity sensors are used for position sensing in industries as diverse as aircraft, ordnance, marine, mass transit and so on. They are well suited to applications with particularly demanding requirements on temperature, vibration, and shock. We have mounted the Infrared Proximity Detector near the Main entrance to keep a track of the number of people entering or leaving the home.

Figure 70 Infrared Proximity Sensor

5.3.2.8

Smoke Detector

The Smoke Detector is a sensitive yet rugged, state-of-the-art protection device that is designed for use in hazardous industrial and commercial locations. The detector is designed to operate effectively with both slow smoldering and fast burning fires. The photoelectric smoke detector uses a solid-state infrared emitting diode (IRED) and a light sensing photovoltaic cell arranged in a labyrinth assembly. The labyrinth permits free access to smoke but restricts external light. Because of its critical function to the operation of the detector, each IRED is selected with extreme care and is subjected to rigorous pre-production testing to ensure long-term reliability and performance.

93

MUSN: Hardware Design

During normal operation (no smoke), the detector samples the air approximately every four seconds for a period of less than one millisecond. The photovoltaic smoke cell, which is placed at an angle to the pulsed invisible light source, is sensitive to the infrared light in the specified frequency emitted by the IRED light source and is designed to receive a signal only when the pulsed IRED source is activated. When smoke enters the chamber, the light from the IRED reflects off the smoke particles and reaches the photovoltaic smoke cell. When the amount of light reflected by smoke reaches the factory set threshold level, the smoke alarm circuit is actuated. The detector will respond to a slow smoldering fire when smoke in the chamber reaches the preset sensitivity setting, typically 1.5%. If a fast burning fire should occur, including fires in flammable liquids and other materials such as plastics that generate black smoke, the abnormally rapid movement of smoke into the detection chamber is sensed by a special rate compensating circuit. An increase in smoke within the detection chamber that exceeds a preset rate causes the rate compensation circuit to increase the intensity of the light source, which increases detector sensitivity. If the smoke continues to build at this rate, an amplifier circuit is triggered and the unit generates an alarm. If not, the detector reverts to normal sensitivity. In normally smoky atmospheres the detector will not go into alarm as long as the concentration is less than the fixed sensitivity of the detector. This results in a sensitive and positive response with the lowest potential for unwanted alarms.

Figure 71 Smoke Detector

94

MUSN: Hardware Design

6 Elecrama Experience and Future Scope

95

MUSN: Hardware Design

6.1 The Elecrama Experience Industrial electrical and electronics manufacturer's Association (IEEMA) organizes an international level exhibition for electrical and electronic goods under the banner of 'Elecrama' biennially. This year ‘Elecrama 2006' the 7th International exhibition of Electrical, Professional electronics and Allied Products was held in Mumbai at Bombay Exhibition Center from 18th to 22nd January, 2006. Elecrama is a platform where the best of industries, both Indian and multinational showcase their cutting edge technologies and cost effective products. About 1,500 companies participated in the exhibition with visitor count reaching up to 20,000 each day. The exhibition was segregated into many halls such as International Pavilion, Power Electronics Pavilion, Industrial Automation Pavilion etc. A small but significant part of the exhibition was the Students’ Pavilion, which brought forward many constructive ideas. The Elecrama 2006 organizing committee received up to 80 entries from various colleges across India. The committee short-listed 41 competitive projects. The criteria of selection were as follows • • • •

Practical approach Innovative Idea Market value Technological content

Our project “Multi-Utility Sensor Network” was selected to represent our college at the “Elecrama 2006” contest. The contest stretched over a period of 5 days. We reached the contest venue a day before the contest to feel the pulse of the exhibition. Over the next few days a crowd of people and many distinguished businessmen and top-level executives visited our project stall and gave us their valuable feedback. The feedback comprised a gamut of ideas Market oriented approach, Technical limitations, aesthetic value of the product and many more interesting comments. All visitors appreciated the novelty of our project. They were especially impressed by our implementation of “Kaun Banega Crorepati” and thanks to this implementation we were easily amongst the most popular stalls in the Students’ Pavillion. What encouraged us even more was the constant interest from people from Industry. They were impressed by the utilitarian value of our project and even enquired if we could implement similar networks for them in their industrial plants. All in all, 'Elecrama 2006' provided us with a platform through which we could display our product in front of the masses and only through this, did we realize the market potential of our product. It also helped us in interacting with eminent people who were well aware of the market technicalities and their feedback was a morale booster. It was a superb experience which we shall always cherish.

96

MUSN: Hardware Design

6.2 Future Scope 6.2.1

Voting Pads

6.2.1.1

Increasing Capacity

The current implementation of the network being used for the game show voting pads comprises of nodes consisting of an ATMega8 microcontroller and a MAX485/DS75176 RS485 Transceiver. They are connected to a single RS 485 bus segment. Only 32 nodes are supported by such a design. MAX487 Transceivers can be used to support up to 128 nodes per segment (shown below).

Figure 72 KBC Studio

The Studio which comprises of such a network can hold up to 200 audience members; hence two segments of the RS485 bus will be able to accommodate everyone. 6.2.1.2

Fastest finger first

Only by a few suitable changes in the software, “Fastest finger first” can also be implemented: • •

Broadcast packets are incorporated for starting and stopping internal timers and counters. Larger reply packets may be used with additional information about time taken to select a choice.

The actual implementation would include the following steps: 1. Host sends broadcast packet to reset all nodes and start their timers. 97

MUSN: Hardware Design

2. Nodes start timer and wait for keypress. 3. At end of the time allotted for answering question, host sends broadcast packet to stop the timers. 4. Host queries all nodes for the answer selected and time taken by the participant to do so. 6.2.1.3

Product Engineering

A much compact and easy to use enclosure can be used (Figure 73). Push button switches with built-in LEDs as follows can be used for convenience (Figure 74). Twisted 2 pair or 5 pair cables and improved connectors as shown can be used for better reliability of the network (Figure 75 and Figure 76).

Figure 73 Suggested Enclosures

98

MUSN: Hardware Design

Figure 74 Push Button switches with LEDs

Figure 75 Twisted Pair

99

MUSN: Hardware Design

Figure 76 Suggested Connectors

6.2.1.4

Use of better Bus standards: CAN/Ethernet

Controller Area Network (CAN), is a serial bus network of microcontrollers that connects devices, sensors and actuators in a system or sub-system for real-time control applications. There is no addressing scheme used in controller area networks, as in the sense of conventional addressing in networks. Rather, messages are broadcast to all the nodes in the network using an identifier unique to the network. Based on the identifier, the individual nodes decide whether or not to process the message and also determine the priority of the message in terms of competition for bus access. This method allows for uninterrupted transmission when a collision is detected. CAN can theoretically link up to 2032 devices (assuming one node with one identifier) on a single network. Ethernet is the most widely-installed local area network (LAN) technology. Ethernet uses a bus or star topology and supports data transfer rates of 10 Mbps. An Ethernet LAN typically uses coaxial cable or special grades of twisted pair wires. Ethernet is also used in wireless LANs. Devices are connected to the cable and compete for access using a Carrier Sense Multiple Access with Collision Detection (CSMA/CD ) protocol.

100

MUSN: Hardware Design

6.2.2

Building Monitoring and Control

As an extension to the home monitoring implementation, a security system can be built in a building. Newer buildings have ducts for wiring for networks like Cable TV, Telephone, Internet on LAN, Ethernet infrastructure already in place. Embedded Ethernet boards can be used on each floor which are connected to the building’s Ethernet Network. The nerves of the network are formed by RS485/CAN sub-networks. The sensor nodes with their sensors form the nerve endings.

Figure 77 Typical Floor Plan for Building Monitoring and Control

Each Embedded Ethernet Board as shown in Figure 77 as the blue node above has the following components: • • •

ATMega128 (or AT90CAN128) Ethernet Interface with NutOS providing TCP/IP Stack Dual RS485 ports (Redundancy) or a CAN interface

The sensor network could be administered by any PC connected to the building’s Ethernet Network. The Gateway can restrict access to the range of IP addresses allotted to each floor to maintain security. Each Embedded Ethernet board will collect data from its RS485/CAN Sub-network sensor nodes and forward that data to the Administration PC. A person living in one of the apartments in the building can login to the buildings web server using a login name and password. The web server maintains a network graph 101

MUSN: Hardware Design

of the whole sensor network. The resident can look at the sensor layout of his own home and can configure various parameters of his home manually. The system will have a distributed UPS. All Ethernet boards will have their own small rechargeable battery backup. This will help in case of fire and other disasters. The network can automatically shutdown the electric supply to the affected sector of the building and open water valves for fire control. The sensor network can be used to log sensor data which might be useful later in case of crimes. The building can have its own mini weather station. The network can collect data such as water supply/electric usage characteristic of residents in a particular flat. The residents can use this data to help cut down their utility bills. The network can be used to control solar cells/water heater mounted on the roof for optimum alignment towards the sun. It can control the water levels in overhead tanks. It can be used to implement traffic management for the Elevator System.

6.2.3

Industrial Monitoring and Control

In any industrial application, huge data systems need to be installed to perform various operations such as data collection, processing, communication, and display. To connect the controller unit with sensors and actuators, many process and manufacturing facilities still include field multiplexers or multi-wire connections (based on 4-20mA loops or 0-10V circuits). Because the wiring required in the older systems is enormous, modern plants often save wiring effort by employing a serial, real-time, data-link industrial network (field bus system) for process and manufacturing control. Fieldbus systems are similar to the widespread Ethernet office networks, in that a single bus connects all devices on one network to a central controller. Not only does that arrangement require substantially less wire, it also increases the system modularity. All devices are addressed via software, so any device can be connected to any socket along the network. The master detects which device is connected to the network, and initiates the action required to start communications.

102

MUSN: Hardware Design

References [1]

ATmega8 AVR Datasheet

[2]

Richard Barnett, Larry O’Cull and Sarah Cox - Embedded C Programming and the Atmel AVR (Thomson Publishing)

[3]

Leitner Harald - The GNU Ansi C compiler for AVR : Getting started notes (haraleit.pdf)

[4]

Rich Neswold - GNU Development Environment for the AVR Microcontroller

[5]

WinAVR man Pages

[6]

Thesis by Seth Edward-Austin Hollar - COTS Dust (cotsdust.pdf)

[7]

Jan Axelson - Serial Port Complete

[8]

Rajkamal - Embedded Systems : Architecture, Programming and Design

[9]

www.avrfreaks.net

[ 10 ] Jan Axelson - Designing RS485 Networks (Circuit Cellar June 1999) [ 11 ] Eagle PCB Layout Editor Documentation

103

MUSN: Hardware Design

Index A ADC..5, 35, 37, 38, 39, 42, 52, 53, 54, 55, 56, 57, 59, 84, 86 ADSC ................................................... 54, 55, 56 Ajax .................................................................... 7 Alarm .......................................................... 89, 91 analog...................................35, 37, 42, 52, 54, 57 architecture ............................... 24, 35, 38, 42, 43 asynchronous ..4, 9, 21, 22, 24, 26, 30, 47, 48, 49, 50 ATmega8 ..5, 6, 24, 36, 37, 38, 39, 40, 41, 52, 60, 66, 69, 84, 86, 103 Atmel................................................... 24, 35, 103 AVRiii, 6, 7, 24, 34, 35, 36, 37, 38, 42, 43, 44, 47, 103 AVRStudio ......................................................... 7 B Balanced ........................................................... 12 biasing................................4, 9, 13, 14, 59, 63, 66 Block diagram .................................................. 60 Boot ...................................................... 37, 38, 43 Bridge ....................4, 6, 64, 66, 69, 70, 71, 72, 79 Broadcast .......................................................... 97

Flash ............................. 35, 36, 37, 38, 42, 43, 91 full duplex................................................... 17, 18 G Gas Leakage detector........................................ 91 ground ...12, 14, 15, 16, 26, 27, 28, 30, 31, 56, 60, 66 H half duplex .................................................. 17, 18 Half Duplex........................................... 10, 19, 59 handshaking ................................................ 27, 32 Home Monitoring ............................... 6, 7, 78, 81 Host computer............................................. 4, 6, 7 humidity...................................................... 87, 88 I impedance ......9, 13, 14, 15, 16, 57, 59, 65, 85, 86 Infrared ................................................... 5, 89, 93 in-system ........................................................... 35 ISP .......................................................... 6, 65, 66 J Java ............................................... 6, 7, 32, 79, 80 JRE................................................................ 6, 32

C

K

cadmium sulphide............................................. 84 Calibrated.................................... 5, 36, 38, 41, 86 carrier detect ..................................................... 28 CAT5 ................................................................ 66 charge-pump ..................................................... 31 clear to send ...................................................... 28 connectors............................60, 65, 66, 69, 72, 98 Controller Area Network ................................ 100 crystal.........................6, 26, 36, 50, 65, 66, 72, 89 CSMA/CD ...................................................... 100

Kaun Banega Crorepati............................... 78, 96

D Data Circuit-terminating Equipment................. 27 Data Terminal Equipment................................. 27 DCE ............................................................ 27, 28 DDxn .......................................................... 45, 46 differential ................................ 11, 12, 14, 16, 65 driver4, 6, 9, 12, 13, 14, 15, 18, 19, 21, 29, 44, 46 DS75176 ................................6, 10, 60, 64, 79, 97 DTE ............................................................ 27, 28 DTR ............................................................ 27, 28

L Layout ..........3, 60, 62, 66, 68, 69, 71, 72, 74, 103 LDR ............................................................ 84, 85 LEDs ......................... 6, 59, 60, 65, 66, 78, 98, 99 Light Dependant Resistor ................................. 84 LM35 .......................................................... 85, 86 Look up table................................................... 88 M Mark............................................................ 22, 29 MAX485 5, 6, 9, 10, 19, 20, 60, 64, 66, 69, 79, 97 measurand ........................................................... 3 Mercury Switch................................................. 83 motion detector ................................................. 89 multi-drop ................................................. 4, 9, 11 Multi-Utility Sensor Network ..................... 78, 96 N noise.........3, 12, 14, 22, 26, 29, 30, 50, 52, 56, 65

E

O

Eagle ................................................. 3, 6, 60, 103 EEPROM .............................35, 36, 37, 38, 59, 66 Elecrama ..................................................... 95, 96 Ethernet..............................4, 9, 78, 100, 101, 102

oscillator ............................................... 36, 37, 66

F Fastest finger first ....................................... 78, 97

P packet........................................ 76, 79, 81, 97, 98 parity ........................................... 9, 22, 23, 24, 47 Pavillion............................................................ 96 PCB..............3, 60, 62, 66, 68, 69, 71, 72, 74, 103

104

MUSN: Hardware Design performance .................3, 5, 32, 35, 38, 42, 52, 93 PIR.................................................................... 89 PORTxn ...................................................... 45, 46 prescaler...................................................... 49, 54 prototype............60, 61, 63, 64, 65, 66, 69, 72, 79 proximity .......................................................... 93

Space............................................... 22, 29, 42, 44 SRAM ................................................... 36, 38, 43 Start..................................... 22, 23, 24, 25, 47, 54 Stop ........................................... 22, 23, 24, 25, 47 synchronous .............................. 21, 22, 24, 47, 48

R

Temperature .................................................. 5, 85 termination .................................. 9, 13, 14, 15, 65 transmitter ........................... 21, 22, 23, 24, 25, 69 TTL ..................5, 6, 12, 14, 15, 29, 30, 31, 32, 33 twisted pair.................................. 6, 9, 13, 16, 100 TXD ............................................................ 27, 69

registers........................................... 35, 42, 43, 45 regulator................................................ 59, 60, 66 reliability....................................... 3, 6, 89, 93, 98 request to send .................................................. 28 ring indicator..................................................... 28 RISC ....................................................... 5, 35, 38 RJ45...................................................... 66, 69, 72 RS-232 ..4, 6, 9, 11, 17, 22, 25, 26, 27, 29, 30, 31, 32, 64, 65, 66, 69, 70, 71, 79 RS-485 4, 5, 6, 8, 9, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 22, 26, 32, 59, 64, 65, 66, 69, 70, 71, 75, 76, 79 RTS....................................................... 27, 28, 32 RXD............................................................ 27, 69 S Schematic...........44, 53, 61, 66, 67, 69, 70, 72, 73 sensor networks ............................................ 3, 36 serial .4, 6, 7, 9, 21, 23, 24, 26, 27, 30, 32, 37, 47, 50, 60, 65, 100, 102 Smoke Detector .......................................... 93, 94

T

U UART ....................................... 24, 25, 26, 29, 35 UBRR ................................................... 49, 50, 51 USART ....5, 24, 37, 38, 47, 48, 49, 59, 64, 65, 69 V voltage divider .................................................. 84 Voting Pad ........................................ 6, 72, 79, 80 Voting Pads............................................. 7, 78, 97 W Who wants to be a Millionare ........................... 78 WinAVR ..................................................... 7, 103 Windows ................................................. 6, 32, 80

105