EX1A DIGITAL CIRCUITS AND SYSTEMS Introduction to the course content and methods TEAM NUMBER: 1 Due date: 7/02/2014 Active members Roles: (reporter, simulator, etc.) (1) Yanqueleh Molina Tenorio (2) Oriol Torán Roca (3) Andrea Garós Moyano
Reporter, Simulator Reporter, Simulator Reporter, Simulator
You have to use this template in order to solve the EX1A, that appears in the site digsys.upc.es. Read carefully the EX1A.docx and follow the instructions of your instructor in order to present the results. 1 Abstract (outline in English the most relevant results and the tools you have used to solve the exercise, 10 lines minimum) With this project we learnt to work in working group, cooperating and distributing the work and helping each other’s with the problems that we found in our way. Sometimes in work individual it is an result, but, when you contrast with other member it is other. Then group need debugging or see the mistakes from work and solve. While a member group it is working an apartat from work other member it can searching from how running new program and it share that knowledge with rest members. About work worst is download programs and learn how I do correct running without any errors. First of all we simulated the circuits in Proteus, after we changed the components by more realistic ones and adjusted the resistor to work with appropriate voltage and current value, for example use 74LSXX family for logic gates and binari convert to decimal(BCD) and other divece like this resistor and light emiting diodes. 2 Objectives (indicate 5 objectives minimum, in English) The objective about this work is: Learn for basic knowledge about logic gates and truth tables. Simulate circuits with Proteus. Make equation algebrian boole for himself and with programms, for example wolframalpha. Simulate a circuits with logic gates with code program in simulators. Learn a new form for share files with the world trougheportfolio, google sites tools.
3 Solution to the questions, analysis, designs, projects (Include a brief description of each question) Analysis 1: Using Proteus and schematics Project name and folder
Projects under development
Analysis_1
Running Proteus and schematics. Logic equations.
Section
d), e), f)
Execution phase ( , , )
Student engineer in charge
d) Search a paper in the web and explain the main characteristics of the cooperative learning methodology. En el aprendizaje cooperatico trata de que el trabajo en equipo estimule a los integrantes y contribuyan al aprendizaje del grupo. Este consta de cinco principios básicos: 1) Interdependencia positiva: Se debe entender que los beneficios propios son beneficios de grupo, de esta manera se crea compromiso con el éxito de otras personas. Se reparten las tareas y debes ocuparte de hacerla y asegurarte de que tus compañeros lo aprendan. 2) Interacción estimuladora: Todos los miembros del grupo estan al mismo nivel, se debe permitir a todos los integrantes ayudar y del mismo modo ser ayudados. Ademas, se debe propiciar el esfuerzo de todos los individuos para conseguir los objetivos del equipo. 3) Habilidades Interpersonales y de equipo: En un grupo las habilidades sociales son muy importantes, se debe saber ejercer la dirección, generar confianza entre los miembros, tomar decisiones, comunicarse y manejar de conflictos. 4) Responsabilidad individual y grupal: Cada individuo del grupo debe realizar su tarea y despues ponerla a disposicion del grupo para que puedan aportar ideas i nuevos conceptos asi como aprender de ellos. 5) Procesamiento grupal: Cada individuo debe autoevaluarse en que medida está contribuyendo para conseguir los objetivos de grupo. Revisar que acciones resultaron útiles y cuales no y que acciones se realizaron de forma incorrecta.
e) Redraw the logic circuit in Fig. 2 (the one your instructor has prepared for you), so that it can be easily captured in Proteus ISIS and placed inside a subcircuit box. For instance, open the Proteus 8.0 file example below in Fig. 3 and modify it conveniently. Simulate it and write down its truth table. Logicstate y logicprobe sustituido por botones y un led. Circuit 1E
Circuit 1F
Para que en la salida se encuentre una corriente de 5mA y 10mA se aplica la siguiente ecuación:
V o −V Led I
=R
Obteniendo valores para cada una de las corrientes 490 Ω y 202 Ω respectivamente.
Circuit 1E
Circuit 1F
Substituyendo las puertas idealas por puertas de la família 74LSXX. Circuit 1E
Circuit 1F
Open collector, cuando la Vi>0.7 V deja pasar corriente al ground mientras que si Vi<0.7 V no deja pasar y activa la salida logica, es el comportamiento de una puerta logica NAND.
f) Analyse the circuit to obtain its algebraic equation for the output. These Boolean algebraic expressions constitute the starting point of the analysis process which can be found in the Unit 1.3: Analysis of a digital circuit (analysis concept map). Truth table L=((S1’+S0+A+B’) ((B+S0)A S1 (1))’ M= (S1’A’S0’B’)’(S0’+A+B’)((S1’(S0+B’))+(A’+(B’(S0’+A’))))(S0’+S1+A’+B) Las ecuaciones simplificadas son: L=(S1 S0’ A’ B’) + ( S1 A B) + (S1 S0 A) M= S0’S1’(A
B) + S0’S1(A’
B) + S0S1’A’ + S0B’ (S1
A)
nº
S1
S0
A
B
L
M
0
0
0
0
0
0
0
1
0
0
0
1
0
1
2
0
0
1
0
0
1
3
0
0
1
1
0
0
4
0
1
0
0
0
1
5
0
1
0
1
0
0
6
0
1
1
0
0
0
7
0
1
1
1
0
1
8
1
0
0
0
0
1
9
1
0
0
1
1
1
10
1
0
1
0
0
1
11
1
0
1
1
1
0
12
1
1
0
0
0
1
13
1
1
0
1
0
0
14
1
1
1
0
1
0
15
1
1
1
1
1
0
Analysis 2: A simple combinational circuit (analysis flow Chart) Project name and folder
Projects under development
Analysis_2
Analysis of a combination circuit based on logic gates
Section
f) g)
Execution phase ( , , )
Student engineer in charge
g) Obtain the truth table using WolframAlpha (Wolfram Research) (see Unit 1.4) from the initial circuit’s equation. This outstanding software that really calculates everything, is going to be your first electronic design automation (EDA) tool, because it will save you the task of minimising the algebraic expression by hand, in the same way a digital calculator spares you the need to solve logarithms, square roots and other complicated mathematical stuff. Compare the truth table obtained which the one deduced by means of calculations (the sum of products (SoP) and sum of minterms, or the product of sums (PoS) and the product of maxterms); and the one obtained previously in e) after simulations in Proteus. Wolfram crea las tablas de al verdad empezando cuando es todo 1, usa la nomenclatura de True para 1 i False para 0. Las entradas de wolfram a,b,c y d corresponden a S1,S0,A y B respectivamente. Tabla de la verdad mediante wolfram: Circuit 1E
Circuit 1F
Design 1: Writing and simulating a circuit in VHDL Project name and folder
Projects under development
Section
Design_1
Describe and simulate a combination circuit using VHDL
h) i) j)
Execution phase ( , , )
Student engineer in charge
h) Search the subject books or the Internet to find a flowchart to describe the PLD/FPGA design flow which will be used once and again through Chapters I, II and III: from circuit specifications using a hardware description language or schematics to final verification using development boards. Para responder este apartado hemos utilizado dos fuentes, buscadores de internet y la pagina web de la asignatura.
En internet, hemos podido observa muchos y muy distintos esquemas de flujo pero ninguno demasiado concreto. Ejemplo Izquierda. En cambio, el esquema que encontramos en la página de la asignatura es mucho más concreto y clarificador ya que, es específico del programa que utilizamos en clase. Podemos observar los pasos y funciones de cada programa (ispLEVER, Synplify y ActiveHDL.
i) Browse the Electronic Components page from our web; and choose a given CPLD/FPGA development board from the list corresponding to a given manufacturer (Lattice, Altera or Xilinx). For instance, the “Hardware Design JK Experimentierplatine für die Digitaltechnik” in case of using the Lattice CPLD ispMACH4128V chip, analyse its datasheet and other relevant materials, and draw a block diagram to include the programmable chip, input switches and pushbuttons, and output LED’s or 7segment displays and the number of pins involved.
j) Deduce and sketch the electrical circuit to interface switches and pushbuttons and to drive LED’s and 7segment displays. Are there all the input pullup resistors and the output limiting resistors? Compare these real circuits from the development boards to your Proteus circuits in section e). A la hora de implementar el display de 7 segmentos usando el decodificador 74LS48 a partir de la décima combinación no se muestran las letras A hasta la F, pero, se muestra la imagen correspondiente a la tabla de la verdad del datasheet.
Simulacion en Lattice Para empezar a utilizar los programas necesarios en las siguientes sesiones (ispLEVER, synply y Active HDL) hemos realizado todos los pasos de creación de archivos y programación para poder simular el funcionamiento de los circuitos. VHD A sample design A combinational circuit produced from the equations
http://digsys.upc.es/ed//CSD/units/Ch1/U1_07/Unit1_7.html
LIBRARY ieee; USE IEEE.STD_LOGIC_1164.all; ENTITY Circuit_1A IS PORT ( S
: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
A,B : IN STD_LOGIC; L
: OUT STD_LOGIC
); END Circuit_1A; ARCHITECTURE algebraic_equation OF Circuit_1A IS BEGIN Let's copy the equations from WolframAlpha, which is pretty much VHDL syntax Let's change S1, S0 > S(1) and S(0) and be aware of the brakets! L <= not( (A and B) or not( not(S(0)) or not(A) ) ) and ( S(1) or not(S(0)) or not(B) ) and (not( S(1) and not(S(0)) and not(A) and not(B) ) ) ; L <= (S(1) and S(0) and A) or (S(1) and not S(0) and B);
L <= ( NOT S(1) OR S(0) OR A OR not B) and not ((B OR S(0))AND A AND S(1)) ;
END algebraic_equation; VHT VHDL Test Bench Created from source file Circuit_1A.vhd 03/06/14 23:14:26
Notes: 1) This testbench template has been automatically generated using types std_logic and std_logic_vector for the ports of the unit under test. Lattice recommends that these types always be used for the toplevel I/O of a design in order to guarantee that the testbench will bind correctly to the timing (postroute) simulation model. 2) To use this template as your testbench, change the filename to any name of your choice with the extension .vhd, and use the "source>import" menu in the ispLEVER Project Navigator to import the testbench. Then edit the user defined section below, adding code to generate the stimulus for your design. LIBRARY ieee; LIBRARY generics; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; USE generics.components.ALL; ENTITY testbench IS END testbench; ARCHITECTURE behavior OF testbench IS COMPONENT Circuit_1A PORT( S : IN std_logic_vector(1 downto 0); A : IN std_logic; B : IN std_logic; L : OUT std_logic ); END COMPONENT;
SIGNAL S : std_logic_vector(1 downto 0); SIGNAL A : std_logic; SIGNAL B : std_logic; SIGNAL L : std_logic; constant Min_Pulse: time:=12.5us; BEGIN uut: Circuit_1A PORT MAP( S => S, A => A, B => B, L => L ); *** Test Bench User Defined Section *** tb : PROCESS BEGIN wait for Min_Pulse*3; S(1) <= '0'; S(0) <= '0'; A <= '0'; B <= '0'; wait for Min_Pulse*3; S(1) <= '0'; S(0) <= '0'; A <= '0';
B <= '1'; wait for Min_Pulse*3; S(1) <= '0'; S(0) <= '0'; A <= '1'; B <= '0'; wait for Min_Pulse*3; S(1) <= '0'; S(0) <= '0'; A <= '1'; B <= '1'; wait for Min_Pulse*3; S(1) <= '0'; S(0) <= '1'; A <= '0'; B <= '0'; wait for Min_Pulse*3; S(1) <= '0'; S(0) <= '1'; A <= '0'; B <= '1'; wait for Min_Pulse*3; S(1) <= '0'; S(0) <= '1';
A <= '1'; B <= '0'; wait for Min_Pulse*3; S(1) <= '0'; S(0) <= '1'; A <= '1'; B <= '1'; wait for Min_Pulse*3; S(1) <= '1'; S(0) <= '0'; A <= '0'; B <= '0'; wait for Min_Pulse*3; S(1) <= '1'; S(0) <= '0'; A <= '0'; B <= '1'; wait for Min_Pulse*3; S(1) <= '1'; S(0) <= '0'; A <= '1'; B <= '0'; wait for Min_Pulse*3; S(1) <= '1';
S(0) <= '0'; A <= '1'; B <= '1'; wait for Min_Pulse*3; S(1) <= '1'; S(0) <= '1'; A <= '0'; B <= '0'; wait for Min_Pulse*3; S(1) <= '1'; S(0) <= '1'; A <= '0'; B <= '1'; wait for Min_Pulse*3; S(1) <= '1'; S(0) <= '1'; A <= '1'; B <= '0'; wait for Min_Pulse*3; S(1) <= '1'; S(0) <= '1'; A <= '1'; B <= '1'; END PROCESS; *** End Test Bench User Defined Section ***
END; Stating the cooperative group ePortfolio Project name
Projects under development
ePortfolio
Open the cooperative group ePortfolio.
Section
k)
Execution phase ( , , )
Student engineer in charge
k) Here, some tasks to “activate” you professionally in Internet and the “cloud”. ∙ Open an account in Google Docs if you still do not have one, and use it to share documents with your cooperative team members. Another convenient alternative or complementary tool is Dropbox.com, they even have special offers for students. You can use also the Microsoft SkyDrive or the Google Drive. 4 Dedication time to solve the exercise
Member 1 Member 2 Member 3
Individual 9h 9h 9h
In group 10h 10h 10h
5 Selfassessment
Member 1 Member 2 Member 3
8 9 8
6 Reflection about the development of the exercise (Describe the meetings outside the class, difficulties in solving the exercise, etc) Alguna de las dificultades que nos provocaran detenernos un poco y analizar mucho fue la parte de la algebra booleana, ya que no coincida en algunos minterns con la tabla de verdad del circuito. Al final después de repetir varias veces el proceso encontramos el error y lo solucionamos exitosamente. Alguna otra dificultad fueron los software’s ya que después de descargarlos e instalarlos teniamos que hacer alguna modificación par aceptar las licencias. En cuanto a la simulacion de lo circuitos en proteus no tuvimos complicaciones, tampoco en
hacerle cambios a los circuitos así como crear la tabla de verda, los minterns y la ecuación de los circuitos a partir de observar el circuito. 7 References www.digsys.upc.es http://www.datasheetcatalog.com/ G1: 1- Figure captions, table captions and references must be cross referenced in the text. 2- You have to include the RTL diagram from synplify, of Circuit1_E and Circuit1_F. 3- You haven’t simulated the circuits with Active_HDL. 4- You have to enumarate the references.
Grade=8
