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PAPER

Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa

Formula-Based Method for Capacitance Extraction of Interconnects with Dummy Fills Atsushi KUROKAWA†a) , Member, Akira KASEBE†† , Nonmember, Toshiki KANAMOTO††† , Member, Yun YANG†††† , Zhangcai HUANG†††† , Student Members, Yasuaki INOUE†††† , and Hiroo MASUDA† , Members

SUMMARY In advanced ASIC/SoC physical designs, interconnect parasitic extraction is one of the important factors to determine the accuracy of timing analysis. We present a formula-based method to efficiently extract interconnect capacitances of interconnects with dummy fills for VLSI designs. The whole flow is as follows: 1) in each process, obtain capacitances per unit length using a 3-D field solver and then create formulas, and 2) in the actual design phase, execute a well-known 2.5-D capacitance extraction. Our results indicated that accuracies of the proposed formulas were almost within 3% error. The proposed formula-based method can extract interconnect capacitances with high accuracy for VLSI circuits. Moreover, we present formulas to evaluate the effect of dummy fills on interconnect capacitances. These can be useful for determining design guidelines, such as metal density before the actual design, and for analyzing the effect of each structural parameter during the design phase. key words: dummy fill, capacitance extraction, capacitance formula, interconnect

1.

Introduction

With high-speed circuits, the accuracy of timing analysis for ASIC/SoC designs is becoming more and more important. In our experiences of VLSI designs using 0.13-µm technology, which is currently being mass produced, timing closure has already become a serious problem. For future designs using 90-nm technology, this timing closure problem will be even more serious. The SPICE model parameters and interconnect information, such as cross-sectional parameters and permittivities, offered from the fabrication side are the main factors in determining the simulation accuracy in the design phase. In addition, EDA tools for cell delay characterization and interconnect parasitic extraction determine the physical design quality, so EDA technologies are very important. To flatten each layer in multi-interconnect technology, chemicalmechanical polishing (CMP) is performed during the LSI fabrication phase [1]–[3]. The non-uniform metal distribution after polishing results in noticeable differences in the metal thickness due to the differences between the metallic Manuscript received June 27, 2005. Manuscript revised September 29, 2005. Final manuscript received November 14, 2005. † The authors are with STARC, Yokohama-shi, 222-0033 Japan. †† The author is with Meitec Corp., Tokyo, 104-0061 Japan. ††† The author is with Renesas Technology Corp., Itami-shi, 6640005 Japan and with Osaka University, Suita-shi, 565-0871 Japan. †††† The authors are with Waseda University, Kitakyushu-shi, 8080135 Japan. a) E-mail: [email protected] DOI: 10.1093/ietfec/e89–a.4.847

and dielectric materials. Dummy metal fills are generally inserted in spaces where there are no interconnects to maintain metal density uniformity. The dummy metal fills significantly affect the accuracy of timing analysis for physical design [4]–[8]. Some filling techniques that consider the effect of dummy fills have been reported [9]–[13]. Moreover, methods to extract interconnect capacitances that include dummy fills, such as 3-D full-wave simulation [6], [14], equivalent permittivity [5], [7], and thickness reduction [8], have been proposed. The 3-D simulation method can produce results with high accuracy. However, because large amounts of processing time are required, it is difficult to apply the method to actual VLSI designs. The equivalent permittivity and thickness reduction methods may incur more errors because of permittivity or thickness approximations [5], [7], [8]. We propose a formula-based method to extract interconnect capacitance using dummy fills with high accuracy. The method can be accomplished using the following procedure: first obtain the capacitances for various structures with dummy fills using a full-wave simulation with a 3-D field solver, then create formulas, and execute a well-known 2.5D extraction [15] in the design flow. The proposed method can extract capacitances of very large interconnect network and can maintain almost the same accuracy as a 3-D simulation. Applying the method to established designs is easy because the proposed method does not require alternations to the current VLSI design flow. The effects of dummy fills on interconnect capacitances using the 3-D field solver have been reported [4]– [8]. However, a formula-based method to evaluate the effect of dummy fills has not been reported. Therefore, we present formulas to evaluate the effects of dummy fills, including process cross-sectional structure and dummy metal size, on capacitance. We also aimed to clarify the sensitivity of certain interconnect structures that were previously unclear. We assumed the well-used uniform cross-stitch pattern in advanced VLSI designs as the dummy fill pattern. The remainder of the paper is organized as follows. Section 2 presents the formulas used to evaluate the effect of dummy fills and shows the analysis results. Section 3 presents the formula-based method to efficiently extract interconnect capacitances in an actual design flow. Finally, we present our conclusion in Sect. 4.

c 2006 The Institute of Electronics, Information and Communication Engineers Copyright


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2.

Capacitance Evaluation Due to Dummy Fills

We present the formulas used to evaluate the effect of dummy fills on interconnect capacitances. The formulas are useful for evaluating dummy fills during the design and for determining design guidelines, such as metal density and dummy metal size. 2.1 Formulas for Evaluation Some dummy fill patterns have been reported elsewhere [6], [7], [10], [13]. Recently, the fill pattern adopted in advanced VLSI designs is the placement that shifts metal fills to the X and Y directions [6], [7] as shown in Fig. 1. This pattern has the advantage in that it can maintain the uniformity of the signal line capacitance [8]. We used the uniform cross-stitch pattern with a dummy metal feature of a square. Inter dummy fills affect the interconnect capacitances, but intra dummy fills hardly affect the interconnect capacitances [8] when there is appropriate spacing between the signal lines and dummy fills. We used an interconnect structure, as shown in Fig. 2, that ignored intra dummy fills and consisted of dummy metal layers and ground planes above and below three parallel lines. We call this structure “iL A jD(G) BkDG,” where i is the number of parallel lines in the objective interconnect layer, j is the number of dummy metal layers above the objective interconnect layer, and the G in A jD(G) means that G is added if there is a ground plane above the dummy metal layer. The number of dummy layers between the interconnect layer and the ground plane below the interconnect layer is k. The G in BkDG means the ground plane below the interconnect layer. Hence, the name of the structure shown in Fig. 2 is “3L A1DG B1DG.” First, we investigated the effect of the spacing between the dummy metal fills on interconnect capacitances. The

structure, as shown in Fig. 2, consisted of a signal line width of w s =0.1 µm, a spacing of s=0.1 µm, a thickness of t=0.15 µm, a height of h=0.15 µm, a dummy metal width of wd =1 µm, and a density of D=0.4032 (40.32%). Figure 3 shows the capacitance difference with the change in spacing between the dummy metal fills shown in Fig. 1. The capacitances were obtained using a 3-D field solver [16]. From Fig. 3, we can see the effect of spacing between the dummy metal fills for shifting the dummy metal fills is negligible if the density and dummy metal width are not changed. For the following analysis, we used a constant ratio, (s x :sy :t x :ty =1:1:1:2), for the spacing between the dummy metal fills. Next, we present the formulas used to evaluate interconnect capacitances over the range of the structural parameters listed in Table 1. The range of parameters listed in Table 1 is set to cover the aspect ratios of ITRS 90 - 22-nm technologies [17]. The parameters in Table 1 are unit-less. We created quadric functions through response surface methodology (RSM) [18]. We got the coefficients of each β using the capacitances obtained from the 3-D field solver for the structural conditions listed in Table 1. Ground capacitance, Cg , per unit length between the grounds above and below the signal line, and coupling capacitance, Cc , per unit length between the parallel lines in same layer are
ws s wd t Cg =εeff β0 + β1 + β2 + β3 + β4 D + β5 α α α α  w 2 α ws s w s wd s + β6 + β11 + β12 2 + β13 2 h α α α  s 2 ws D wst ws + β15 2 + β16 + β22 + β14 α h α α swd sD st s + β25 2 + β26 + β23 2 + β24 α h α α

Fig. 3

Capacitances with ratio of spacings between dummy metal fills.

Table 1 Fig. 1

Fig. 2

Dummy fill pattern on top view.

Cross section for 3L A1DG B1DG structure.

Structural parameters used for analysis.

Parameter Signal line width, w s Spacing, s Thickness, t Height, h Dummy metal width, wd Spacing ratios between dummy metals, s x :sy :t x :ty Density, D

Values 1, 3, 5 1, 2, 3 1.5, 2, 2.5 1.5, 2, 2.5 3, 7, 11 1:1:1:2 0.2–0.6

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 w 2

wd D wd t wd + β35 2 + β36 α α h α  t 2 Dt Dα 2 + β44 D + β45 + β46 + β55 α  h α  α 2 t + β56 + β66 (1) h h  ws α wd 1 t + β4 + β5 Cc =εeff β0 + β1 + β2 + β3 α s α D α  w 2 h ws w s wd s + β6 + β11 + β12 + β13 2 α α s α  α 2 ws wst wsh + β15 2 + β16 2 + β22 + β14 αD s α α  w 2 wd α t h d + β24 + β25 + β26 + β33 + β23 s sD s s α wd wd t wd h 1 t + β35 2 + β36 2 + β44 2 + β45 + β34 αD α α D ⎫ αD  2 ⎪  t 2 h ⎪ h th ⎬ + β55 + β56 2 + β66 + β46 (2) ⎪ ⎭ αD α α ⎪ α

(3) Ct =2 Cc + Cg + β33

d

+ β34

where Ct is the total capacitance per unit length and εeff is the effective permittivity. The structural parameters have an arbitrary unit. The parameter used for adjusting the unit is α. The units for Eqs. (1)–(3) are F/m. The capacitance values are the same for structures whose cross-sectional structural parameters have similar relationships. For example, in Fig. 2, the capacitance per unit length for a structure with w s =0.1 µm, s=0.1 µm, t=0.2 µm, h=0.2 µm, wd =1 µm, and D=0.4 is the same as that of a structure with w s =1 µm, s=1 µm, t=2 µm, h=2 µm, wd =10 µm, and D=0.4. Therefore, if the structural parameters converted using α are within the range listed in Table 1, the accuracy of the formulas is guaranteed. If we want to determine the capacitances of a minimum signal line, we may set α=wmin . For example, when the w s /α in β1 (w s /α) of Eq. (1) is 1, the converted value falls within the range listed in Table 1. In general, we recommend using the minimum line width for α. Figure 4 shows the regression analysis results. The adjusted multiple correlation coefficient (R2 ) was 0.999 for Cc and Cg , and indicates a strong linear relationship. Table 2 lists the coefficients of Eqs. (1) and (2). Table 3 lists the accuracy. The error is calculated from the capacitance Cmodel using the proposed model (e.g. Eqs. (1)–(3)) with the capacitance Cexact using a field solver and is calculated as Error =

Cmodel − Cexact × 100 (%) . Cexact

Fig. 4

(a) (b) Regression analysis using 3L A1DG B1DG structure.

Table 2 Coefficients of Eq. (1) Cg and Eq. (2) Cc for 3L A1DG B1DG structure. Coef. β0 β1 β2 β3 β4 β5 β6 β11 β12 β13 β14 β15 β16 β22

Cg 1.75E-01 8.87E-03 8.57E-02 2.27E-03 −9.89E-01 −3.70E-02 2.87E-01 8.44E-04 1.48E-03 −1.88E-03 1.17E-01 −1.04E-02 3.38E-01 −1.37E-02

Table 3

Cc −7.48E-01 1.57E-01 1.66E+00 2.93E-02 3.63E-02 3.83E-02 1.68E-01 −1.25E-02 5.92E-02 2.22E-03 −1.28E-02 7.87E-03 −4.91E-03 −7.27E-01

Coef. β23 β24 β25 β26 β33 β34 β35 β36 β44 β45 β46 β55 β56 β66

Cg −1.24E-03 7.39E-02 1.35E-03 2.19E-01 1.11E-03 1.83E-02 −5.61E-03 −1.74E-02 −6.00E-01 2.71E-01 2.09E+00 9.32E-03 −1.06E-01 −4.67E-01

Cc −9.77E-04 1.45E-02 9.94E-01 −1.03E-02 −9.21E-04 −2.82E-03 1.21E-03 −3.89E-03 −6.80E-03 1.08E-02 1.63E-02 −7.93E-03 −1.95E-02 −9.42E-03

Accuracy of formulas for 3L A1DG B1DG structure. Error type Positive max error (%) Negative max error (%) RMS error (%)

Ct 2.9 −2.9 0.8

Cg 7.1 −8.1 1.6

Cc 6.3 −6.4 1.3

solver is 1,500,000, and CPU time is 242,423 seconds on two Redhat-linux-8 with two CPUs of 3.2 GHz and memory of 4 GB. Formulas used to evaluate interconnect capacitances for various structures (1L A1D B1DG, 1L A1DG B1DG, and 3L A1D B1DG), except for the structures shown in Fig. 2, are described in the Appendix. From Tables 3, A· 2 and A· 4, we can see that the accuracy of the developed formulas is reasonable, and the formulas can be utilized for evaluating the effect of dummy fills.

(4)

In Table 3, “Positive max error” means the maximum of positive error, “Negative max error” means the absolute maximum negative error, and “RMS error” is the error of the root mean square. The number of data used for obtaining the coefficients of Eqs. (1) and (2) for 3L A1DG B1DG is 729, and each formula consists of 6 parameters. We use 3 points for each parameter. The number of divisions for the field

2.2 Capacitance Sensitivity Analysis We analyzed the sensitivity of the capacitances using the capacitance formulas introduced in the previous sub-section. The sensitivity analysis results, as shown in Fig. 5, were obtained using parameters in the intermediate layer of the ITRS 90-nm technology. The Y-axis is sensitivity and is defined as

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 S ensitivity = Cob ject Cbase

(5)

where Cob ject is the objective capacitance due to parameter change and Cbase is the capacitance for the basic structure with w s =s=0.1375 µm, t=0.23375 µm, h=0.20625 µm, wd =0.9625 µm, and D=0.4. Here, s1 and s3 are the minimum spacing and the triple spacing to the minimum spacing, respectively. The lines are the results obtained by the formulas and the marks are the results obtained by the field solver. The accuracy of operation between approximation formulas becomes generally worth than the accuracy of each approximation formula. However, in the sensitivity analysis results shown in Fig. 5, the accuracy and tendency of sensitivity are reasonable. The RMS errors in the 6 Figs. (a)–(f) are within 1.5%. From Fig. 5, we can see that the Cg sensitivities to the signal line width, spacing, height, and density were high, and that the Cc sensitivities to the spacing and metal thickness were high. In other words, Cg was virtually unaffected by the metal thickness and dummy metal width,

(a) Signal line width

(b) Spacing

(c) Metal thickness

(d) Height

(e) Dummy metal width

(f) Density

Fig. 5 Sensitivity analysis results using 3L A1DG B1DG structure. FM and SL stand for formula and solver, respectively.

whereas Cc was virtually unaffected by the signal line width, height, dummy metal width, and density. In the ranges for practical use, the Cg increases approximately directly proportional to density increases, and the dummy metal width hardly effects the interconnect capacitances of Cg and Cc . For the other structures tested (refer to the Appendix for the formulas), we can say that the accuracy of the formulas is high. 3.

Formula-Based Capacitance Extraction Method

We presented formulas in the previous sections to evaluate the effect of dummy fills on signal line capacitances. In this section, by using simpler formulas than Eqs. (1) and (2) with multiple parameters, we present a method to extract interconnect capacitances in VLSI design flow. 3.1 Formulas to Extract VLSI Interconnect Capacitances Some interconnect parameters, such as thickness, t, height, h, and permittivity, ε, are finalized in the step when the process conditions are fixed. Dummy metal width, wd , and density, D, are fixed before the physical design phase. Therefore, for the formulas used in the design flow, many parameters described in the previous section can be reduced. Moreover, the accuracy increases because of the smaller number of parameters required. Figure 6 shows a cross section of interconnects with different parameters. In general, obtaining interconnect capacitances using 2-D analysis is not accurate enough because interconnect structures with dummy fills are not constant along the interconnect length. We used the 3-D field solver to create an interconnect library. As the computational cost for 3-D analysis is expensive, appropriate structural inputs were required. The minimum condition to achieve high accuracy is to use the dummy fill pattern of a cycle until the same cross-section in depth for the required direction appears. Figure 6 shows the illustrations for cross sections of interconnects. Figure 7 shows the errors of the signal line capacitances obtained using the 3-D field solver when the number of dummy layers (#La=0, 1, 2, and 3) above the signal line layer is changed in the structure shown in Fig. 6(a). The number of dummy layers below the signal line layer is 1 (#Lb=1). The basic structures for each signal line error are 3L A1D B1DG in Fig. 7(a) and 1L A1D B1DG in

(a)

(b)

Fig. 6 Cross sections: (a) without top ground plane (3L AmD BnDG), and (b) with top ground plane (3L AmDG BnDG).

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(a) (b) Fig. 7 Effects of dummy fill layers without a top ground plane for structure where w s =1, t=1.5, h=1.5, wd =10, D=45%, and Lb =1: (a) 3L A1D B1DG and (b) 1L A1D B1DG. Table 4 Parameter values, errors, and CPU time required for creating 6 structures (3L A1DG B1DG, 3L A1DG B2DG, 3L A2DG B2DG, 3L A0D B1DG, 3L A0D B2DG, 3L A1D B1DG). Number of divisions in field solver is 2,000,000. Parameter, error type, CPU time w (×wmin ) s (×wmin ) Positive max error (%) Negative max error (%) RMS error (%) CPU time (s)

Condition & value No. 1 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 1, 2, 3

No. 2 1, 3, 5, 7, 10

No. 3 1, 5, 10

1, 2, 3

1, 2, 3

3.0

3.2

4.3

−2.7

−2.8

−3.0

1.4

1.5

1.9

147480

49880

30406

Fig. 7(b). We can see that the capacitances can be approximated using the structure with a neighboring dummy metal layer above the signal line layer. Moreover, the difference between the capacitances for the structures with and without a dummy layer (difference between #La=0 and 1) is large. The capacitance formulas for the structures shown in Fig. 6 can be expressed with two variables, w s and s Cg =γ0 + γ1 w s + γ2 s + γ3 w2s + γ4 w s s + γ5 s2 (6) γ w γ2 s 5 + γ3 w2s + γ4 + 2 (7) Cc =γ0 + γ1 w s + s s s where the units for capacitances are expressed as fF/µm. Table 4 shows the parameter values to create formulas, the formula errors, and CPU times for some structures using the parameters based on an ITRS 90-nm intermediate layer. The structures are 3L A1DG B1DG, 3L A1DG B2DG, 3L A2DG B2DG, 3L A0D B1DG, 3L A0DG B2DG, and 3L A1D B1DG. Each error is the maximum value for the above six structures. CPU time is the total simulation time for the six structure by the field solver [16] on two Redhatlinux-8 with two CPUs of 2.8 GHz and memory of 4 GB. We use wd =0.6875 µm (=wmin ×5), D=31.65%, and a relative permittivity of 3.1. The simulation conditions are that the algorithm uses a finite difference method and the number of divisions is 2,000,000. From the results, we can see that a lot of data for creating formulas are not required. The cost of CPU time is very high. However, the simulation conditions

are not optimal in the number of divisions, window size, and so on. As described in subsection 2.1, if the number of divisions is 1,500,000 and CPU is 3.2 GHz, the CPU time for the data of 729 becomes 242,423 seconds. The runtime estimated by the number of data and the CPU of 3.2 GHz is 30 faster than that of the No.1 condition in Table 4. Moreover, by using a fast simulator, the CPU time can be decreased sharply [6]. Table 5 lists the results for coefficients of (6) and (7) when using No.1 condition in Table 4. The RMS errors were within 1.3% and the maximum errors were within 3.0%. To create an interconnect library for practical use, formulas adapted to more structures are required. For example, there are the structures for one line, two lines, and large spacing between the lines above and below the signal layer. These can be created using a similar method to that described above. In the case of a structure without a top ground plane, the interconnect capacitances can be almost approximated using a neighboring dummy metal layer above a signal layer. By eliminating the structures with negligible capacitances differences, we can reduce the amount of data in the interconnect library. The runtime required to create a library is almost determined by simulation time of the field solver, and after that, the time due to RSM can be negligible because the time for creating a formula using RSM is less than 1 second. We predict that the number of structures for creating a library including one line and two line structures is possible to be several thousands in 8 metal layer process. However, as described above, by optimizing the simulation conditions, multiple CPUs, and/or fast simulator, we are certain that the library can be created within practical time. 3.2 Proposed Method in Design Flow To apply the proposed formula-based method for extracting interconnect capacitances with dummy fills to actual designs, enhancements in the EDA tools used in the design flow process are required. Figure 8 shows the design methodology. As shown in section A of Fig. 8, the procedure is to: 1) obtain interconnect capacitances for various structures using the 3-D field solver, 2) create formulas using RSM, and 3) prepare the interconnect library. We performed these processes once for each process technology to build the design environment. The physical design and verification steps, as shown in Fig. 8 section B, in the procedure is to 1) recognize whether or not the dummy fills exist in the analysis window, and 2) extract the interconnect capacitances using the most appropriate formula. That is, the recognition of dummy fills above and/or below the signal line layer in a parasitic extraction step is needed. If there are no dummy fills present, the extraction method used is the same as the conventional extraction method and the structures correspond to #La=0 and #Lb=0 shown in Fig. 6. The procedures described above assume that dummy fills are inserted during the design phase. However, even when the dummy fills are inserted just before mask fabrica-

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852 Table 5 Coefficients and accuracies for capacitance formulas of various structures when using No.1 condition in Table 4. Cg,sum is the sum of capacitances between ground planes.

Fig. 8

Coefficient & error type γ0 γ1 γ2 γ3 γ4 γ5 Positive max error (%) Negative max error (%) RMS error (%)

3L A1DG B1DG 3L A1DG B2DG 3L A2DG B2DG Cg Cc Cg,sum Cc Cg Cc 5.03E-03 −9.13E-03 1.21E-02 −7.07E-03 6.66E-03 −5.18E-03 4.64E-02 2.12E-02 7.30E-02 2.73E-02 2.65E-02 3.32E-02 5.09E-02 1.40E-02 8.20E-02 1.36E-02 3.28E-02 1.35E-02 2.51E-03 −1.13E-02 4.53E-03 −1.34E-02 2.22E-03 −1.55E-02 4.90E-03 9.25E-04 7.63E-03 1.06E-03 2.79E-03 1.23E-03 −2.38E-02 −4.63E-04 −3.49E-02 −4.46E-04 −1.38E-02 −4.54E-04 0.3 2.7 0.5 2.8 1.7 3.0 −0.7 −2.7 −0.5 −2.4 −0.7 −2.3 0.2 1.4 0.2 1.3 0.4 1.2

Coefficient & error type γ0 γ1 γ2 γ3 γ4 γ5 Positive max error (%) Negative max error (%) RMS error (%)

3L A0D B1DG 3L A0D B2DG 3L A1D B1DG Cg Cc Cg Cc Cg Cc 1.01E-02 −2.91E-03 1.08E-02 4.11E-05 1.34E-02 −2.79E-03 5.12E-02 2.68E-02 3.08E-02 3.25E-02 5.00E-02 3.70E-02 5.79E-02 1.33E-02 3.92E-02 1.29E-02 5.94E-02 1.29E-02 4.99E-04 −1.10E-02 2.96E-04 −1.30E-02 9.69E-05 −1.43E-02 −9.08E-04 9.69E-04 −1.69E-03 1.15E-03 −1.24E-03 1.08E-03 −2.25E-02 −4.01E-04 −1.49E-02 −3.87E-04 −2.52E-02 −3.92E-04 0.5 2.1 2.2 2.3 2.3 2.3 −0.5 −1.8 −0.6 −1.8 −0.7 −1.9 0.2 1.0 0.5 1.0 0.5 1.0

Proposed method in design flow.

tion (after the physical design), we can apply the formulabased method. Based on the design rules and by predicting whether or not dummy fills are inserted, we can select the appropriate formulas to extract capacitances. Although the proposed method uses the 3-D field solver, the high computational cost for very large interconnects can be avoided when using simple formulas in the actual design phase. That is, the dummy fill insertion is not relevant before/after the physical layout, and the proposed formula-based method can extract interconnect capacitances with practical speed and with good accuracy. The proposed method can be applied to other dummy filling such as parallel lines and perpendicular lines with additional spacing [13] by adding a parameter of the additional spacing to formulas. Moreover, we describe briefly the difference between the proposed method and the existing methods. For extracting interconnect capacitances that include dummy fills, methods of full-wave simulation [6], [14], equivalent per-

mittivity [5],[7], and thickness reduction [8] have been reported. We recognize that the method of full-wave simulation is very slow and not practical for VLSI circuits. For that reason, approximation methods such as equivalent permittivity and thickness reduction were developed. To create a library, the method of equivalent permittivity needs almost the same CPU time as the proposed method in this paper. The method of thickness reduction has an advantage of high-speed library creation because of 2-D analysis. The two methods can quickly extract the interconnect capacitances in a design flow. However, the accuracy of the methods is not high. The proposed method can extract the capacitances more accurately. In the design flow, since the proposed method requires the calculation time by using the proposed formulas, we believe that overhead costs due to the runtime to whole runtime are small because general extraction tools without dummy fills are also using structural recognition and the function for capacitance calculation such as [15]. 4.

Conclusion

We have presented a formula-based method to extract interconnect capacitance with dummy fills in a VLSI design flow. We have also presented formulas to evaluate the effect of dummy fills on interconnect capacitances. The following items regarding dummy fills were clarified: 1) when densities and the dummy metal widths are the same, signal line capacitances are virtually unaffected by the spacing between the dummy fills, 2) dummy fills above the signal lines affect the signal line capacitances even if there is no ground

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plane above the signal lines, and 3) when there are multiple dummy fill layers above the signal lines and that there is no top ground plane, the capacitances can be approximated using only a neighboring dummy fill layer above the signal lines. References [1] D.O. Ouma, D.S. Boning, J.E. Chung, W.G. Easter, V. Saxena, S. Misra, and A. Crevasse, “Characterization and modeling of oxide chemical-mechanical polishing using planarization length and pattern density concepts,” IEEE Trans. Semicond. Manuf., vol.15, no.2, pp.232–244, May 2002. [2] C.C. Jeng, W.K. Wan, H.H. Lin, M.-S. Liang, K.H. Tang, I.C. Kao, H.C. Lo, K.S. Chi, T.C. Huang, C.H. Yao, C.C. Lin, M.D. Lei, C.C. Hsia, and M.-S. Liang, “BEOL process integration of 65nm Cu/low k interconnects,” Proc. IITC, pp.199–201, June 2004. [3] S. Lakshminarayanan, P.J. Wright, and J. Pallinti, “Electrical characterization of the copper CMP process and derivation of metal layout rules,” IEEE Trans. Semicond. Manuf., vol.16, no.4, pp.668–676, Nov. 2003. [4] P. Zarkesh-ha, S. Lakshminarayann, K. Doniger, W. Loh, and P. Wright, “Impact of interconnect pattern density information on a 90 nm technology ASIC design flow,” Proc. ISQED, pp.405–409, March 2003. [5] W.-S. Lee, K.-H. Lee, J.-K. Park, T.-K. Kim, Y.-K. Park, and J.-T. Kong, “Investigation of the capacitance deviation due to metal-fills and the effective interconnect geometry modeling,” Proc. ISQED, pp.373–376, March 2003. [6] J.-K. Park, K.-H. Lee, J.-H. Lee, Y.-K. Park, and J.-T. Kong, “An exhaustive method for characterizing the interconnect capacitance considering the floating dummy-fills by employing an efficient field solving algorithm,” Proc. SISPAD, pp.98–101, Sept. 2000. [7] K.-H. Lee, J.-K. Park, Y.-N. Yoon, D.-H. Jung, J.-P. Shin, Y.K. Park, and J.-T. Kong, “Analyzing the effects of floating dummyfills: From feature scale analysis to full-chip RC extraction,” Proc. IEDM, pp.685–688, Dec. 2001. [8] A. Kurokawa, T. Kanamoto, A. Kasebe, Y. Inoue, and H. Masuda, “Efficient capacitance extraction method for interconnects with dummy fills,” Proc. CICC, pp.485–488, Oct. 2004. [9] B.E. Stine, D.S. Boning, J.E. Chung, L. Camilletti, F. Kruppa, E.R. Equi, W. Loh, S. Prasad, M. Muthukrishnan, D. Towery, M. Berman, and A. Kapoor, “The physical and electrical effects of metal-fill patterning practices for oxide chemical-mechanical polishing processes,” IEEE Trans. Electron Devices, vol.45, no.3, pp.665– 679, March 1998. [10] A.B. Kahng, G. Robins, A. Singh, H. Wang, and A. Zelikovsky, “Filling algorithms and analyses for layout density control,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol.18, no.4, pp.445–462, April 1999. [11] Y. Chen, A.B. Kahng, G. Robins, and A. Zelikovsky, “Area fill synthesis for uniform layout density,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol.21, no.10, pp.1132–1147, Oct. 2002. [12] Y. Chen, P. Gupta, and A.B. Kahng, “Performance-impact limited area fill synthesis,” Proc. DAC, pp.22–27, June 2003. [13] A. Kurokawa, T. Kanamoto, T. Ibe, A. Kasebe, C.W. Fong, T. Kage, Y. Inoue, and H. Masuda, “Dummy filling methods for reducing interconnect capacitance and number of fills,” Proc. ISQED, pp.153– 158, March 2005. [14] O. Cueto, F. Charlet, and A. Farcy, “An efficient algorithm for 3D interconnect capacitance extraction considering floating conductors,” Proc. SISPAD, pp.107–110, Sept. 2002. [15] N.D. Arora, K.V. Raol, R. Schumann, and L.M. Richardson, “Modeling and extraction of interconnect capacitances for multilayer VLSI circuits,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol.15, no.1, pp.58–67, Jan. 1996.

[16] Raphael version 2004.06, Synopsys Corporation. [17] International technology roadmap for semiconductors: Semiconductor Industry Association, 2003. [18] G.E.P. Box and N.R. Draper, Empirical model-building and response surfaces, John Wiley & Sons, 1986.

Appendix We describe the formulas to evaluate some structures. The capacitance formula for a signal line is
ws wd t + η3 D + η4 Cg =εeff η0 + η1 + η2 α α α  w 2 α w s wd ws D s + η5 + η11 + η12 2 + η13 h α α α  w 2 ws t ws wd D d + η14 2 + η15 + η22 + η23 h α α α wd t wd Dt Dα 2 + η33 D + η34 + η35 + η24 2 + η25 h α h α  t 2  α 2  t + η45 + η45 . (A· 1) + η44 α h h Tables A· 1 and A· 2 list the coefficients and accuracies for 1L A1D B1DG and 1L A1DG B1DG structures. 1L A1D B1DG is the structure with a dummy layer above a signal line, and with a dummy layer and a ground plane below a signal line. 1L A1DG B1DG is the structure with a dummy layer and a ground plane above a signal line, and with a dummy layer and a ground plane below a signal line. Moreover, Tables A· 3 and A· 4 list the coefficients and accuracies for 3L A1D B1DG structure with a dummy layer above three parallel lines, and with a dummy layer and a Table A· 1 Coefficients of Eq. (A· 1) for 1L A1D B1DG and 1L A1DG B1DG structures. Coef. η0 η1 η2 η3 η4 η5 η11 η12 η13 η14 η15 η22 η23 η24 η25 η33 η34 η35 η44 η45 η55

1L A1D B1DG 1.16E+00 1.08E-01 −1.12E-02 −8.60E-01 1.76E-01 1.38E+00 −1.38E-02 −7.26E-04 2.82E-01 −2.21E-02 4.74E-01 1.61E-03 4.51E-02 −1.17E-02 −5.14E-03 −2.14E+00 4.71E-01 4.47E+00 −1.99E-02 8.06E-02 −1.52E+00

1L A1DG B1DG 7.42E-01 4.63E-02 −6.65E-03 −7.17E-01 1.07E-01 6.31E-01 −6.20E-03 −7.40E-04 2.03E-01 −9.84E-03 3.79E-01 1.10E-03 2.65E-02 −6.81E-03 −9.08E-03 −1.40E+00 3.47E-01 2.72E+00 −8.56E-03 4.65E-02 −7.71E-01

IEICE TRANS. FUNDAMENTALS, VOL.E89–A, NO.4 APRIL 2006

854 Table A· 2 Accuracy of formulas for 1L A1D B1DG and 1L A1DG B1DG structures. Error type Positive max error (%) Negative max error (%) RMS Error (%)

Table A· 3 Coef. β0 β1 β2 β3 β4 β5 β6 β11 β12 β13 β14 β15 β16 β22

1L A1D B1DG 2.4 −3.6 0.8

Akira Kasebe received the B.E. degree in electrical engineering from Nippon Bunri University, Oita, Japan, in 2001. From 2001, he is with Meitec Corporation, where he is engaged in the print circuit board design and the parasitic extraction technology development of VLSI interconnects.

1L A1DG B1DG 2.9 −4.8 0.9

Coefficients of Eqs. (1) and (2) for 3L A1D B1DG structure.

Cg 1.51E-01 6.60E-02 1.51E-01 −2.32E-03 −8.86E-01 −5.94E-02 6.74E-01 −4.92E-03 −8.10E-03 −1.53E-03 1.23E-01 −1.08E-02 3.19E-01 −1.94E-02

Table A· 4

Cc −2.15E-01 2.97E-01 1.23E+00 2.87E-02 2.71E-02 7.34E-02 −1.14E-01 −1.43E-02 5.80E-02 2.03E-03 −1.86E-02 7.18E-03 −2.74E-02 −5.29E-01

Coef. β23 β24 β25 β26 β33 β34 β35 β36 β44 β45 β46 β55 β56 β66

Cg −9.38E-04 9.01E-02 −1.12E-03 2.25E-01 1.08E-03 3.61E-02 −7.61E-03 −9.88E-03 −1.14E+00 3.18E-01 2.84E+00 1.16E-02 −1.13E-01 −8.06E-01

Cc 1.63E-04 1.22E-02 9.84E-01 2.51E-02 −6.88E-04 −3.73E-03 7.90E-05 −2.71E-03 −7.45E-03 3.90E-03 2.94E-02 −6.23E-03 −1.76E-02 3.34E-02

Toshiki Kanamoto was born in Osaka, Japan, in 1965. He received B.S. and M.S. degrees in Physics from Nihon University, Tokyo, Japan, in 1989 and 1991, respectively. In 1991, he joined ASIC Design Engineering Center, Mitsubishi Electric Corporation, Itami, Japan, where he has been engaged in research and development of the physical design and verification technologies. On April of 2003, he was transferred to Renesas Technology Corporation as a member of Design Technology Division in Itami. He is also working towards his Doctor degree at Osaka University. He is a member of the Information Processing Society of Japan.

Yun Yang received the B.S. degree in electronic engineering from Fudan University, Shanghai, China, in 1998 and the M.S. degree in Micro-Electronics Department from Fudan University, Shanghai, China, in 2004. Now he is pursuing the Ph.D. degree at Graduate School of Information, Production and Systems, Waseda University, Kitakyushu, Japan. His research interests include pipeline operation, MPEG chip design, VLSI CAD development and analog/digital circuit design. He is a

Accuracy of formulas for 3L A1D B1DG structure.

Error type Positive max error (%) Negative max error (%) RMS error (%)

Ct 3.1 −2.8 0.8

Cg 6.5 −6.0 1.4

Cc 5.0 −5.0 1.2

ground plane below three parallel lines. student member of IEEE.

Atsushi Kurokawa received the B.E. degree in electrical engineering from Seikei University, Tokyo, Japan, in 1986 and the D.E. degree in Information, Production and Systems Engineering from Waseda University, Fukuoka, Japan, in 2005. From 1986 to 2002, he worked for Sanyo Electric Co., Ltd., Gunma, Japan. He is now with Semiconductor Technology Academic Research Center (STARC). His research interests include high-speed/low-power design techniques and timing analysis for VLSI circuits. Dr. Kurokawa is a member of IPSJ and IEEE.

Zhangcai Huang was born on March 8th, 1978 in Jiangxi province, China. He received the B.E. degree in electrical engineering from East China Jiao Tong University, Nanchang, China, in 2001. He received M.E. degree in electronic engineering from Shanghai Jiao Tong University, Shanghai, China, in 2004. He is now pursuing the Ph.D. degree at Graduate School of Information, Production and Systems, Waseda University, Kitakyushu, Japan. His research interests include Static Timing Analysis, interconnect analysis and analog circuit design. He is a student member of IEEE.

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Yasuaki Inoue was born in Niigata, Japan, on September 6, 1945. He received a diploma from the Department of Electronics, Nagaoka Technical High School, Niigata, Japan, in 1964 and the D.E. degree in electronics and communication engineering from Waseda University, Tokyo, Japan, in 1996. From 1964 to 2000, he was with Sanyo Electric Co., Ltd., Gunma, Japan, where he was engaged in research and development in analog integrated circuits and analog/digital CAD systems. In Sanyo Semiconductor Company, he was General Manager of the CAD Engineering Department from 1993 to 1998 and the Memory Development Department from 1998 to 2000. He holds over forty patents. From 2000 to 2003, he was a Professor with the Department of Integrated Cultures and Humanities, also a Professor with the Graduate School of Integrated Science and Art, University of East Asia, Shimonoseki, Japan. Since 2003, he has been a Professor with the Graduate School of Information, Production and Systems, Waseda University, Kitakyushu, Japan. His research interests include numerical analysis of nonlinear circuits and systems, analog circuits, and LSI CAD systems. He was an Associate Editor of the IEEE Transactions on Circuits and Systems Part II from 1997 to 1999. He received the Ishikawa Award from the Union of Japanese Scientists and Engineers in 1988, the Distinguished Service Award from the Science and Technology Agency, the Japanese Government in 1999, the TELECOM System Technology Award from the Telecommunications Advancement Foundation in 2002, the Achievement Award from the Information Processing Society of Japan (IPSJ) in 2003, and the Funai Information Technology Prize from the Funai Foundation for Information Technology in 2004. Dr. Inoue is a member of IEEE, IPSJ, IEEJ and JSST.

Hiroo Masuda received the B.S. degree in applied physics and Dr. of Engineering in electric system from Tokyo Institute of Technology, Tokyo, in 1970 and 1979, respectively. In 1970, he joined Central Research Laboratory, Hitachi, Ltd., Tokyo, Japan. He initially engaged in research and development of 3-µm MOS device and process. From 1975 he joined MOS memory group and developed a 64K Dynamic Memory. From 1981 to 1982 he was a Visiting Scholar at the University of Michigan, Ann Arbor. From 1982 to 1991, he was with Central Research Laboratory, Hitachi, Ltd., where he worked on semiconductor device simulation and modeling. From 1991 to 2000, he is with Device Development Center, Hitachi Ltd., where he worked on Computer Aided Engineering for VLSI’s, including TCAD (Technology CAD) application methodology and statistical yield modeling and metrology. Since 2000, he is with STARC (Semiconductor Technology Academic Research Center), Development Department-1, Physical Design Group as a Senior Manager, where he is engaged in research and development works on physical design issues for sub-100 nm VLSIs. Dr. Masuda is a senior member of the Institute of Electrical and Electronics Engineers Inc., and a member of the Japan Society of Applied Physics.