High Performance 65 nm SOI Technology with Enhanced Transistor Strain and Advanced-Low-K BEOL W-H. Lee, A.Waite^, H. Nii#, H. M. Nayfeh, V. McGahay, H. Nakayama*, D. Fried, H. Chen, L. Black^, R. Bolam, J. Cheng, D. Chidambarrao, C. Christiansen, M. Cullinan-Scholl, D. R. Davies, A. Domenicucci, P. Fisher^, J. Fitzsimmons, J. Gill, M. Gribelyuk, D. Harmon, J. Holt, K. Ida*, M. Kiene^, J. Kluth^, C. Labelle^, A. Madan, K. Malone, P. V. McLaughlin, M. Minami*, D. Mocuta, R. # * Murphy, C. Muzzy, M. Newport, S. Panda, I. Peidous^, A. Sakamoto*, T. Sato , G. Sudo#, H. VanMeer^, T. Yamashita , H. Zhu, P. # Agnello, G. Bronner G. Freeman, S-F Huang, T. Ivers, S. Luning^, K. Miyamoto , H. Nye, J. Pellerin^, K. Rim, D. Schepis, T. Spooner, X. Chen and M. Khare # IBM Systems and Technology Group, Sony Electronics, Inc*, Toshiba America Electronic Components, Inc , Advanced Micro Devices, Inc^, IBM Semiconductor Research and Development Center (SRDC), Hopewell Junction, NY 12533 Contact: [email protected] M. Horstmann, A. Wei, T. Kammler, J. Höntschel, H. Bierstedt, H.-J. Engelmann, A. Hellmich, K. Hempel, G. Koerner, A. Neu, R. Otterbach, C. Reichel, M.Trentsch, P.Press, K. Frohberg, M. Schaller, H. Salz, J. Hohage, H. Ruelke, J. Klais, M. Raab, D. Greenlaw and N. Kepler Advanced Micro Devices, AMD Saxony LLC & Co. KG, Wilschdorfer Landstrasse 101, 01109 Dresden, Germany

I. Abstract A high performance 65 nm SOI CMOS technology is presented. Dual stress liner (DSL), embedded SiGe, and stress memorization techniques are utilized to enhance transistor speed. Advanced-low-K BEOL for this technology features 10 wiring levels with a novel K=2.75 film in selected levels. This film is a SiCOH-based dielectric optimized for stress to enable integration for enhanced performance. The resulting technology delivers pFET and nFET AC switching on-current of 735 µA/um and 1259 µA/um respectively, at an off-current of 200 nA/um (Vdd=1.0 V), and 6% reduction in interconnect delay. Process yield is demonstrated on a SRAM cell with 2 size of 0.65 µm .

The remaining process flow steps are equivalent to our baseline CMOS process, except for a modified Ni silicide process that achieves improved contact and stability on SiGe. This is followed by DSL implementation in the middle-of-line (MOL) [2]. A cross-sectional TEM image of a completed device is shown in Fig. 2, also shown is an AFM image of the surface morphology of the source/drain area of the pFET demonstrating a smooth RMS roughness value of 0.11 nm. The advanced-low-K dielectric film used in the BEOL interconnect levels is based on the K=2.75 material previously discussed [3]. This film has been optimized for lower permittivity (K=2.75) and stress. Extendibility of the film into both 2x and 4x fatwire levels has been demonstrated.

II. Technology Description

III. FEOL Performance Results

The major ground rules used in this technology are equivalent to our 65-nm-baseline technology which utilizes DSL for enhanced performance [1]. DSL is a process integration flow that combines tensile and compressive stress silicon nitride liners on nFET and pFET devices respectively, resulting in increased channel strain and performance for both. Fig. 1 shows our baseline flow with additional enhanced strain process steps. Specifically, the embedded SiGe process is implemented with epitaxial SiGe growth in cavities etched into the source/drain areas of the pFETs. The nFETs are covered with a nitride hardmask during recess etch and epitaxial growth of SiGe in the pFET areas. Photolithography is utilized to mask the nFET areas while the hardmask is etched into a spacer in the pFET areas. This spacer defines the proximity of the SiGe to the channel area and prevents SiGe growth on the pFET polysilicon gate electrode. A stress memorization technique (SMT) is implemented for the nFETs where increased tensile strain was achieved by the deposition of a stress dielectric film and subsequent thermal anneal.

A plot of the Ion-Ioff characteristics is shown in Fig. 3 along with the transistor characteristics in Fig. 4 at 1.0 V Vdd, where the threshold voltage roll-off is well-behaved down to 30 nm gate length, and sub-threshold swing is maintained at ~110 mV/dec (Fig. 5-6). pFET AC switching on-current of 735 µA/µm at off-current of 200 nA/µm with a corresponding DC on-current of 700 µA/µm was achieved. For the nFET, the AC switching on-current was 1259 µA/µm and the DC on-current was 1137 µA/µm at the same off-current. The excellent short-channel effect (SCE) control was achieved by using strong-halo-channel doping, shallow junctions and optimization of the diode leakage currents. The eSiGe pFET source and drain to body junctions where designed to ensure equivalence in terms of floating body effects with the baseline. The dRtotal/dL method, a technique that minimizes the effect of uncertainties in Lpoly (gate length) and Rext (series resistance) on the measured mobility for deeply-scaled devices [4], shows that the increased pFET on-current is due to enhanced hole carrier mobility and lower series resistance.

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This technique also demonstrates that the SMT process flow results in increased electron mobility for the nFET devices compared to the baseline. The nFET devices have an on-current versus overlap capacitance relationship which differs from the baseline. In particular, the oncurrent plateaus at higher overlap capacitance as shown in Fig. 7. As a result, optimized halo channel doping was utilized to maximize the device performance gains using SMT, and to ensure adequate process window with overlap capacitance. AC performance, shown in Fig. 8, demonstrates 14% ring-oscillator improvement compared to baseline-65-nm-technology. IV. BEOL (Interconnects) The hierarchical BEOL architecture consists of ten levels of Cu interconnect with dual damascene integration using the 65-nm-baseline SiCOH film (K=3.0), an advanced SiCOH film (K=2.75), and F-doped TEOS (K=3.6) interlayer dielectric (ILD) in targeted levels. The baseline film is used in the thinwire levels (M1/M2/M3/M4), advanced SiCOH film in the 2x (M5/M6) and 4x (M7/M8) fatwire levels, and F-doped TEOS in the 8x fatwire levels (M9/M10). Although advanced low-K dielectrics are often proposed for thinwire interconnects, there is a substantial benefit in placing these films in 2x and 4x fatwire levels containing relatively long across-chip connections, in contrast to thinwire levels which typically consist of short runs. The tensile stress characteristic of SiCOH-based films tends to limit their usable thickness due to cracking concerns. The mechanical properties of the advanced SiCOH film have been accordingly optimized to enable use in intermediate fatwire levels. Process deviations from the 65-nm baseline are minimal. The advanced SiCOH film is deposited in the same toolset as the 65-nm-baseline (K=3) SiCOH film using identical precursors but modified deposition parameters. Wet clean, metallization, and CMP processes are identical to those used in the 65-nm baseline. Reactive ion etch is optimized for the K=2.75 film’s composition, which has a higher carbon content compared to the 65-nm-baseline film. The modeled capacitance trend in migrating from K=3.6 (F-doped TEOS) to K=3.0 (65-nm-baseline) and K=2.75 for a representative 2x fatwire level is shown in Fig. 9, demonstrating an additional 6% reduction in capacitance over the K=3 film. Fig. 10 shows measured capacitance vs. resistance for the K=2.75 and K=3.0 films, demonstrating reduced RC parasitics. Fig. 11 compares 1 million via chain yield between these films, demonstrating equivalent yield to our baseline technology. Fig. 12 shows an example BEOL stack cross-section for 10 wiring levels, with advanced Low-K dielectric used in wiring levels M5 through M8.

V. Reliability (FEOL & BEOL) and SRAM Yield Fig.13 shows pFET and nFET ultra-thin gate oxide (1.05 nm) time-dependent dielectric breakdown (TDDB) measurements, demonstrating equivalence to baseline-65nm-technology. Furthermore, negative-bias-temperature instability (NBTI) results for pFET device are also comparable to the baseline for this technology, as shown in Fig. 14. Fig. 15 shows an example of electromigration reliability for the advanced-low-K film versus a K=3 reference film showing comparable results. Fig. 16 shows BEOL TDDB for three different wet clean strengths. The trend indicates that TDDB failure is intrinsic, i.e. determined by spacing and not by defects. Fig. 17 shows the stability of the integrated advanced-low-K structure against thermal cycle. SRAM performance is enhanced using metal 1 bit-line and advanced-low-K dielectric due to reduced interconnect parasitics. Fig. 18 shows a 2 0.65µm SRAM cell top-down SEM view after spacer formation and SRAM yield comparison between 65-nm SOI baseline and the technology described in this paper, at various testing voltages. As shown in Fig. 19, overall yield and voltage sensitivity of this technology is comparable to our 65-nm SOI baseline. VI. Conclusions An industry leading 65 nm CMOS technology using enhanced strain for pFET and nFET transistors and advanced-low-K BEOL for overall microprocessor speed improvement is presented. FEOL and BEOL reliability and SRAM yield is shown to be comparable to our baseline65-nm-technology. VII. Acknowledgments The authors would like to acknowledge the support of the E. Fishkill 300mm Fabrication facility and staff, and managerial support from S. Crowder, P. Gilbert and L. Su. References [1] E. Leobandung et al. VLSI 2004 p. 126 [2] H. S. Yang et al. IEDM 2004, p. 1075 [3] M. Fukasawa et al., IITC 2005 [4] K. Rim et al. IEDM 2002 p. 43-46

Process flow description

• Isolation • Well Formation • Gate Stack Etch • Gate Reoxidation

nFET

pFET

⇒Si Recess Etch in PFET ⇒ Selective eSiGe Growth

• Halo and extension implantation • Spacer Formation • Source/drain implantation ⇒SMT

• RTA • Ni Silicide • DSL MOL

(a) NFET

⇒Advanced Low-K BEOL

Fig.1. Enhanced strain process flow with changes from our baseline-65-nm for the technology described in this paper

Fig.

pFET DC Ion=700 µΑ/µm AC Ion= 735 µΑ/µm

Fig. 2. X-TEM and AFM of nFET and pFET devices

(b) X-TEM of pFET and AFM of SiGe epitaxial layer

nFET DC Ion=1137 µΑ/µm AC Ion= 1259 µΑ/µm

Vdd=1 V

pFET

nFET

Fig. 3. pMOS and nMOS Ion/Ioff characteristics, Fig. 4. Transistor drain current versus drain dashed lines correspond to AC switching Ion voltage for multiple gate voltages (0.1 V step) measured with pulsed IV

Fig. 5. Sub-threshold characteristics

nFET

50 mV

SMT

1V

No SMT

This work (enhanced strain)

Baseline

-1 V

pFET

~14% improvement

-50 mV

Fig. 6. Threshold Voltage versus gate length demonstrating excellent SCE down to 30 nm

Fig. 7. Enhancement of drain current versus overlap-capacitance using SMT

Fig.8. Ring Oscillator delay vs. leakage current demonstrating ~14% delay improvement

0.6 0.6 0.4 0.4 0.2 0.2

00 K=3.6 K=3.6

K=3.0 K=3.0

K=2.75 K=2.75

Bulk Dielectric Dielectric Constant Constant Bulk

K=3.0

K=2.75

K=2.75 K=2.75 K=2.8

Wafer

M5 Resistance (relative units)

Fig. 10. BEOL M5 (2X fatwire) capacitance vs. Fig. 11. Via chain yield for advanced-low-K film resistance demonstrating reduced RC parasitic demonstrating equivalence with our baseline for this technology

Fig. 12. SEM of ten-level build with advanced low-K (K=2.75) in levels M5 thru M8

Cumulative Distribution (%)

Fig. 13. TDDB for pFET and nFET ultra-thin gate oxides (1.05 nm). solid line corresponds to historical trend

Fig. 14. Accelerated pFET NBTI comparing to baseline

Lot #

Fails at 1000 Thermal Cycles

1

0%

2

0%

3

0%

Fig. 17. Stability of the integrated advanced-low-K structure against thermal cycle

Electromigration: M8→ V7 →M7 e-flow K=2.8 (A, B) K=2.75 (A,B) K=3.0 (C) K=3.0 (C)

Weibull Scale

Fig.9. Modeled M5 (2x fatwire) capacitance trend vs. bulk dielectric constant showing ~6% reduction for this technology

K=3

Time to Fail (hrs)

Fig. 15. BEOL electromigration reliability

Fig. 18. Top-down SEM of a 0.65 2 µm SRAM cell

M5 TDDB (100V, 150C) Wet clean split A: More aggressive B: Standard C: Less aggressive

Cumulative Failure

-24%

1M Chain Yield (relative units)

-18%

0.8 0.8

M5 Capacitance (relative units)

Capacitance Capacitance(relative (relativeunits) units)

1.2 1.2

1.01

Time to Failure (s)

Fig. 16. BEOL TDDB for various wet cleans

Fig. 19. SRAM yield for this technology compared to baseline