IEEE 1500 compliant Self-Test design library Davide Appello ST Microelectronics, Agrate Brianza (MI) – ITALY Paolo Bernardi, Michelangelo Grosso, Ernesto Sanchez, Matteo Sonza Reorda Dipartimento di Automatica e Informatica, Politecnico di Torino, Torino – ITALY Jorge Lagos-Benites Pontificia Universidad Católica del Perú, Lima – PERU We propose for presentation and open-source release the description of a set of self-test circuitries for various core types and an IEEE 1500 compliant wrappers structure able to easily control such self-test features. In particular, we will provide the VHDL code of: o a Programmable BIST for memory testing o an Infrastructure-IP for supporting the SBST of processors o a fully programmable Logic BIST for combinational and sequential circuits The Programmable BIST architecture, detailed in [1], permits the application of word-oriented tests for memory (usually March) by loading a small internal SRAM code memory. A control unit fetches and decodes the instruction loaded in the code memory during the initialization phase and a memory adapter module applies test vectors to the DUT. The architecture is explained in Fig. 1. External RAM
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Fig. 1: Conceptual view of the adopted test structure for a memory core.
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Fig. 2: Conceptual view of the adopted test structure for a processor core.
The Infrastructure-IP for supporting the SBST of processors is able to activate functional test procedures by making use of the processor functionalities (test program upload, test program launch and result collection). The architecture detailed in [2] is shown in Fig. 2. The programmable Logic BIST architecture allows applying a user-definable number of pseudorandom patterns according with a selected seed. Exploiting the parameters of programmability of this architecture, it is possible to achieve a high fault classification ability as shown in [3]. All the introduced structures integrate self-test oriented IEEE 1500 compliant wrappers able to manage multiple test frequencies; in all the presented test architectures, a common data
communication protocol simplifies their insertion and adoption in industrial frameworks. The STIL test program for cores including Self-test facilities and surrounded by such a kind of IEEE 1500 wrapper can be generated automatically, without simulation, by STAT [4] (this tool is already open-source and has been presented during the 2006 IOST3 edition. Its structure is shown in fig.4). WCLK (low ATE frequency)
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Fig 3. The IEEE 1500 wrapper schema.
Fig 4. STAT software architecture.
The design package is available at the following URL:
http://www.cad.polito.it/tools and includes the following files: o the Programmable BIST version for a generic 64kx8 SRAM core o the Infrastructure-IP version for the open-source microcontroller mc8051 o the programmable Logic BIST version for the C6288 parallel multiplier included in the ITC 99 benchmarks o the description of a sample SoC including those three components o a set of scripts for simulation, synthesis and FPGA prototyping o a set of test programs including IIP ready functional programs for processor and Programmable BIST ready March tests descriptions.
References [1] D. Appello, P. Bernardi, A. Fudoli, M. Rebaudengo, M. Sonza Reorda, V. Tancorre, M. Violante, “Exploiting Programmable BIST For the Diagnosis of Embedded Memory Cores”, IEEE International Test Conference, 2003, pp. 379-385 [2] P. Bernardi, M. Rebaudengo, M. Sonza Reorda, ”Using Infrastructure IPs to support SW-based SelfTest of Processor Cores”, IEEE International Workshop on Microprocessor Test and Verification, 2004 [3] P. Bernardi, C. Masera, F. Quaglio, M. Sonza Reorda, “Testing logic cores using a BIST P1500 compliant approach: a case of study”, IEEE Design Automation and Test in Europe Conference, 2005 [4] D. Appello, P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda, V. Tancorre,”On the Automation of the Test Flow of Complex SoCs”, IEEE VLSI Test Symposium, May 2006, Page(s): 166-171
