IEEE Transactions on Electron Devices 58 (11), 3890 (2011) A Combined Interface and Border Trap Model for High Mobility Substrate Metal-Oxide-Semiconductor Devices Applied to In0.53Ga0.47As and InP Capacitors G. Brammertz1, A. Alian1, H.-C. Lin1, M. Meuris1, M. Caymax1 and W.-E Wang1 1

imec, Kapeldreef 75, B-3001 Leuven, Belgium

Abstract: By taking into account simultaneously the effects of border traps and interface states, the authors model the alternative current (AC) capacitance-voltage (CV) behavior of high mobility substrate Metal-Oxide-Semiconductor (MOS) capacitors. The results are validated with the experimental In0.53Ga0.47As/hi-κ and InP/hi-κ CVcurves. The simulated C-V and conductance-voltage (G-V) curves reproduce comprehensively the experimentally measured capacitance and conductance data as a function of bias voltage and measurement frequency, over the full bias range going from accumulation to inversion and full frequency spectra from 100 Hz to 1 MHz. The interface state densities of In0.53Ga0.47As and InP MOS devices with various high-k dielectrics, together with the corresponding border trap density inside the high-k oxide, were derived accordingly. The derived interface state densities are consistent to those previously obtained with other measurement methods. The border traps, distributed over the thickness of the high-k oxide, show a large peak density above the two semiconductor conduction band minima. The total density of border traps extracted is of the order of 1019 cm-3. Interface and border trap distributions for InP and In0.53Ga0.47As interfaces with high-k oxides show remarkable similarities on an energy scale relative to the vacuum reference. I. INTRODUCTION Recent advances in the fabrication of high mobility MOSFET devices1-6 have led to an increased interest in Ge and III-V devices for the application as high performance transistors for CMOS generations beyond the 16 nm node7. One of the numerous challenges being investigated is the reduction of defects at the III-V oxide interface. In particular, one of the disturbing features of III-V substrate CV-measurements is the so-called “frequency dispersion in accumulation”. This issue was already addressed thirty years ago by Hasegawa et al. on GaAs and InP substrates8, who tried to model the frequency dispersion in accumulation with tunneling of electrons into the oxide. More recently, this model was further applied to explain the frequency dispersion in accumulation of GaAs samples with atomic layer deposited oxides9. Kim et al.10 attributed the frequency dispersion in accumulation in In0.53Ga0.47As samples to border traps inside the oxide and they were able to modulate them with H-anneals. Following this report, Yuan et al.11 presented a model that quantized the border trap density by analyzing the frequency dispersion at specific bias voltages in accumulation, which yielded a border trap density of 4.5x1019 eV-1cm-3. In this contribution, we combine the model of Yuan et al. with the interface state model by Martens et al.12 to simulate simultaneously the effects of border traps and interface states on the measured C-V and G-V data. This admittance model is then fitted to experimental measurements from InP and In0.53Ga0.47As MOS capacitors to deconvolute and extract the corresponding interface state density distribution and border trap density of the III-V MOS stack. 1

Fig 1. Admittance model that takes into account the effect of both border and interface traps on the admittance of n-MOS capacitors. For p-MOS capacitors the branches Gn and Gp should be interchanged. II. EXPERIMENT The two In0.53Ga0.47As devices used in this work consist of 5x1016 cm-3 n- and p-type doped In0.53Ga0.47As layers grown lattice matched on respectively 2x1017 cm-3 n- and p-type doped InP substrates by metal-organic chemical vapor deposition (MOCVD). The two InP devices used in this work consist of 2x1017 cm-3 n- and p-type doped InP substrates. The top surface of all four substrates was cleaned with (NH4)2S before 300°C ALD deposition of a 9 nm thick Al2O3 dielectric film using as precursors trimethylaluminum (TMA) and H2O. On top of the dielectric, 50 nm thick Pt metal dots were deposited through a shadow mask. The full stack was then annealed in forming gas at 400°C during 5 minutes. AC-CV curves were acquired using an Agilent 4280A LCR-meter with frequencies varying from 100 Hz to 1 MHz. III. MODEL We use an admittance model that takes into account both the effects of border and interface traps. We therefore replace the substrate capacitance in the model of Yuan et al.10 by a more sophisticated model including the effect of interface states12. The resulting admittance model is shown in Fig. 1. The different elements in the shown admittance model can be calculated using the following procedure. The substrate capacitance Cs and inversion capacitance Cinv can be calculated by solving the Poisson equation 13: q (N d − N a + p − n ) d 2V . (1) =− 2 εs dx Here, q is the electron charge, Nd and Na are the donor and acceptor concentrations in the semiconductor, n and p are the electron and hole density respectively and εs is the dielectric constant of the semiconductor. It should be noted that, as the density of states in the III-V conduction band is low, the Fermi level can be allowed to travel quite far into the conduction band. It is therefore important to use the exact electron density for degenerate semiconductors and not the exponential Boltzmann approximation only valid inside the semiconductor bandgap. Also a correction for the non-parabolicity of the conduction band needs to be applied14: 2

n=

2NC

π

∫

∞

0

ε 1 / 2 (1 + αε )1 / 2 (1 + 2αε )dε , 1 + exp(ε − φ )

(2)

where Φ=(EF-EC)/kT is the reduced Fermi energy, EC is the conduction band edge energy, EF is the Fermi energy, NC is the effective density of states in the conduction band, k is the Boltzmann constant, T is the temperature and α is the nonparabolicity factor given by: 2

1  m  (3) α = 1 − e  . ε g  m0  Here, me is the electron effective mass, m0 is the free electron mass and εg = (EC-EV)/kT is the normalized bandgap energy, with EV being the valence band edge energy. From the solution of the Poisson equation, which can either be performed semi-analytically as in Ref. 15, or fully numerically for complex heterojunction structures as in Ref. 16, we can derive the semiconductor majority carrier charge Qmaj and the minority carrier charge Qmin as a function of the surface potential Φs. The semiconductor capacitance Cs and inversion capacitance Cinv can then be written as: dQmaj (Φ s ) C s (Φ s ) = − (4) dΦ s and dQ (Φ ) Cinv (Φ s ) = − min s (5) dΦ s The interface state capacitance is given by: +∞ Φs q ⋅ d  ∫ Dit , D dE − ∫ Dit , A dE  −∞  Φs  . Cit (Φ s ) = (6) dΦ s Here, Dit,D is the donor like interface state density and Dit,A is the acceptor-like interface state density. The electron and hole interface state conductance Gn and Gp are related to the interface state capacitance Cit through the interface state time constant τit: C (Φ ) C (Φ ) G n (Φ s ) = it s and G p (Φ s ) = it s , (7) τ it ,n (Φ s ) τ it , p (Φ s ) where τit,n and τit,p are given by17,18: 1 1  Φ − EC   E − Φs  exp s exp V τ it ,n (Φ s ) =  and τ it , p (Φ s ) =  . (8) σvt N C σvt N V  kT   kT  Here, σ is the capture cross section, vt is the thermal velocity and NV is the effective density of states in the valence band. The minority carrier generation-recombination conductance Ggr depends on several factors, such as the amount of defects in the bulk of the material and at the different interfaces and cannot easily and accurately be calculated from material properties. It can nevertheless easily be derived from the inversion response of the experimental CV-curves and will therefore be treated as a fitting parameter that is independent of the surface potential. In the model, the dielectric layer of thickness tox is divided into n subsections of thickness ∆x=tox/n. From the substrate, electrons can tunnel into the different subsections. The additional capacitance arising from electrons tunneling from the substrate into the defect states at the position x can be expressed as11: (9) C bt ( x, Φ s ) = q 2 N bt ( x, Φ s ) ∆x .

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The border trap conductance Gbt is related to the border trap capacitance Cbt through the time constant τbt of electron tunneling into the border trap state at the position x19: C ( x, Φ s ) Gbt ( x, Φ s ) = bt , with (10) τ bt ( x, Φ s ) 1 (11) τ bt ( x, Φ s ) = exp(2κx ) , with κ (Φ s ) = 2me ECox − Φ s h . σvt N C

(

)

Here, E Cox is the conduction band edge energy of the oxide. With these input parameters the total admittance of the structure can then be numerically calculated as a function of the surface potential and the AC frequency. Finally, the relationship between gate voltage VG and surface potential Φs is given by: Q (Φ ) Q (Φ ) VG = Φ s + φ m − φ s − s s − it s − Φ bt (Φ s ) , (12) C ox C ox where φ m and φ s are the metal and semiconductor work functions respectively, Qit(Φs) is the interface state charge at the semiconductor surface at the surface potential Φs: +∞

Φs

Φs

−∞

Qit (Φ s ) = ∫ qDit , D dE − ∫ qDit , A dE .

(13)

And Φbt is the potential drop over the border trap charge: tox Φs (t − x )  + ∞ Φ bt (Φ s ) = ∑ ox  ∫Φ qN bt , D dE − ∫−∞ qN bt , A dE  .  ε ox  s x =0

(14)

Table 1: Values of material parameters used in the simulations. In0.53Ga0.47As InP

Na cm-3 5 1016 2 1017

Nd cm-3 5 1016 2 1017

Nc cm-3 2.1 1017 5.7 1017

Nv cm-3 7.7 1018 1.1 1019

me / 0.04 0.08

mh / 0.45 0.58

Eg eV 0.74 1.34

εs / 12 12.5

In0.53Ga0.47As InP

σ cm2 10-15 10-15

vt,e cm/sec 5.5 107 3.9 107

vt,h cm/sec 2 107 1.7 107

φs eV 4.5 4.38

tox nm 9 9

Ec,ox eV 2.7 2.7

εox / 8 8

φm eV 4.9 4.9

IV. DISCUSSION We will now compare the experimental CV-data to the simulation results. For the simulation, values of the material parameters used in equations (1)-(14) are summarized in table 1. All parameter values were taken from Ref. 20. In addition to these material parameters that are quite accurately known for the materials under study, In0.53Ga0.47As and InP, three fitting parameters have been varied in order to fit the simulation results to the experimental data. These three fitting parameters are the generation-recombination conductance Ggr in Siemens, the interface state density Dit as a function of energy in states/eVcm2 and finally the border trap density as a function of energy and position in the oxide in states/eVcm3. The electron and hole capture cross sections were arbitrarily chosen as being equal to 10-15 cm-2. The real capture cross section can strongly differ from this value, which introduces an error in the energy positioning of the interface states and in the

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Fig 2. n-type In0.53Ga0.47As capacitor: Top figures: capacitance as a function of bias voltage for nine different frequencies (100 Hz, 300 Hz, 1 kHz, 3 kHz, 10 kHz, 30 kHz, 100 kHz, 300 kHz and 1 MHz. Dark blue: 1 MHz, light blue: 100 Hz). Bottom figures: the conductance normalized versus area and frequency G/Aωq as a two dimensional contour map, plotted as a function of bias voltage and measurement frequency. The experimental data is shown on the two left hand side figures, whereas the simulation results are shown on the two figures on the right hand side.

spatial positioning of the border traps. For every order of magnitude that the real capture cross section would differ from this value of 10-15 cm-2, the real interface state energy position with respect to the values shown on our figures would shift by 60 meV, whereas the position of the border trap would shift by 2κln10, where κ was defined by equation (11). Figures 2 and 3 show the capacitance as a function of bias voltage for nine different frequencies (100 Hz, 300 Hz, 1 kHz, 3 kHz, 10 kHz, 30 kHz, 100 kHz, 300 kHz and 1 MHz) and the normalized total conductance G/Aωq as a two dimensional contour map, plotted as a function of bias voltage and measurement frequency. Two figures are shown, one for nIn0.53Ga0.47As (Fig. 2) and one for p-In0.53Ga0.47As (Fig. 3). Whereas the experimental data is shown on the left hand side of the figures, the simulation results are shown on the right hand side. Good agreement between the model and the simulation can be observed. Nevertheless, one main discrepancy between the experiment and the model is the existence of band bending fluctuations due to the interface charge21. When the charge due to interface and border traps at the interface is large, the surface potential naturally fluctuates stronger than when there is little charge at the interface. As a consequence the capacitance and conductance response are heavily smeared out over the voltage range, but only in regions where the interface charge is large. This effect is not included in the model and therefore the 5

Fig 3. p-type In0.53Ga0.47As capacitor: Top figures: capacitance as a function of bias voltage for nine different frequencies (100 Hz, 300 Hz, 1 kHz, 3 kHz, 10 kHz, 30 kHz, 100 kHz, 300 kHz and 1 MHz. Dark blue: 1 MHz, light blue: 100 Hz). Bottom figures: the conductance normalized versus area and frequency G/Aωq as a two dimensional contour map, plotted as a function of bias voltage and measurement frequency. The experimental data is shown on the two left hand side figures, whereas the simulation results are shown on the two figures on the right hand side. interface state peaks in the simulated capacitance and conductance are generally much narrower as compared to the experimental data, which shows much broader capacitance and conductance peaks. The overall trends of the experimental data can nevertheless be replicated with the simulation. Different regions in the CV and GV, where inversion, border traps or interface states are dominant, can now be determined. For the n-type In0.53Ga0.47As capacitor, the positive bias voltage region, accumulation, is dominated by the effect of border traps. At around zero bias, at mid-gap, the border trap response weakens and the interface state response now increases, taking over the dominant part. As the surface potential goes into the lower half of the bandgap, minority carriers start to interact with interface states and strong weak inversion peaks emerge in the CV and GV (-0.7 V < Vg < 0.3 V). At bias voltages smaller than -0.7 V, the capacitance and conductance are completely dominated by the minority carrier generation-recombination response. In the ptype In0.53G0.47As capacitor data of figure 3, only two dominant regions can be discerned. At negative bias voltages, in accumulation, the capacitance and conductance response is completely dominated by a very large interface state response, which leads to a very strong apparent frequency dependent flatband voltage shift. The measured capacitance and conductance is entirely due to majority carriers interacting with interface states, real 6

Fig 4. Input parameters for the simulation of the n- and p-type In0.53Ga0.47As samples: Interface state density as a function of energy (a). Border trap density as a function of position in the oxide and energy (b). accumulation is not observed. There is Fermi level pinning before the surface potential reaches the valence band edge energy. At positive voltages, in inversion, the capacitance and conductance are dominated by the minority carrier generation-recombination. In the p-type In0.53Ga0.47As figures, one additional strong discrepancy between the experimental data and the simulation can be seen. The accumulation capacitance in the simulation case converges to the oxide capacitance value, whereas this is not the case for the experimental data. More investigations are necessary to identify the reason for this discrepancy in the negative bias region of the p-type In0.53Ga0.47As capacitor. Figure 4 shows the input parameters of the model in the case of the n- and p-type In0.53Ga0.47As capacitors, namely the interface state distribution Dit as a function of energy and the border trap density Nbt as a function of energy and position in the oxide. The interface state density is the same as the one derived previously with the conductance method4. A large density of donor-like defects is present mainly in the lower half of the bandgap, whereas the upper half of the bandgap shows relatively low interface state density. Inside the conduction band, acceptor-like interface states are present. The latter are in resonance with the conduction band, and can therefore exchange charge very rapidly with the conduction band, such that it is not completely clear yet whether these states are beneficial to the conduction of electrons in transistors, as they artificially increase the electron density close to the interface, or whether they are detrimental to the conduction of electrons in transistors, as they might also increase the amount of carrier scattering at the interface. Transistor data1-5 has shown relatively high effective mobility of electrons in In0.53Ga0.47As MOS transistors, despite high density of interface states inside the conduction band, such that the degrading effects of these interface states are probably small. The border 7

Fig 5. n-type InP capacitor: Top figures: capacitance as a function of bias voltage for nine different frequencies (100 Hz, 300 Hz, 1 kHz, 3 kHz, 10 kHz, 30 kHz, 100 kHz, 300 kHz and 1 MHz. Dark blue: 1 MHz, light blue: 100 Hz). Bottom figures: the conductance normalized versus area and frequency G/Aωq as a two dimensional contour map, plotted as a function of bias voltage and measurement frequency. The experimental data is shown on the two left hand side figures, whereas the simulation results are shown on the two figures on the right hand side. trap distribution that was used for both the n- and p-type In0.53Ga0.47As capacitor simulations shows a large density of traps inside the conduction band of In0.53Ga0.47As. The peak maximum is positioned approximately 0.4 eV above the conduction band edge energy and the full width at half maximum of the border trap peak is about 0.2 eV wide. In the spatial region the peak decreases from the interface with the semiconductor towards the bulk of the oxide, but the decrease is only slow. In addition to these two distributions, the input value for the minority carrier generation-recombination conductance was chosen to be 5 mS for the n-type sample and 20 mS for the p-type sample, in order to fit the experimentally measured minority carrier generation-recombination rates. Figures 5 and 6 show the experimental and simulated capacitance and conductance of the two InP samples. Figure 5 shows the capacitance and conductance of the n-type InP capacitor, whereas figure 6 shows the data for the p-type InP capacitor. Again, good agreement between the model and the simulation can be observed. Also the same discrepancy between the experiment and the model shows up, which is due to the existence of band bending fluctuations in the experimental data because of fluctuations of the surface potential due to large interface charge. The interface charge due to large densities of interface and border traps naturally smears out the experimentally measured capacitance and conductance peaks, but this smear out cannot be simulated with the current model. 8

Fig 6. p-type InP capacitor: Top figures: capacitance as a function of bias voltage for nine different frequencies (100 Hz, 300 Hz, 1 kHz, 3 kHz, 10 kHz, 30 kHz, 100 kHz, 300 kHz and 1 MHz. Dark blue: 1 MHz, light blue: 100 Hz). Bottom figures: the conductance normalized versus area and frequency G/Aωq as a two dimensional contour map, plotted as a function of bias voltage and measurement frequency. The experimental data is shown on the two left hand side figures, whereas the simulation results are shown on the two figures on the right hand side.

The frequency dispersion in the positive bias voltage region of the n-type InP sample is completely dominated by a large border trap contribution, which also leads to a large plateau of conductance in accumulation, relatively independent of bias voltage and frequency, similarly to what is measured experimentally. In the negative bias voltage region, the CV and GV curves are dominated by a large interface state contribution that only arises from the interaction of majority carriers with interface states. Minority carriers can be neglected for the InP capacitors at room temperature, as the minority carrier generation recombination rate is much smaller than the frequencies used here (Ggr = 0 S). In the case of the p-type InP sample, the full CV and GV curves are dominated by interface states. In fact, the Fermi level pins well before the surface potential can reach the valence band edge energy, resulting in pretty much flat CV-curves and extremely large frequency dispersion in accumulation. This Fermi level pinning arises from a very large interface state density in the lower half of the InP bandgap, as shown in figure 7. Figure 7 shows the input parameters of the model, namely the interface state density and the border trap density. The interface state distribution shows very high density in the lower half of the bandgap and relatively low density close to the conduction band. Such a distribution is similar to the one already measured with the conductance method on similar capacitors22. The border trap distribution 9

Fig 7. Input parameters for the simulation of the n- and p-type InP samples: Interface state density as a function of energy (a). Border trap density as a function of position in the oxide and energy (b).

Fig 8. Input parameters for the simulation of both In0.53Ga0.47As and InP samples on an absolute energy scale with reference to the vacuum energy: Interface state density as a function of energy (a). Border trap density at the semiconductor oxide interface as a function of energy (b).

shows a large peak of border traps about 0.2 eV above the conduction band edge energy of the InP. The maximum border trap density, located at the interface with the semiconductor, is larger by a factor 7 as compared to the In0.53Ga0.47As case, but otherwise shows very similar characteristics. This is visualized in figure 8, which shows the interface state density and border trap density for both the In0.53Ga0.47As and InP samples on an absolute energy scale, relative to the vacuum energy. It can be seen that the interface state density for In0.53Ga0.47As and InP show significantly high similarities, pointing in the direction of physically very similar defects possibly being responsible for this contribution. Also, on an absolute energy scale the border traps show the same type of distribution for both InP and In0.53Ga0.47As.

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V. CONCLUSIONS We have presented a comprehensive model for the admittance of high-mobility semiconductor MOS capacitors, which takes into account both the effects of interface states and border traps. The model was compared to experimental CV and GV data for frequencies varying from 100 Hz to 1 MHz and as a function of bias voltage ranging from inversion to accumulation. Good agreement between experimental data and simulation could be observed by only varying the interface and border trap density, all other parameters being fixed. The main discrepancy between model and experiment is the existence of band bending fluctuations in the experimental data, which are due to fluctuations of the surface potential because of large charges at the interface, which is not taken into account in the model. The derived interface state densities are similar to previously measured densities, derived by applying the conductance method. The border trap density shows a peaked density of 3 1019/eVcm3 about 0.4 eV above the conduction band edge energy for In0.53Ga0.47As MOS capacitors and a peaked density of 2 1020/eVcm3 about 0.2 eV above the conduction band edge energy for InP capacitors.

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