Intrinsic Leakage in Low Power Deep Submicron CMOS ICs Ali Keshavarzi 4100 Sara Road Intel Corporation Rio Rancho, NM 87 124 ali-keshavarzi @ccm.rr.intel.com

Kaushik Roy School of ECE Purdue University West Lafayette, IN 47907 kaushik @ ecn.purdue.edu

ABSTRACT:

The large leakage currents in deep submicron transistors threaten future products and established quality manufacturing techniques. These include the ability to manufacture low power and battery operated products, and the ability to perform IDDQ sensitive measurements with the significant ensuing benefits to test, reliability, and failure analysis. This paper reports transistor intrinsic leakage reduction as functions of bias point, temperature, source-well backbiasing, and lowered power supply (VDD). These device properties are applied to a test application that combines IDDQ and F M A X to establish a 2-parameter limit for distinguishing intrinsic and extrinsic (defect) leakages in microprocessors with leakage. high background IDDQ

I. Introduction The ability to control power in ICs is linked to control of transient and quiescent power. Control of quiescent leakage currents will allow use of deep submicron transistor circuits in low power and battery operated products and will retain the quiescent power supply current ( 1 0 ~ ~measurement ) technique for the large, fast ICs projected by the SINSematech Roadmap 11-61. The motivation is to measure and understand the leakage properties of deep submicron transistors which is essential to guide solutions for reducing power and leakage per transistor. IDDQ is a quiescent power parameter used by the test process to detect defects with high sensitivity. It is used in failure analysis to assist defect location and also by reliability engineers to screen out extrinsic defects that cause field failures [3]. The problem of deep submicron transistor leakage must be solved or the performance goals of the SINSematech Roadmap will apply to an increasingly narrow list of product types. Experimental deep submicron transistor data were used here to delineate the components of transistor leakage that contribute to total IDDQ of an IC. Transistor off-state current (IoFF) is the drain current when the gate-to-source voltage is zero. IO^ is influenced by threshold voltage, channel physical dimensions, channellsurface doping profile, draidsource junction depth, gate oxide thickness, and VDD. IoFF in long channel devices is dominated by leakage from the drain-well and well-substrate reverse bias pn junctions [4]. Short channel transistors require lower

Paper 7.3 146

Charles F. Hawkins EECE Dept. University of New Mexico Albuquerque, NM 87 13 1 hawkins @eece.unm.edu

power supply levels to reduce internal electric fields and power consumption. This forces a design reduction in the threshold voltage, VT, that causes a relatively large rise in IOW This increase is due to weak inversion state leakage that is a function of VT and not transistor channel length. In this paper we focus on all leakage mechanisms contributing to IDDQ (not just the drain terminal). Other leakage mechanisms are peculiar to the small geometries themselves. As drain voltage VD increases, the drain to channel depletion region widens and significant drain current can result. This increase in IOWis typically due to channel surface current from drain-induced barrier lowering (DIBL) or to deep channel punchthrough currents [7-111. Other IoFF leakage mechanisms include gateinduced drain leakage (GIDL), oxide tunneling, and gate narrow width effects. Measurements will illustrate these leakage current mechanisms and their properties in deep submicron transistors. The dominant off-state leakage in our short channel L,R samples was weak inversion with distinguishable short channel effect (SCE) contributions from DIBL and GIDL at elevated VDD. Experiments were conducted to show how IOWcan be reduced with cooler temperatures, substrate backbias, and lowering V D D in the quiescent logic state. This information was used to interpret leakage properties of a large IDDQ-teStabk microprocessor with over 3 million transistors. IDDQ as a general test pattern measurement is primarily used to detect circuit defects, design errors, or process deviations [12]. In a different application of IDDQ, we used standby current (IsB)to relate intrinsic die leakage to microprocessor performance (FMAx). IsB is an IDDQ measurement for one logic state, but is primarily used to measure standby static power. The clock is disabled during standby. The microprocessor and wafer scribeline transistors in this study were from a 0.35 pm CMOS process technology with Leff< 0.25 pm and nominal VDD= 2.5 V [ 131. The p- and n-channel test chip transistors were geometrically sized at 20~0.36,20~0.4, and 20x20 microns. The surface p channel transistors had shorter Leff than the n-channel transistors due to lateral Boron diffusion from drains and sources during fabrication. Despite this, the p-channel

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transistors had substantially lower IOW compared to nchannel transistors. This study used wafer lots in which IDDQand IOW were at the high leaka,ge tail of the distribution, so that off-state leakages and IDDQ are higher than normal for this technology. The next section examines device off-state leakages for various technologies.

Table 2. IOWfor LDD and HDD CMOS Devices.

I

0.4

Table I compares IOWfor various technologies and shows the increasing leakage of smaller sized deep submicron transistors. These leakages (pA/um) for present and older technologies are typical values from a rarige of data. IOW was measured under various conditions. 0.25 pm and 0.18 pm technology values were estimated from diffusion current physics (which covers several of the mechanisms described above). Table 1 is approximate and not intended as a Roadmap guide. It clearly shows that transistor IOW is increasing as technologies evolve, however, data predicting exact leakage values with Roadmap goals [6] can be inaccurate and misleading.

0.36

I

Table 1. Comparisons of Process Technologies

I

Table 2 shows off-state leakage (Iop) variation between test transistors made in 0.35 pm dimensions, but in two different technologies and at drawn channel lengths of 20, 0.4, and 0.36 um. A 3.3 V BiCMOS technology with LDD (Lightly Doped Drain) is compared to an identical geometry 2.5 V CMOS HDD (Heavily Doped Drain) transistor. The HDD structures have abrupt, heavily doped profiles near the drain and source. The p-channel transistors are surface devices.

n- and p-channel leakages were comparable for the 20 pm channel devices that are dominated by p n junctions (Tabde 2). For the 0.4 pm n-transistors, the HDI> structures have higher IOWas SCE's appear and, for the 0.36 pm devices, all transistors showed different, but large off-state leakage increases. These data show the leakage variability for various transistor architectures (LDD HDD), types @ and n), and dimensions (Lgate).

1I I1 1I 11 I1 1I

20

11. Deep Submicron Off-State Leakage

0.03

0.03

0.02

0.13

4.1

3.1

4.2

32

658

266

138

835

Another source of large IOWvariation is in the intrinsic effective channel lengths within a die, wafer, and wafer lot. L,H is presently a difficult manufacturing parameter to control. The Fall 1997 revision of the SIA Roadmap will not predict off-statla leakage values to Roadmap technologies as did piredecessor editions [ 141. The next section examines more critically the reasons for higher IOW on small transistors.

111. Transistor Lealkage Mechanisms Log&) versus VG is an important transistor curve in the saturated and linear bias states (Fig. 1). It allows measurement of many device parameters such as IOW,VT, ID(SAT), ID(LIN), g,(SAT), g,(LIN), and slope (St) of VG versus ID in the weak inversion state. IOW is measured at the VG= 0 V intercept.

1E-12 1E-13 1E-14

I

0.5

0

0.5

1

v,

1.5

2

2.5

(VI

Fig. 1. Log (ID) vs. V,? at saturated bias (VD=2.5 V) and linear bias (VD=O.1 V) states for 20x0.4 pm n-channel transistor.

The n-channel transistor (Fig. 1) had an IoFFof 20 p N p m and 4 pA/pm in the saturated and linear states. The St slope is 79 mV/decadi: of ID. The relevant bias to estimate IDDQ from IOWin Fig. 1 is VD = 2.5 V. This is the voltage applied to most logic gate transistors in the off-state.

We describe eight short channel leakage mechanisms illustrating certain with measurements (Fig. 2). 11 is reverse bias p n junction leakage, 12 is weak inversion,

Paper 7.3 1 47

I3 is Drain Induced Barrier Lowering (DIBL), 4 is Gate Induced Drain Leakage (GIBL), Is is channel punchthrough, I6 is channel surface current due to narrow width effect, 17 is oxide leakage, and Is is gate current due to hot carrier injection. Currents I, - I6 are off-state leakage mechanisms while I7 (oxide tunneling) occurs when the transistor is on. 1s can occur in the off-state, but more typically occurs during the transistor bias states in transition. Variation in the many IoFFvalues reported here reflect variation in intrinsic Ldf, V s U B ~ and temperature. D '7

Gate

?,

'7 ' 8

dominates modern device off-state leakage due to the low VT that is used. Table 3 shows transistor log&) versus VG subthreshold slopes (S,) for the different technologies listed in Table 1. S, for the test transistors in this report was about 80 mV/decade at room temperature. S, has not increased as technologies advance mainly because To, has been scaled and substrate doping profiles have improved. S, is a function of gate oxide thickness and the surface doping adjust implants. An S , 2 100 mV/decade is an indication that the device technology is leaky and unsuitable for high volume manufacturing. Lower S, values indicate better control of SCE's and a lower IOW for a given threshold voltage.

Technology

Doping mV/decade

I /J.

I

LDD

I

86

I

85

I

0.6 pm 5V CMOS '4

Fig. 2. Summary of leakage current mechanisms of deep submicron transistors 131.

1. pn Reverse Bias Current (and gated diode leakage) (11): A reverse bias p n junction leakage (II) has two main components: Qne is minority carrier drift near the edge of the depletion region and the other is due to electron-hole pair generation in the depletion region of the reverse bias junction [lo]. If both n- and p-regions are heavily doped, Zener tunneling may also be present. For an MOS transistor, additional leakage can occur between the drain and well junction from gated diode device action (overlap and vicinity of gate to the drain to well pn junctions) or carrier generation in drain to well dcpletion regions with influences of the gate on these current components [15]. pn reverse bias leakage (IRE")is a function of junction area and doping concentration [4,10]. IREv for pure diode structures in our technology was a minimal contributor to total transistor IOm. p n junction breakdown voltage was > 8 V. 2. Weak Inversion (I2): Weak inversion current between source and drain in a MOS transistor occurs when gate voltage is below VT [9,10]. The weak inversion region is seen in Fig. 1 as the linear portion of the curve. The channel has virtually no horizontal E-field so carriers move by diffusion similar to charge transport across the base of bipolar transistors. The exponential relation betwccn driving voltage on the gate and the drain current is a straight line in a log plot. Weak inversion typically

Paper 7.3 148

0.8pm5VCMOS

0.25 pm 1.8V CMOS

HDD [161

3. DIBL (Drain-Induced Barrier Lowering) (13): DIBL occurs when the depletion region of the drain interacts with the source near the channel surface to lower the source potential barrier. The source then injects carriers into the channel surface without the gate playing a role. DIBL is enhanced at higher drain voltage and shorter L,ff. Surface DIBL typically happens before deep bulk punchthrough. Ideally, DIBL does not change the slope, St, but does lower VT. Higher surface and channel doping and shallow source/drain junction depths reduce the DIBL leakage current mechanism [9,11]. Fig. 3 illustrates the DIBL effect as it moves the curve up and to the right as VD increases. DIBL can be measured at constant VG as the change in ID for a change in VD. For VD between 0.1 - 2.7 V, ID changed 1.68 decades giving a DIBL of 1.55 mVIdecade change of I D .

4. GIDL (Gate-Induced Drain Leakape) (b): GIDL current arises in the high electric field under the gate/drain overlap region causing deep depletion [ 111. GIDL occurs at a low VG and high VD bias and generates carriers into the substrate and drain from surface traps or band-to-band tunneling. It is localized along the channel width between the gate and drain. GIDL current is seen as the "hook' in the waveform of Fig. 3 that shows increasing current for negative values of VG. Thinner To,, higher VDD, and LDD

structures enhance the electric field dependent GIDL. GIDL is a major obstacle in IopFreduction.

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Fig. 4. p-channel I D VS V D for VG = - 0.5 V. -1.5 V, -2.5 V.

Weak lnvenlon 6

1E-12 1E-13

+---t---

-0.5

0

1

0.5

v,

1.5

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Fig. 3. n-channel IDvs. VG showing DIBL, GIDL, weak inversion, and pn junction reverse bias leakage components. We isolated IGDLby measuring source current log(1,) versus VG. It is seen as the dotted line extension of the VD = 4.0 V curve in Fig. 3. IGDLis removed since it uses the drain and substrate (well) terminals, not the source terminal. The GIDL contribution to IOWis small at 2.7 V, but as the drain voltage rises to 4.0 V (close to burn-in voltage), the off-state current on the VD = 4.0 V curve increases from 6 nA (at the dotted line intersection with VG = 0 V) to 42 nA, for a GIDL of 36 nA. The pure weak inversion and reverse bias pn junction current of 99 pA is approximated from the VD = 0.1 V curve.

6 . Narrow Width Effect (I6): Transistor VT in non-trench isolated technologies increases for geometric gate widths on the order of 5 0.5 um. An opposite and more complex effect is seen for trench isolated technologies that show decrease in VT for effective channel widths on the order of W 50.5 pm [16]. No narrow width effect was observed in our transistor sizes with 7N >> 0.5 um. 7. Gate Oxide Tunneling (I7): Gate oxide tunneling current I,, from high electric fielld (Eox)can cause direct tunneling through the gate or Fowler-Nordheim (FN) tunneling through the oxide bandis (eqn. (1)) [lo]. FN tunneling typically lies at a highier field strength than found at product use conditions and will probably remain so. FN tunneling has a constant slope for E,, > 6.5 MV/cm (Fig. 5). Fig. 5 shows significant direct tunneling at lower E,, for thin oxide.

5. Punchthrough (I5): Punchthrough occurs when the drain and source depletion region approach eal;h other and electrically “touch” deep in the channel. Punchthrough is a space-charge condition that allows channel current to exist deep in the subgate region causing the gate to lose control of the subgate channel region. Punchthrough current varies quadratically with drain voltage and S, increases reflecting the increase in drain leakage [lo, p.1341. Punchthrough is regarded as a subsurface version of DIBL. Fig. 4 shows an I D versus VD family of curves for two lengths of Le*. These curves were necessary to verify that short channel transistors were not in punchthrough. Punchthrough was not observed since St was constant, the transistor family of curves showed a flat saturation region, and I o ( s ~was ~ ) a linear function of I n e * (Fig. 13 later). As expected, the smaller channel shows more: current drive for a given gate voltage.

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Fig. 5. Fowler-Nordheim and direct tunneling in n-channel transistor oxide. The 60-80 8, curve shows dominance of FN tunneling while the < 50 8, curve shows FN at high E,,, but significant direct tunneling at low electric fields.

Paper 7.3 149

] : 1[:

Oxide tunneling current is presently not an issue, but could surpass weak inversion and DIBL as a dominant leakage mechanism in the future as oxides get thinner.

St(O"C)= 80mV/dec

VT = 0.35 V - [ - 0.8 x loe3

8. Hot Carrier Iniection (IS): Short channel transistors are more susceptible to injection of hot carriers (holes and electrons) into the oxide. These charges are a reliability risk and are measurable as gate and substrate currents. While past and present transistor technologies have controlled this component, it increases in amplitude as L,E is reduced unless VDDis scaled accordingly.

IV.

IoFF

Parametric Reduction Techniques

In this section, temperature, source-to-well back-biasing data, and lowered power supply voltage in quiescent state are examined for effectiveness in reducing IoW. 1. Temuerature: Log(ID) versus VG shows a linear change in slope S, with temperature (Fig. 6) as predicted by the logarithm of the bipolar model [9,10]. Eqn. (2) shows the St relation where Cd and CO, are the channel depletion and thin oxide capacitances. St varied from 81.9 to 58.2 mV/decade as the temperature was lowered from 25 OC to 50 'C. The reduction in IoFFis 160 pA to 0.45 pA for the 20 pm wide device (8 pA/pm to 23 fA/pm). The IOW reduction factor is 356.

current decades are: and

= 73.3 mV/dec

~

*

- 25 OK] = 0.37 V

0.37 V = 5.05 decades 73.3 mV I dec Iow(0 "C) =

1 PA 105.05

= 8.9pA

The reduction factor is 42 pAB.9 pA = 4.7 which is close to the measured value of 5.6.

2. Substrate-Well Biasing: Biasing the source-well to negative voltages for an n-channel and positive voltages for ap-channel transistor increases V, [9,10]. Fig. 7 shows suppression in n-channel drain current when the source-towell voltage is backbiased from 0 to -5 V (the backbias is the well voltage). Virtually no change is seen in S, (Fig. 7) in contrast to the temperature effect (Fig. 6). An important observation from Fig. 7 is that as VT increases IOW decreases. -

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Fig. 7. n-channel log(ID)vs VG for six substrate biases on a 0.35 pm logic process technology (VD= 2.7 V).

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Fig. 6. ID vs. VG showing temperature sensitivity of IOFF. Two parameters reduce IOWas temperature is lowered: (1) St linearly drops with Kelvin temperature, (2) threshold voltage VT increases. The temperature coefficient of VT was measured at about -0.8 m V k for these thin oxides. This allows estimates of IOW at other temperatures. Examule: At room temperature, if VT = 0.35 V measured at ID= 1 uA, S , = 80 mV/dec, and IoFF = 42 pA, then IoFF(0 "C)can be estimated. From Eqn. (2)

Paper 7.3 150

Fig. 8(a) enlarges Fig. 7 around the off-state region. IoFF drops from 9.58 nA at VSUB = 0 V to 2.18 pA at VsUB = - 4 V (479 to 109 fA/um) for a reduction factor of 4,394. GIDL elevates IOWas VsUBdrops below =: - 4 V showing no benefit in IoWreduction for VSUB < - 4 V. Fig. 8(b) shows IOWfor a p-channel transistor as Vsus goes from 0 to 5 V. IOW drops from 26 pA at VsUB= 0 V to 10 fA at VSUB= 2 V (1.3 to 0.5 fA/pm) for a reduction factor of 2,600. GIDL is more severe in this p-channel transistor as IOW elevates when VsUB> 2 V. GIDL behavior should be characterized for each technology to find optimum substrate bias conditions. io^ reduction factors for well backbiasing have an intrinsic variation with L,E so that characterization should determine mean and standard deviations to access expected IoFFreduction capability.

Table 4. IOFF and Power Reduction Factors with VD and VSw"

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Fig. 8(a). n-channel log I, vs. VGfor six substrate biases on a 0.35 pm process technology (V, = 2.7 V). 1 aE06 1

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I 1.5 I 0.139 I 42 I 33.3k I 60k I * IOW and quiescent (Q) power reduction factors calculated at VS"B=3V are scaled to 1.4 nA (at VD=2.7 V, VsuB=O V). Q-Power = VI, IoFF.

V. IOFF,

IDDQ,

and CMOS Microprocessor Testing

This section relates transistor off-state current to performance of a 32-bit CMOS microprocessor. A common IC design practice increases the maximum operating frequency (FMAX)for a given CMOS technology by lithographically reducing transistor channel lengths and Leg to less than a given process target. This increases transistor intrinsic off-s tate leakage, but the shortened L,R provides higher IC operating clock frequencies. As transistor IoFFincreases,, the standby current (ISB)and IDDQ increase.

0.3

VG (V)

Fig. 8(b). p-channel log IDvs. VGfor six substrate biases on a 0.35 pm process technology (V, = -2.7 V). This GIDL interference with backbias IOWreduction was further examined. IOFF was ITlGNlred for backbiases at lower VD in an attempt to decrease elecitric fields and reduce GIDL. While lowering VD did decrease Iom, we found that GIDL still elevated 1 0 as~ VsUB ~ became more negative than -3 V. Table 4 summarizes the IOW values at three VD and two VsuB values for an n-channel transistor. If concurrent IoFF reduction is used with substrate backbiasing and lowered VD, then the reduction is multiplicative. The data in column 4 show an IOW reduction factor of 14.9k for VD = 2.0 V and 33.3k for VD = 1.5 V. The reductions in quiescent (0) power were 20.1k and 60k for the same VD and VsuB conditions. These results show that IoFF suppression and quiescent power reduction from backbiasing will improve to a certain point and then further lowering of VsUBonly increases IOW. However, larger reductions can be achieved by concurrently lowering VsUBand VD. Studies are needed to determine the effect of lowering VDD on signal to noise ratio of IDDQdetectable defects.

A cumulative distribution of IsB is shown for a population of experimental data on a microprocessor with intrinsically short channel lengths (Fig. 9). Curve (b) shows die that are intrinsically leakier than those in Curve (a) because wafer (b) has die with smallrx L,ff transistors. The IsB (IDDQ) values are large due to measurement at 85 oc for a population of die with very short channel lengths. The shorter L,r on the die increased IsB causing the observed tail. Is8 measured at the IC level is a summation of the leakage for all transistors in the IC and is dominated by the transistors with minimum channel length.

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Fig. 9. Intrinsic cumulative distribution for ISBat 85 O C for ICs with: (ai) short Lgae,(b) very short Lgate.

Paper 7.3 151

An important observation is that the microprocessors in distribution (b) are markedly faster than those in (a). Two key observations: ( 1 ) no punchthrough existed as shown in earlier data (and later in Fig. 12), (2) No extrinsic defect leakage in the distribution was observed (based on controlled experiment with effective channel length). The critical parameter that affects device speed and offstate leakage is the transistor effective length, not the geometric length. Several properties change as the intrinsic L,ff becomes smaller. First, DIBL increases allowing more charge to enter the channel from the source and threshold voltage goes down. Fig. 10 shows this VT effect measured on a distribution of intrinsically short p channel transistors. The test transistors were measured in the wafer scribe lines. The data in Fig. 10-14 are modified for publication (absolute values are not necessary to show these effects).

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Fig. 10. VT vs. Le, for short p-channel transistors.

A related effect is the increase in Iom as L,K becomes smaller (Fig. 11). IOWhas a log-linear response to L,ff (Fig. 11) while VT has a linear response to L,ff(Fig. IO).

'

: 0.18

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: 0.19

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0.2

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0.22

0.23

Lfl(um)- Normallzed

Fig. 11. IoFFvs. Le, for short p-channel transistors.

Paper 7.3 152

0.25

4.2

Fig. 12. Iom vs. VT for short p-channel transistors.

Fig. 13 shows these relations with ID(SAT) versus l/Leff measurements. Transistors with shorter Leff will charge and discharge load capacitances faster than long transistors. Eqn. (3) is the saturation current equation for a MOSFET and shows ID(SAT)as a linear function of 1/ Leg [IO]. K is the conduction constant.

W

ID(SAT) =

0.17

0.3

-

VT IV) Normalized

0.24

Len (um) -Normalire

1E-101

4.35

0.4

Shorter channel lengths reduce transit time of carriers moving from source to drain and load gate to channel capacitance, so that the device and circuit are faster. A lower VT allows stronger drive to transistors with shorter channel length, but the reduced VT increases IOW. If the same gate voltage is applied to a distribution of Leff transistors, then shorter transistors will show more drain current response (gm) or ID(SAT). Drain current in the saturated state is an indicator of how fast a transistor can charge and discharge load capacitance during logic transition.

.

4.2T vT

The log-linear relation between IOWand VT is shown in Fig. 12. This exponential relation shows orders of magnitude reduction in IOWfor smaller magnitude changes in VT.

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K *

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0.W 6

7

8

llleft (ut")

(3)

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Fig. 13. ID(SAT) vs. l/Leffforp-channel transistors.

I 8

Importantly, Figures 4 and 13 support evidence that the ICs in Fig. 9 are not in punchthrough; the IC's from distribution tail are leakier due to weak inversion and DIBL effects. We found a clear correlation between IDD(! (IsB) and the maximum operating frequency (FMAX) of a microprocessor as both are functions of L,ff. Fig. 14 summarizes the previous figures showing how F M A X and ISB track each other. IsB and F M A X are: fundamentally related as both are functions of channel1 length. This relation was used in testing. An adjustable Ise, limit can be set based upon the parameters I[ss and FMAX to establish a 2-parameter test limit that distinguishes fast and slow die from those that are defective. The concept allows, for improved signal to noise ratio for defect detection for high performance ICs with high background leakage levels.

the corresponding FMAX value put an IC in one of four categories. The upper limit is determined by the user incorporating various components of variation. For example, many dice may be characterized by a Gaussian distribution with limits typically set at 30 to 40 or limits may be chosen based on empirical data and acceptable yield loss. Table 5. I C decision matrix for IsB and

L

VI. Discussion

.. = nM**+r*+

Normalized Maximum IFrequency i:FUlx)

Fig. 14. Iss versus FNAXfor 32-bit microprocessor.

Fig. 15 further illustrates the test application. We have assumed a linear dependency for simplicity. Intrinsic values of ISB can be distinguished from extrinsic (defect driven) ISB values and a limit set up to reject the defective ICs. The ISBlimit moves up as F M A X 1ncreases. '

-

FMAX VS ISB

I)

I

Intrinsic leakage Reduction: At least five approaches exist to lower intrinsic leakage allowing low power operation and IDDQ testability: (1) temperature reduction, (2) substrate backbiasing, (3) lowered quiescent VDD, (4) multiple transistor threshold designs, (5) alternative technologies (SOI). These are discussed below.

Defects

..... Upper Limit

-.

Leakage Reduction Faclm: IoFFreduction factors can be used as estimates for each product. For example, if a product has a mean IDDQ of 100 mA and substrate backbiasing achieves a reduction of 2,500, then mean intrinsic I D Dshould ~ fall to about 40 uA. If both substrate backbiasing and quiescent VDD lowering were used to suppress I, then a mean of about 3-7 uA would be expected. We emphasize that these reduction factors were obtained for data measured on our technology and may differ with each company process. Also, the intrinsic IDDQ must be dominantly due to weak inversion and not a design, defect, or fab induced leakage.

-+

FMAX Fig. 15. Ise versus FMAx for the 32-bit microprocessor.

(1) Temperature: The sensitivity factor S, predictably decreases with lowered temperature while VT rises both factors contribute to a decrease in IOW. For test practices that use T -50 O C (military applications), the reduction factor measured here was 356; a relatively small fraction, but usieful if intrinsic IDDQ is on the order of 1-10 mA. The major reason for this smaller temperature reduction is that the VT temperature coefficient decreases as transistor oxides get thinner. The rise in VT with cooler temperatures is becoming insignificant and temperature as a technique for intrinsic leakage and IDDQreduction may lose its efficiency for the oxides that are getting thinner with SIA Roadmap achievsements.

Table 5 is a decision matrix when I ~ sand F ~ ~values A x are High (H) or Low (L) at test. The IsB value coupled with Paper 7.3 153

(2) Substrate (Well) Backbiasing: The VSUBdata show that backbiasing during the quiescent portion of a logic cycle offers significant reduction in intrinsic leakage current. Reduction factors between 2500 to 4400 were reported for backbiases between 12 V to 3 VI. These backbiases are applied during the quiescent, not the transient portion of the logic cycle. In our technology, GIDL was insignificant at user biases (VSUB = 0 V), but was a limiting variable in further suppression of IOWby backbiasing. If GIDL can be better controlled for larger substrate backbiases, then larger reductions in IoFF can be achieved [ 11. A second limiting factor in the amount of backbias applied to the transistor is the increased field across the thin oxide. The thin oxide takes virtually all of the backbias voltage. For example, if VG = 0 V, VsuB = - 4 V, and T,, = 50 A, then E,, = 8 MV/cm which is not a reasonable value for E,,. Fig. 5 showed a transistor with 60 - 80 A oxide in which significant FN tunneling occurs for E,, > 6.5 MVJcm. Another caution is that these higher fields stress the oxide into a regime where oxide wearout becomes a concern. While the combination of well backbiasing and VDD reduction offers an approach for power reduction and IDDQ measurements in deep sub micron ICs, these data advise caution. Substrate backbiasing must be used carefully. Each technology must be characterized to understand the relation between GIDL, IoFF, and backbiasing. Indiscriminate backbiasing of the wells may lead to higher Iom if GIDL is not understood. These effects are highly sensitive to T,, and other technology parameters. A challenge is the layout required to achieve separate voltage control of source and wells for II- and p-channel transistors and tradeoffs such as area and cost. Sachdev has proposed such designs that separate source and well contacts during the quiescent portion of logic cycle [ 11. (3) Lowering Ouiescent VDD: Leakage currents decrease as VDDis lowered (Fig. 1 and 3) which is uniformly good for quiescent power reduction and reliability. However, lowering quiescent VDD to decrease background IDDQto detect defects is more complicated. A description of this interaction is beyond the scope of the paper, but some observations will be made. The effect on IDDQdefect detection signal to noise ratio by lowering quiescent VDD depends upon defect location, defect type, and whether the transistor driving a defect is in the saturated or linear state. The background noise is not random noise, but the DC leakage currents of the transistors. In deep submicron transistors, this noise current may be weak inversion, p n junction,

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GIDL, DIBL, punchthrough, or oxide tunneling current. Model equations for each leakage mechanism can be compared to the various IDDQdefect situations.

(4) Multiple Threshold (MT) CMOS: Fig. 12 quantifies the exponential reduction in IoFF as VT increases. This is the essence of the MT technique to reduce 1 0 ~ . Slower and noise margin sensitive subcircuits of an IC will have transistors with higher VT and fast portions of the circuit will have lower VT. MT can be implemented specifically in the quiescent mode by backbiasing (discussed before) or more globally by process technology using threshold adjust implant. Several aspects of MT design have been reviewed [ I ,181.

( 5 ) Alternative Technologies (SOI): SO1 devices have small parasitic capacitances and nearly ideal subthreshold characteristics. SO1 represents a possible technology having superior leakage (ideal St of 60 mV/dec at room temperature and better weak inversion leakage) and capacitive advantages. If we compare the room temperature weak inversion component of IoFF of an SO1 transistor (60 mV/dec) with the example in Section IV (80 mVIdec and VT = 0.35 V), then the IOWreduction factor for SO1 is 28X. Substrate backbiasing and other IOW reduction techniques can also be applied to SOL This technology is reviewed in [1,18,19]. Increased IOm, IDDQ, and quiescent power are serious concerns as transistors shrink. IDDQtesting is the only working technique to detect bridge defects and certain forms of open defects. Its overall high defect detection efficiency has been reported most recently by Maxwell, et al. [20], and Nigh et al., [21]. The positive IDDQ economic impact on reliability and burn-in reduction has been reported [22]. Finally, while long used in failure analysis techniques, breakthroughs are recently reported by Nigh and Forlenza using IDDQ and other test data for noninvasive failure analysis [23].

VII. Conclusions We found the following major conclusions for measurements on our technology that reduce power in the quiescent mode as opposed to the transient mode. Substrate backbiasing reduced leakage currents by factors of 2500 to 4400 and was the most promising single variable in high leakage suppression. Substrate backbiasing in combination with reduced VDD in the quiescent state gave large reduction factors in leakage current of about 15k to 33k and in quiescent power of about 20k to 60k.

Larger reductions can be obtained with substrate backbiasing, but the GIDL effect must be controlled during the backbias. The influence of L,ff on IOW, VT, IsB, and F M A X was used tactically to discriminate between intrinsic ancl extrinsic (defective) ICs at test for a 32-bit microprocessor. The dominant intrinsic leakage mechanisms for present technology are weak inversion and DIBL, however, direct tunneling of electrons through the thin gate oxide may be a doiminating leakage factor in future generation ICs. Multiple VT CMOS shows promise in reduction OS leakage - four orders of magnitude reduction in Ion: for a 150 mV change in VT (Fig. 12) for a given process technology.

Acknowledgments We would like to thank Shekhar Borkar, Vivek De, Kent Fuchs, Richard Green, Wayne Needham, Gerry Neudeck, Moises Ortiz, Bob Pierret, Gopal Rao, John Sherman, Glenn Shirley, Deo Singh, Jerry Soden, Josh Walden, Mike Wegener, and Murray Woods for valuable discussions and their contributions. Kaushik Roy’s research is sponsored by DARPA [F33615-95-C-1625] and NSF Career Award [9S01869-MIP]. Charles F. Hawkins was on a sabbatical leave at Intel Corporation in 1997.

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10. R.F. Pierret, Semiconductor Device Fundamentals, AddisonWesley, Reading, MA, 1996. 1 1. J.R. Brews, Chap. 3 in, High Speed Semiconductor Devices, ed. S.M. Sze, John Wiley & Sons, New York,1990. 12. J.M. Soden, C.F. Hawkins, R.K. Gulati, W. Mao, ‘‘IDDQ Testing: A Review, Journal of Electronic Testing: Theory andApplications, Vol. 3, No. 4, pp. 291-303, Dec. 1992. 13. M. Bohr, et al., “A High Performance 0.35 pm Logic Technology for 3.3 V and 2.5 V Operation,” IEDM Tech. Dig., p. 273, Dec. 1994. 14. Wayne Needham, Intel Corp., Personal Comm., Feb. 1997. 15. AS. Grove, Physics and Technology of Semiconductor Devices, John Wiley &: Sons, 1967. 16. M. Bohr, et al., “A High Performance 0.25 pm Logic Technology Optimized for 1.8 V Operation,” IEDM Tech. Dig., pp. 847-851, Dec. 1996. 17. J.A. Mandelman and J. Alsmeier, “Anomalous Narrow Channel Effect in Trench-Isolated Buried-Channel p MOSFET‘s,” IEEE Elec. Dev. Ltr., vol. 15, no. 12. Dec. 1994. 18. L. Wei, Z. Chen, and K. Roy ,”Double Gate Dynamic Threshold Voltage (DlGDT) SO1 MOSFETs for Low Power High Performance Designs,” IEEE SO1 Conf., 1997. 19. Y. Taur, et al., “CMOS Scaling into the Nanometer Regime,” Proc. IEEE, pp. 486-503. Vol. 85, April 1997. 20. P.C. Maxwell, R.C. Aitken, K.R. Kollitz, and A.C. Brown, ”100~and AC Scan: The War on Unmodeled Defects,” Int. Test Conf, pp. 250-258, Oct. 1996. 21. P. Nigh, W. Needham, K. Butler, P. Maxwell, R. Aitken, and W. Maly, “So, What is an Optimal Test Mix? A Discussion of the Sematech Methods Experiment,” Int. Test Conf., Nov. 1997. 22. T.R. Henry and T. Soo, “Burn-In Elimination of a High Volume Microprocessor Using IDDQ,” Int. Test Conf., pp. 242-249, Oct. 1996. 23. P. Nigh and D. Forlenza, “Application & Analysis of IDoQ Diagnostic and Fault !iimulation Software,” Int. Test Conf., Nov. 1997. ”

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