ISPD 2014 Benchmarks with Sub-45nm Technology Rules for Detailed-Routing-Driven Placement Vladimir Yutsis

Ismail S. Bustany

David Chinnery

Joseph R. Shinnerl

Mentor Graphics Corporation Fremont, California, USA {Vladimir_Yutsis, Ismail_Bustany, David_Chinnery, Joseph_Shinnerl}@mentor.com

Wen-Hao Liu Department of Computer Science National Tsing Hua University, Hsinchu, Taiwan [email protected]

ABSTRACT The public release of realistic industrial placement benchmarks by IBM and Intel Corporations from 1998–2013 has been crucial to the progress in physical-design algorithms during those years. Direct comparisons of academic tools on these test cases, including widely publicized contests, have spurred researchers to discover faster, more scalable algorithms with significantly improved quality of results. Nevertheless, close examination of these benchmarks reveals that the removal of important physical data from them prior to release now presents a serious obstacle to any accurate appraisal of the detailed routability of their placements. Recent studies suggest that academic placement algorithms may lack sufficient awareness of the pin geometry and routing rules missing from these benchmarks to adequately address the challenge of computing routable placements at 28nm-process technologies and below. In this article, the reconstitution of the existing benchmarks via the injection of realistic yet fictitious pin data and routing rules is described. The enhanced benchmarks enable more meaningful comparisons of new placement algorithms by industrial detailed routing, beginning with the 2014 ISPD placement contest.

Categories and Subject Descriptors B.7.2 [Integrated Circuits]: Design Aids - Placement and Routing; D.2.8 [Software Engineering]: Metrics—complexity measures, performance measures

General Terms Algorithms, Design Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]. ISPD’14, March 30–April 2, 2014, Petaluma, CA, USA. Copyright 2014 ACM 978-1-4503-2592-9/14/03 ...$15.00. http://dx.doi.org/10.1145/2560519.2565877 .

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(b)

Figure 1: Sample GR/DR miscorrelation: (a) errors predicted by GR (b) actual DR errors.

Keywords Placement; routability; placement evaluation; global routing; detailed routing

1.

INTRODUCTION

As design rules continue to proliferate with downward scaling in the fabrication technology of integrated circuits, the importance of accuracy in routability modeling at the placement stage continues to increase. Numerous recent studies [1, 8, 10, 17] and contests [12, 15, 16] indicate a growing gap between the predictions of global-routing (GR) models traditionally employed in placement and the actual violations encountered by detailed routing (DR); an example is illustrated in Figure 1. Highly accurate local modeling of routability throughout global placement, however, seems unlikely to be computationally efficient. As design sizes grow to tens of millions of movable objects or more, and the design cycle itself grows ever more complex, demand on the speed and scalability of placement continues to increase. Fine-grain design rules may hold little or no relevance to the coarse-grain cell-area density targets typically employed at the earliest iterations of global placement. Thus, one of the more pressing challenges to placement developers is the formulation of routability models which (a) provide high enough scale-appropriate accuracy when needed and (b) demand low computational overhead when irrelevant.

Existing benchmarks [12, 13, 15, 16] originated in industry and do illustrate much of the modern placement challenge, especially with respect to complex floorplan geometry, placement utilization, and global netlist structure. However, a large fraction of the technical specifications for these benchmarks has been removed for proprietary reasons. In addition to all timing-related data, pin shapes and their locations on cells are gone. These missing details impose hard limits on the testability of academic algorithms developed without access to proprietary design data. The release of improved global-placement test suites constructed from publicly available benchmarks is the primary contribution of our work. Reducing the gap between routability estimates used by global placement [3, 4, 5, 7] and errors revealed only by detailed routing [8, 9, 14, 18] requires test suites that better expose inadequate consideration of design rules most frequently violated during placement. While actual proprietary information cannot be released, it is not difficult for an experienced physical-design engineer to create fictitious geometry reproducing the essential challenges of real fabrication geometry. Details of our construction are listed in the remaining sections of this paper along with simplified descriptions of some design rules they expose. Without our enhancements, the existing test cases lack sufficient detail to fully reveal the miscorrelation between global routing and detailed routing seen on actual industrial designs. A brief description of the evaluation metric used for the ISPD 2014 Detailed-Routability-Driven Placement Contest is presented in the last section.

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(b)

Figure 2: Pin layout in a cell affects routability: (a) easier (b) harder.

Figure 3: Minimum spacing design rule.

2. SAMPLE DESIGN RULES General routability challenges for placement include the following. • Netlist: high-fanout nets, data paths, timing objectives • Floorplan: low or high placement utilization, irregular placeable area, narrow channels between fixed blocks • Routing constraints: routing blockages and restrictions by layer, pin access, boundary-pin placement, power/ground(pg)-grid avoidance • Design rules: minimum spacing, pin geometry, edgetype, end-of-line, non-default routing (ndr) As is customary, we label routing layers from lowest to highest as m1 (Metal 1), m2, .... Standard cells typically have pins connecting to routing wires directly on m1 but frequently have pins directly connecting to routes on m2 and, in some technologies, even up to m4. Connections to highly dense m1 pins are subject to complex design rules related to cut space, minimum metal area, end-of-line rules, double patterning rules, etc. These rules make it challenging to pre-calculate routable combinations of placed objects. Figure 2 illustrates how the availability of routing tracks within a cell, as determined by pin geometry, influences the ease of routing to the cell. For 65nm technology and below, many design rules are imposed to ensure a printable gdsii mask [2], and contemporary industrial detailed routers typically issue reports on 40 or more distinct types of design-rule-check (drc) violations. However, we view a handful of the most commonly violated of these as generally representative: minimum spacing, end-of-line, non-default routing (ndr), edge-type, and

blocked pin. These are described in the remainder of this section.

2.1

Minimum-Spacing Rule

There is a required minimum spacing between any two metal edges. This minimum spacing requirement depends on both the widths of the two adjacent metal objects and the parallel length of one object’s neighboring edge projected on to the other object’s edge facing it. See Figure 3.

2.2

End-of-Line Rule (EOL)

eol is another spacing rule between objects, but more than two shapes can be involved, and various distance metrics can be used. A 3-object eol between the top of Object 1 and the bottom of Object 2 is illustrated in Figure 4. eol is a function of these four parameters:

Figure 4: EOL-spacing rule terms defined.

(a) (b)

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Figure 5: EOL-spacing violations can occur if cells with L-shaped pins are abutted.

Figure 7: EOL violations due to NDR. (a) EOL spacing violation for routing objects within overcongested areas; (b) Double-width magenta pin with NDR assigned; (c) Double-width wires in accordance with the NDR assigned to magenta pin.

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(a)

(b)

Figure 6: Example violations of (a) minimum spacing and (b) EOL spacing restrictions between routing objects within over-congested areas. Most of these violations occur in the vicinity of pins assigned with an NDR. Length of end: A minimum width for Object 1 to avoid a violation. Parallel length: Vertical distance below the top of Object 1 within which Object 3 will increase the minimum spacing between Objects 1 and 2. Halo: Area around corner of Object 1 where Object 2 may trigger the eol rule. Parallel halo: Minimum spacing between Object 1 and Object 3 to avoid a violation. The parallel halo is a second spacing requirement triggered by the eol spacing. See Figures 5 and 6 for example eol violations.

2.3 Non-Default Routing Rule (NDR) Non-default routing rules may specify by routing layer increased wire spacing for a net, increased wire width for a net, or increased via cut number at selected junctions [2]. Via cut number is the number of vias connected to a wire at a single junction. In practice, such rules might be imposed to avoid electromigration or to reduce wire delay. An ndr may be assigned to a cell pin for wires or vias connecting to it. An ndr may or may not accompany increased pin width or specific non-rectangular pins. ndrs are specified in the floorplan def file but may be assigned to a pin in the cell lef file. See Figure 7.

2.4 Edge-Type Rule While the preceding rules apply uniformly to all shapes based on geometry alone, an edge-type rule is specific to neighboring vertical-edge pairs of particular cell instances.

)

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Figure 8: Four edge-type violations. Double width M2 is used for the red pins. An edge-type doublespacing constraint is also enforced at the adjacent cell edge. These spacings may be required to improve yield, for spacing between different implant dosages, to ensure pin reachability, etc. Examples: • The left edge of every ao22s01 cell must be placed at least 0.600µm away from the right edge of every a034s01 cell adjacent to it. • The left edge of every ao22s01 cell must be placed at least 0.400µm away from the left edge of every other ao22s01 cell. • The left edge of every ao22s01 cell must be placed at least 0.800µm away from the right edge of every other ao22s01 cell adjacent to it. See Figure 8.

2.5

Blocked Pin

A blocked pin cannot be reached by a via or wire without violations. See Figure 9.

(a)

(c) #cells #nets #I/Os #macs util w ¯ σ(w) ρ¯ σ(ρ) λ π

(b) Figure 9: Blocked pins. (a) M1 pins (blue) under M2 power stripe (pink) are not accessible by vias. (b) M2 pin (red) overlaps M2 stripe. (c) M2 pins with NDR assigned are placed too close to each other.

3. BENCHMARKS Two separate benchmark suites,1 A and B, have been adapted from public suites used in previous contests. Both suites have been translated [8] from Bookshelf Format [6] to lef/def format [2] so that industrial routers can parse and route the benchmarks. Neither suite has region constraints, and all standard-cell rows in each design are the same height. There are no fixed standard cells or movable macros in any of the test cases. Each suite presents routability challenges in different ways, as described below. Some characteristic data for the benchmarks are presented in Tables 3 and 5, following notation in Table 1. The statistics on cell widths, pin areas per cell, and boundary perimeter provide some crude, aggregated proxies for routability complexity. Smaller average cell widths will tend to amplify routability congestion caused by high cell-area density. Higher pin density per cell may obstruct routing tracks inside cells (Figure 2) and make pins harder to reach. The placement boundary includes contours around all interior fixed macros (Figure 11) as well as the primary contour enclosing the entire placement region. A relatively longer boundary indicates more concave corners in the placement region, increased likelihood of narrow channels, and increased complexity in the estimation of wirelength and routing congestion due to fixed obstructions along signal paths.

Table 2: Suite A PG-grid geometry (µm) by layer m1 m2 m3 m4 m5 rail width wr 0.51 0.58 3.50 4.00 4.00 rail spacing sr 1.49 20.0 14.0 20.0 14.0 The test cases have the following additional characteristics; most of these are modifications made to the original data in order to increase expected routing difficulty. 1. Each cell instance is down-sized to the minimum area available for it in the associated 65nm cell library.2 2. The routing pitch (minimum track height) is 0.2µm. 3. There are 10 routing tracks per standard cell row; hence, each such row is 2.0µm high. 4. All movable cells are single-row high. 5. Except for L-shaped pins, all pins are uniformly shaped rectangles 1µm high by 0.1µm wide. 6. Approximately 7.7 % of all cell instances of test case edit_dist and 0.02% of the 2nd variant of test case pci_bridge32 are given exactly one L-shaped output pin each, placed as shown in Figure 5. 7. The rectangular pins on each cell are grouped in pairs uniformly spaced 0.3µm apart, including the spacing between the left-most pair and the left cell edge. Pins in each pair are placed the minimum-spacing distance from each other. 8. The I/O pins have been placed by Olympus-SoCTM [11] along the boundaries of the m3, m4, and m5 layers and marked fixed. 9. Most cell pins are located on layer m1. 10. ndr with double wire width and double wire spacing is assigned to all nets with fanout > 10. 11. The driving pin of standard cell ms00f80 is promoted to layer m2 to check the ability of placement to prevent its intersection with pg rails. 12. Standard cell ao22s01 has output pin near edge on m1 but has edge-type constraint with 2× spacing, i.e., 0.2µm. 13. There are 5 routing layers, but only 4 routing layers are available: m2, m3, m4, and m5. 14. Cells have signal pins only, no power or ground pins. m1 may be used only for vias to m1 pins. m1 is otherwise excluded from routing.

3.1 Suite A Suite A consists of eight test cases adapted from benchmarks released by Intel Corporation for the ISPD 2013 discrete cell-sizing contest [13]. These test cases have essentially the simplest possible floorplan geometry. Each of the test cases has a rectangular placement region without fixed macros or any other fixed obstructions. All movable objects are standard cells of comparable sizes. Thus, routability challenges in these test cases arise only from cell sizes, pin geometry, power/ground (pg) grid geometry, design rules, and cell placements. Suite A pg grid geometry is listed in Table 2. 1 As of this writing, some specifications of these benchmarks are being adjusted and may still change, in order to provide an appropriate level of difficulty. Additional test-case variants are also being considered. All such changes and additional test cases, if any, will be collected and posted on the ISPD 2014 contest web site as an addendum to this article.

Table 1: Benchmark data notation number of movable standard cells number of nets number of fixed I/O pins number of fixed macros (cell area) / (placeable region area) average standard-cell width (µm) std. deviation in standard cell widths (µm) average per-cell of (pin area)/(cell area) std. deviation of (per-cell pin area)/cell area (number L-shaped pins)/(total number of pins) (boundary perimeter)/(bounding-box perimeter)

2

Despite the 65nm cell library, the modified routing dimensions and additional design rules do present challenges typical of sub45nm designs.

To enable detailed routing, the translator [8] has been adapted to modify the benchmarks as follows.

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(b)

Figure 10: Example standard cells from Suites A (a) and B (b). Table 4: Suite B PG-grid geometry (µm) by layer m2 m3 m4 m5 m6 m7 rail width wr 0.10 0.86 0.80 0.90 0.90 1.0 rail spacing sr 9.0 18.0 9.0 18.0 9.0 18.0

15. On some designs, m5 is also blocked to increase routing difficulty. This is representative of designs where fewer routing layers are used to reduce fabrication cost. 16. More conservative minimum-spacing, edge-type, and end-of-line design rules have been added. 17. Non-default routing rules — double width, double spacing, double-cut vias, layer restrictions — are assigned to medium-fanout nets and to some cell pins. Figure 10 shows example standard cell layouts. The design rules listed above were applied uniformly across all the test cases in Benchmark Suite A. However, Design Rule 1 below was applied in two different ways to each of the following designs only: des_perf, edit_dist, and pci_bridge32. Hence, each of these test cases has two variants, as listed in Table 3. Design Rule 1. Standard cell oa22f01 has output pin ‘o’ promoted to m2 and imposed 2× width, 2× spacing, doublecut vias ndr. This restriction should be observed within 1.0µm, i.e., 5 pitches of the output pin; beyond that, only default spacing rules apply. Variant 1. Double width (0.2µm) for pin ‘o’ and edgetype spacing 0.2µm assigned to edge next to pin ‘o’ with ndr double wire width and double wire spacing. Variant 2. Single-width L-shaped pin for ‘o’.

3.2 Suite B Suite B consists of three cases adapted from benchmarks released by IBM Corporation for the DAC 2012 placement contest [15]. In contrast to the test cases in Suite A, the test cases in Suite B have many fixed macros and hence more complicated floorplan geometry; see Figure 11. Suite B power/ground (pg) grid geometry is listed in Table 4. The standard cells in Suite B have been left at their given sizes.

1. Wire width and wire spacing rules are set based on the 28nm technology node. The minimum wire width and via size are set respectively to 50 nm and 50×50 nm2 . The minimum-spacing and eol spacing rules are set respectively to 50nm and 65nm. In addition, based on the default settings in the DAC 2012 benchmarks, metal layers 1–4 and 5–7 have respectively 1× and 2× the minimum wire width, via size, and wire spacing. 2. The routing pitch (minimum track height) is 0.1µm. 3. There are 9 routing tracks per standard cell row; hence, each such row is 0.9µm high. 4. All pins are uniformly sized rectangles 0.056×0.084µm2 and have been left at their given locations on cells and macros, except where their placements cause drc violations for all placements. In such cases, the offending pins have been moved minimally to prevent such drc violations. 5. Pins rendered inaccessible by routing blockages have been promoted to the top layer of the blockages to make them accessible. 6. Some I/O pins were originally located at the same position, which would cause routing violations. The translator retains only the I/O pin that appears first in the benchmark files and removes the others located at the same position. 7. All cells without any pins were removed; these amounted to less than 0.25% of total cell area. Cells with one output pin and no input pins were retained, with an input pin added but left unconnected. 8. There are between 6 and 7 routing layers available on these designs: either m1–m6 or m1–m7. In contrast to Suite A, m1 is available for routing on all test cases in Suite B. 9. A pg grid has been inserted into metal layers 2–7 following the geometry in Table 4. pg rails on m2 are spaced 10 rows apart instead of just one row apart. 10. There are neither m1 pg pins on cells nor m1 pg rails, because m1 cell signal pins are too close to their cells’ horizontal-edge boundaries and would overlap with any realistic m1 pg rails. 11. About 0.02% of standard-cell pins in the original benchmarks are at the same location and thus short the nets connecting to these pins. These shorts have been corrected by retaining only the cell pin connected to the last such net. 12. The I/O pins for the testcases in Suite B were placed by Olympus-SoC [11] on either (a) layers m6 and m7, for the test cases with m1–m7 allowed for routing, or (b) layers m5 and m6, for the test cases with m1–m6 allowed for routing. The placed I/O pins were then marked fixed. 13. Double-width-double-spacing non-default rules are assigned to nets with 60 ≤ fanout ≤ 128.

4.

PLACEMENT CONTEST EVALUATION

Submitted def placement solutions were evaluated in the Olympus-SoCTM place and route system subject to system memory limits and a 24-hour run-time limit. A script was used to check the placed designs for the following in-

Table 3: test case mgc_des_perf_1 mgc_des_perf_2 mgc_edit_dist_1 mgc_edit_dist_2 mgc_fft mgc_matrix_mult mgc_pci_bridge32_1 mgc_pci_bridge32_2

Benchmark Suite A characteristics, following notation in Table 1 #cells #nets #I/Os #macs util w ¯ σ(w) ρ¯ σ(ρ) λ 112644 112878 374 0 0.90 0.794 0.389 0.199 0.045 0 112644 112878 374 0 0.85 0.794 0.389 0.199 0.045 0 130661 133223 2574 0 0.40 0.799 0.521 0.210 0.048 0.0265 130661 133223 2574 0 0.43 0.799 0.521 0.210 0.048 0.0265 32281 33307 3010 0 0.83 0.905 0.428 0.191 0.044 0 155325 158527 4802 0 0.80 0.781 0.368 0.203 0.037 0 30675 30835 361 0 0.84 0.830 0.369 0.191 0.044 0 30675 30835 361 0 0.85 0.830 0.369 0.191 0.044 0.0001

Table 5: Benchmark Suite B characteristics, following test case #cells #nets #I/Os #macs util w ¯ mgc_superblue11 925616 935731 27371 1458 0.44 1.196 mgc_superblue12 1286948 1293436 5908 89 0.48 0.871 mgc_superblue16 680450 697458 17498 419 0.49 1.014

validating features: cells out of bounds, netlist changes, and movement of fixed objects. Valid placements were legalized and routed in Olympus-SoC. Each placement’s score S was computed as a sum of four category scores: cell legalization displacement, detailed-routing violations, detail-routed wire length, and run time: S = Sdp + Sdr + Swl + Scpu .

fas (t) = 25 · (t − a)/(b − a)

(2)

λ 0 0 0

π 6.08 3.39 5.25

Table 6: Routing violation weights Design Violation Type i Weight wi Routing open 1.0 Routing blocked pin 1.0 Routing short 1.0 Design-Rule-Check (drc) violation 0.2

(1)

The better the placement, the lower the score. Each category score is normalized and scaled to lie in [0, 25]. An invalid placement receives the worst possible score of S = 100. With the exception of the detailed routing score, all categories make use of simple affine scaling fas : [a, b] → [0, 25] defined as

notation in Table 1 σ(w) ρ¯ σ(ρ) 0.964 0.027 0.019 0.729 0.034 0.016 0.882 0.031 0.018

π 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0

score Sdp was computed ⎧ ⎨ 0 dp − 0.25 Sdp = ⎩ 25

as if if if

dp ≤ 0.25 scrh 0.25 < dp < 25.25 scrh dp ≥ 25.25 scrh.

(3)

A placement for which Sdp = 25 is considered invalid and hence receives score S = 100.

for every t ∈ [a, b].

4.1 Placement-Legalization Score All placement submissions were run through OlympusSoC placement legalization prior to routing, in order to support wide participation by global-placement teams not necessarily having access to drc-aware legalization. The Olympus-SoC placement legalization was used to fix the following defects in the submitted global placements. 1. 2. 3. 4. 5. 6. 7.

Overlaps, both cell-to-cell and cell-to-blockage Edge-type violations Cells not aligned on standard-cell rows Cells with incorrect orientation Cell pins that short to the pg grid Cell pins inaccessible due to the pg grid drc placement violations between standard cells

Significant cell displacement in legalization was penalized as follows. First, a raw legalization score dp was calculated as the average Manhattan displacement of the 10% most displaced of all cells in units of standard-cell row height (scrh).3 From dp, the legalization-displacement category 3 For well-spread placements, many cells in this 10% might have zero displacement.

4.2

Detailed-Routing Score

Weighted sum dr = dr(p) = w1 v1 + w2 v2 + w3 v3 + w4 v4 is computed from the number of violations vi of routing violation type i and weight wi in Table 6. Let drmed denote the median of these unscaled sums dr over valid placements p, and let $ dr drrel = . 1 + drmed Then Sdr =

%

2.5 · drrel 25

if if

drrel ≤ 10 drrel > 10.

In all cases, 0 ≤ Sdr ≤ 25. Square root is taken, as there may be a wide range in violation counts.

4.3

Detail-Routed Wirelength Score

Unscaled score wl is simply the final detail-routed wirelength reported by the router. Over all valid placements p on a benchmark with Sdp (p) < 25, let wlmed wlmin

= the median of the wl(p). = the minimum of the wl(p).

mgc_superblue11

mgc_superblue12

mgc_superblue16

Figure 11: Floorplans for the test cases in Suite B; all macros are fixed. Then Swl =

%

fas (wl) 25

if wl < 5 × wlmed if wl ≥ 5 × wlmed ,

where fas denotes affine scaling (2) from [wlmin , 5 · wlmed ] into [0, 25].

4.4 Run-time Score Let cpu denote total wall-clock time for placement, legalization, global routing, and detailed routing on one benchmark, on an unloaded machine with 8 cores. Each benchmark suite has a hard run-time limit per test case, cpumax . For Benchmark Suite A, cpumax = 24 hours per test case. If cpu > cpumax , then the placement is disqualified, Scpu = 25, and S = 100. Over all valid placements p on the benchmark, let cpumin = minimum of the cpu(p). Then Scpu = fas (cpu), where fas denotes affine scaling (2) from [cpumin , cpumax ] into [0, 25].

5. CONCLUSIONS Constructive collaboration between academic and industrial researchers in physical design depends on the ability of both groups to share useful test data and results. The challenge of computing routable placements in sub-45nm technology has increased with the proliferation of complex geometries and design rules, yet publicly available benchmarks to date have generally lacked the detail needed for researchers to evaluate new placement techniques accurately. The constructions described here, while far from restoring full physical realism, represent an important improvement in the test data used to quantify placement quality. Artificial reconstructions of pin geometry and routing rules in conjunction with enhanced translation [8] to lef/def format

have enabled more realistic detailed routing on those placements and a higher standard against which proposed new methods for physical design can be judged. Future enhancements can be expected to include more diverse pin geometry and routing rules and, ultimately, the incorporation of realistic timing constraints.

6.

ACKNOWLEDGMENTS

We thank the following people for their insight and help: Charles J. Alpert, Yao-Wen Chang, William Chow, Chris Chu, Azadeh Davoodi, Andrew B. Kahng, Shankar Krishnamoorthy, Igor L. Markov, Alexandre Matveev, Mustafa Ozdal, Cliff Sze, Prashant Varshney, Natarajan Viswanathan, Alexander Volkov, Benny Winefeld, Evangeline F.Y. Young.

7.

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