Introduction • Default RxVGA2 DC offset calibration method gives unstable calibration results. • The noise, which is introduced in every VGA2 gain stage (Stage A and Stage B), may cause instability of comparators in calibration loop. • To reduce noise, every VGA2 gain stage is reprogrammed before calibration. Test description: •
•
•
Set VGA2 A stage gain to 18dB and VGA2 B stage to 0dB • Run auto cal for channel I and Q, on VGA2 A stage only. • Save Cal Results. Set VGA2 A stage gain to 0dB and VGA2 B stage to 18dB. • Run auto cal for channel I and Q, on VGA2 B stage only. • Save Cal Results. Calibration executed 100 times to check repeatability.
• Both RXVGA2 calibration methods are tested and compared. Enabling Personal Broadband™
Calibration Algorithm Block Diagram RxVGA2 DC Offset Calibration Procedure Perform DC Calibration Procedure in RxVGA2SPI with ADDR:= 3 (For DC Reference Channel) and get Result
Perform DC Calibration Procedure in RxVGA2SPI with ADDR:= 1 (For DC Reference Channel) and get Result
Save TopSPI::CLK_EN Register
TopSPI::CLK_EN[4] :=1 Result == TRUE?
NO
Result == TRUE?
NO
YES
1
YES
1
RxVGA2::VGA2GAIN::=01010
Perform DC Calibration Procedure in RxVGA2SPI with ADDR:= 0 (For DC Reference Channel) and get Result
Result == TRUE?
NO
Result == TRUE?
1 YES
Perform DC Calibration Procedure in RxVGA2SPI with ADDR:= 4 (For DC Reference Channel) and get Result
Perform DC Calibration Procedure in RxVGA2SPI with ADDR:= 2 (For DC Reference Channel) and get Result
Improved Calibration Algorithm Block Diagram RxVGA2 DC Offset Calibration Procedure Perform DC Calibration Procedure in RxVGA2SPI with ADDR:= 3 (For DC Reference Channel) and get Result
Perform DC Calibration Procedure in RxVGA2SPI with ADDR:= 1 (For DC Reference Channel) and get Result
Save TopSPI::CLK_EN Register
TopSPI::CLK_EN[4] :=1 Result == TRUE?
NO
Result == TRUE?
NO
YES
1
YES
1
RxVGA2::VGA2GAIN::=01010
Perform DC Calibration Procedure in RxVGA2SPI with ADDR:= 0 (For DC Reference Channel) and get Result
Result == TRUE?
YES
RxVGA2::DECODE := 1 Set to Direct Control Signals
Perform DC Calibration Procedure in RxVGA2SPI with ADDR:= 4 (For DC Reference Channel) and get Result
Perform DC Calibration Procedure in RxVGA2SPI with ADDR:= 2 (For DC Reference Channel) and get Result
NO Result == TRUE?
NO
YES
1
1
RxVGA2:: VGA2GAINB:=0110, VGA2GAINA:=0.
RxVGA2:: VGA2GAINB:=0, VGA2GAINA:=0110.
Result == TRUE?
NO
YES
1
RxVGA2::DECODE := 0 Set to Decode Control Signals
1
Restore TopSPI::CLK_EN Register
END
* Yellow blocks indicates the calibration algorithm modifications.
New RXVGA2 calibration algorithm improved calibration stability. Calibration values vary ~ ±2 values over 100 iterations. DC offset level variation reduced using new calibration method. The residual DC offset has to be removed by implementing averaging filter in baseband/FPGA.
Appendix: Correcting RX I and Q DC Levels Software in the receiver baseband is required to calibrate the DC level on the I and Q channel. The process of applying DC level adjustment to the I & Q channel is an optional requirement for fine tuning purposes only. The methodology of correcting the DC levels is shown in the diagram below.
Default RxVGA2 DC offset calibration method gives unstable calibration results. ⢠The noise, which is introduced in every VGA2 gain stage (Stage A and Stage ...
25 dB. RxPLL frequency 2137 MHz. TxLPF. 5 MHz. Active LNA. LNA2. RxVGA2. 30 dB. RxVGA1. 120. Internal RF Loopback to LNA2 path. Digital IQ interface running at. 30.72 MHz. 1MHz CW signal is generated by. DIO card. Data fed to Tx DAC's. Tx and Rx I/Q
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