Low power 10-bit SAR ADC for 40MSPS sampling rate Sainath V1, Deepak Malani Indian Institute of Science, Bangalore 1

[email protected]

Abstract- This paper proposes a low power successive approximation ADC using split capacitor array. The ADC with a resolution of 10bits and high sampling rate of 40MSPS was designed and verified by SPICE simulation. The ADC achieved sampling rate of 40MSPS with power consumption of 850uW. I. INTRODUCTION Low power ADCs are useful in applications like wireless sensor networks [6], wireless receivers [1]. Compared to flash and pipeline types, SAR ADC offers low complexity low power solution for such applications, since the comparator and the SAR logic are only power hungry blocks in this type of converter. There is a scope of implementing time-interleaved architecture to achieve higher sampling rate. Also, the offset caused by comparator does not affect the linearity of overall ADC. Section II explains the architecture of SAR. Section III explains the design of major components of ADC. Section IV presents the simulation results. II. SAR ARCHITECTURE SAR circuit consists of only three major blocks: Comparator, SAR Control Logic and digital-to-analog converter (DAC) as shown in Fig.1. Start and sample signals are given from the external block to sample the input and start the conversion.

capacitance value of 50fF, the minimum feature size of current foundry processes. The penalty paid by using split capacitor of value that of unit capacitor is reduction of number of DAC conversion levels by one to 1023 levels. Also to avoid mismatch (3 sigma process variation) among capacitors while fabrication, to affect the non-linearity, we implement MIM capacitors as parallel combination of unit size capacitors (50fF). Total thermal noise due to capacitor is order of few nV and is thus negligible. Hence size of unit capacitor is chosen to be the minimum standard size offered by foundry (with 3sigma variation). Capacitor array acts as both DAC and track and hold circuit.

Fig. 2 Split capacitor array

Choice of switch sizes: The DAC switches were used as shown in Fig. 3. To minimize charge injection errors, the switch sizes were kept just sufficient for the DAC output to settle within less than 0.5 LSB within Tclk/4. PMOS switch size is 13u while that of NMOS is 6.5u. The sizes of pass transistor used for input sampling are same as that of those connecting to rail voltages.

Fig. 1 Block diagram

III SAR ADC Design A. Charge Redistribution DAC Array SAR ADC requires binary weighted DAC circuit. For 10-bit DAC the size of MSB capacitor is very large, which results in higher power consumption of the DAC unit. This can be reduced by using split capacitor array: MSB part and LSB part connected by split capacitor as shown in Fig.2. We have implemented DAC using MIM capacitors with unit

Fig. 3 DAC switches

The operation of DAC is explained in sub-section D.

B. SAR Control Logic The speed of SAR depends significantly on the delay of the control logic circuit. We have implemented two-level registers for implementing the logic [2]. The first level consists of eleven shift registers which ripple a logic high pulse during each clock cycle of a conversion. The output of shift registers clocks the second level of registers, which are referred as switch registers that drive the switches of the DAC. The implementation of these registers was done as proposed by [3]. The output node of switch registers is dynamic in nature.

Fig. 6 Comparator Latch

Fig.4 Two level registers for SAR Logic C. Comparator The comparator gives digital output corresponding to the difference between the input voltage and the fraction of reference voltage. The comparator latch pulls the output voltage to complementary voltage levels by regenerative action. To reduce the input offset of the latch, it is preceded by a moderate gain pre-amplifier, which decreases the input offset by its gain factor. The tail transistor carries constant current of 200uA and its gate voltage is controlled by common mode feedback (cmfb).

D. SAR operation Fig. 7 shows the timing diagram of SAR operation. In the first cycle, all capacitors are grounded to remove the residual charges from previous conversion, controlled by reset pulse. In next cycle, the top plate of MSB capacitor array is connected to Vbias (Vref/2) and bottom plates of all capacitors are connected to input voltage through pass transistor controlled by SAMP signal. In next cycle, top plate of MSB array is left floating, while Vref is connected to the MSB capacitor and all other capacitors are grounded. This makes DAC output equal to (Vbias-Vin + Vref/2). DAC output is fed to one of the differential inputs of preamplifier of the comparator, whose other input is held at Vref/2 (which we have kept same as Vbias). The output of comparator is used by SAR logic to control the DAC switches for next conversion. Total number of cycles required for conversion is n+2 for n-bit ADC.

Fig. 7 Timing Waveform

Fig. 5 Pre-amplifier (differential input)

III. SIMULATION RESULTS

The latch circuit is similar to a sense amplifier consisting of cross-coupled inverter, and the latch input controlled by sense clock. The sense clock was kept to be 1ns delayed with respect to ADC clock. The circuit for dynamic latch is shown in Fig. 6

DAC Settling error was observed to be within 0.5 LSB for the input voltage range 0-1V. However, charge injection at DAC output, resulted in offset error for input voltages that are close to rail voltage. This reduces the dynamic range of the ADC to 1 volt. Input voltage more than 1volt results in low resolution output. The maximum quantization error for our input range 0-1V

was observed to be 0.8LSBs. For input voltage range near mid-voltage, DNL was observed to be 0.9 LSB. The power consumption by all blocks was observed to be 850uW for a sine wave input of 5MHz, sampled at 41.6 MSPS.

[3]

REFERENCES

[5]

[1]

[2]

Sheung Yan Ng et al. “A low-voltage CMOS 5-bit 600 MHz 30mW SAR ADC for UWB wireless Receivers” IEEE Symposium on Circuits and Systems, vol.1,pp. 187- 190, Aug 2005 Carlos A. Vega de la Cruz, “A Switched Opamp Comparator to Improve the Conversion Rate of Low-Power Low-Voltage Successive Approximation ADCs” MS Thesis, University of Puerto Rico, 2005

[4]

[6]

Ginsburg B.P. , Chandrakasan A. P. “Dual Time-Interleaved Successive Approximation Register ADCs for an Ultra-Wideband Receiver” IEEE Journal of Solid State Circuits, vol 42, pp. 247-257, Feb. 2007. McCarroll B.J. Sodini C.G. “A High-Speed CMOS Comparator for Use in an ADC” IEEE Journal of Solid State Circuits, vol 23, pp. 159165, Feb. 1988. Yoshida T et al “A 1V supply successive approximation ADC with rail-to-rail input voltage range” IEEE Intl Symposium on Circuits and Systems, vol. 1. pp. 192-195, May 2005 Naveen V. , Chandrakasan A. P. “An Ultra Low Energy 12-bit RateResolution Scalable SAR ADC for Wireless Sensor Nodes” IEEE Journal of Solid State Circuits, vol 42, No. 6, pp. 1196-1205, June 2007.