Modeling Litho-Constrained Design Layout DAC 2007 Presentation June 6, 2007

Min-Chun Tsai Daniel Zhang Zongwu Tang

Predictable Success

Outline Problem statement & issues of prior-art approaches. Our new approach. Finding the optimal model. Building the right scoring system. Results & Usages. Conclusions.

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Problem statement & Issues of prior-art Problem Statement Need to mitigate lithography issues during design stage. Has to be predictable. Has to be fast with minimum foundry process information.

Issues of prior-art: Post-OPC approach Attempt to simulate post-OPC contour, CD, EPE. Need tremendous amount of foundry information. Foundry needs design data to refine its recipes. Foundry recipes are not matured till late in technology developments. Become very foundry specific and very long runtime.

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Issues of prior-art Issues of prior-art: Pattern-Match A design-rule complementary approach. It applies only to pre-known difficult patterns. Can not be used to find new hot-spots. Needs detailed analyzing and complete description of the pattern to avoid flagging false violations.

Issues of prior-art: Contour-Curve-Fitting Attempt to fit contour using compact modeling. Fit well only in 1D layout, but not in 2D patterns. Hot-spots are caused by 2D pattern interactions.

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Our Approach optical system

P ⊗ ∫ 193nm

OPCed mask

layout / mask

silicon/wafer OOPS !

Shape recovered

P ⊗ ∫

Had a High Resolution Optics, P’

P ' ⊗ ∫ The “conformal” high resolution modeling technique: Transforms to a high resolution model, no need of OPC. While retains hot-spot, litho sensitive information. 5

Finding the optimal high-resolution model Rayleigh criterion:

R = k1 × (λ / NA) Industry experience: k1 RET/OPC Technology Node @ λ

>=0.65 No

0.5 - 0.65 Weak

< 0.5 Strong

500, 350nm 180nm@248 130nm@248 @365 130nm@193 90nm@193 250nm@248

Current 65nm node, k1 of 0.4 was achieved by strong opc.

First principle calculation: a 120nm wavelength stepper could bring k1 back to 0.65. 6

Experimental method to derive the optimal high-resolution model Baseline: extract the intensity profile from a known hot-spot post-OPC pattern.

Optimization: Vary optical parameters. Build models. Apply to original layout. Extract intensity profile. Till ‘best-fit’ profile is found.

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Building the right scoring system Intensity could be a metric for measuring the hot-spot. “Contrast” and its derivates provide a much stronger correlations to litho sensitivity. Contrast = (Imax – Imin) / (Imax + Imin)

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Determine score cut-off threshold Can be determined by known hot-spot patterns, Or through full-chip simulation and exam most sensitive patterns.

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Results & Usages Runtime: 20X speedup against a full-blown mask tapeout flow post-OPC check. Found dozen of violations need to be fixed in a realistic layout. Usage: routing litho-friendly optimization.

12mm2 chip using 10cpus

This method (hrs)

Mask tapeout flow (hrs)

Speed Up

Metal 1

0.83

23.16

27.9

Metal 2

0.58

9.84

17 Green color- original, opc sensitive design. Red color – after optimization.

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Examples of Other Usages Propose usage: gauge chip lithography health. Proposed usage: guide OPC recipe optimization.

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Conclusions We have developed a super fast “conformal” high resolution modeling technique to extract and quantify lithosensitive layout. This technique is a move towards “foundry independent model”. It works directly on design, no need of mask-synthesis steps. It provides a robust and predictable way to enhance litho friendly design. It can be used before technology matures. Yes, No Contours!! 12