JOURNAL OF TELECOMMUNICATIONS, VOLUME 11, ISSUE 2, DECEMBER 2011 49

FPGA based low power reconfigurable modulator with Digital Up Converter for adhoc networks

Latha Sahukar

Dr. M. Madhavi Latha

Associate professor Aurora’s Technological and Research Institute (ATRI) Parvatapur, Uppal, Hyderabad, AP- 500039, INDIA

Professor, HOD ECE Dept, JNTU College of Engineering Hyderabad, AP - 500085, INDIA

Abstract—Modern communication networks are implemented with Adhoc network based topologies. At present the level of re-configurability in adhoc networks is limited up to TCP and IP layers for forming up networks, building up routing functionality etc. The progress made in communication system design by adapting based on channel conditions can give higher bandwidth wireless links with lower power consumption. Implementing such physical layer for mobile adhoc applications can result in more efficient networks. This work presents the reconfigurable modulator enabled with Digital Up Converter (DUC). The results demonstrate the proper functionality on Spartan 3E FPGA, reporting upto 78 MHz maximum clock operation with 80 mW power consumption. Keywords: DDC, DUC, adhoc networks, reconfigurable modulator, digital filters, FPGA, software defined radio, MANET

I.

INTRODUCTION

The upcoming requirements of mobile adhoc networks require re-configurability at various layers. The present adhoc network schemes are designed to configure the nodes at TCP, IP and application layers. In such schemes the nodes configure their network addresses, message formats, security algorithms to suit as per the network in which they are proposed to join[1]. There is tremendous progress in last decade for building the efficient physical layer for networking. The schemes such as OFDMA propose the communication nodes to have capability to configure their parameters as per the channel conditions[2]. Future adhoc network’s nodes must have capabilities to work in tightly occupied and dynamically changing channel conditions. The nodes must also be designed addressing low power and high reliability requirements. In this circumstances the physical layer of the node must be designed with self controlling and reconfigurable communication techniques. The reconfigurable physical layer requires circuits capable of adapting to different modulation schemes, bandwidths, multiplexing schemes and carrier frequencies[4]. The Field Programmable Gate Arrays (FPGAs) are suitable platforms for development of custom wired digital hardware based algorithms/architectures. The conventional usage of FPGAs for commercial wireless equipment design is for prototyping and pre-silicon verification only. In such cases FPGAs are used as evaluation platforms for stable RTL release and fixing all bugs before releasing for ASIC manufacturing.

With the advent of low power techniques and nano meter scale fabrication processes current FPGAs are suitable to be used in place of ASICs. The Xilinx’s Spartan-6 (45 nm) and Virtex-6 (40 nm) FPGAs offer low power and has become the primary factor for selection in wireless devices[6]. The new release of Xilinx’s 7 series FPGAs are built with 28nm processes which even cut down the power consumption. Hence the future wireless nodes can be designed with FPGAs which carry advantages of both re-configurabiltiy and low power consumption. There are few market available proven solutions for realizing the reconfigurable modulator/demodulator blocks along with suitable DUC/DDC to result in complete SDR solutions[3][5]. However such solutions are tailored for military applications, which are not only costly but also has several blocks which are not required for mobile adhoc networks. This papers presents the architecture for reconfigurable modulator suitable for FPGA based mobile adhoc nodes. The section-II explains the proposed architecture of reconfigurable modulator. The section-III explains the power optimized DUC details and its implementation aspects in Xilinx FPGAs. The section-IV provides the simulation, synthesis results and performance analysis.

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JOURNAL OF TELECOMMUNICATIONS, VOLUME 11, ISSUE 2, DECEMBER 2011 50

II.

RECONFIGURABLE MODULATOR

A. High level architecture The proposed architecture is all digital implementation of reconfigurable modulator. The information bits shall be used to generate the digital I & Q symbols for selected modulation scheme. The Numerically controlled oscillator(NCO) is used for COS and SIN carrier generation at the Intermediate Frequency (IF) level. The DUC can translate the signal from IF to band of interest and also ensures the match with output DAC’s suitable sampling rates. The figure.1 shows the high level architecture of the implemented FPGA reconfigurable modulator. Digital source

Symbol mapper Type of modulation

RRC filters

Roll-off factor

Fixed IF

DUC

DAC

Output frequency band

NCO

Modulation controller

Xilinx Chipscope

Fig. 1. High level architecture for reconfigurable modulator \ B. Symbol mapping and symbol shaping filter The symbol mapper block generates the I & Q bits for selected modulation scheme. a programmable serial in parall out shift register is used for generating the parallel words each with log2M bits for selected M-ary modulation scheme.

Fig 3. Impulse response of RRC filter Initially RRC filter is realized in MATLAB and a script is developed to print the values in VHDL ROM format. These coefficients are programmed for implementing FIR filter. Transposed form FIR filter is used to implement RRC filter to achieve higher operating clock speeds. The figure 4 shows the architecture of transposed form of FIR filter. Generic VHDL coding modules are developed such that the code shall remain same for implementing filter of any size. Only the filter coefficients array in package need to be updated. The input and output bit sizes also can be changed by directly modifying the constants in package.

Fig 2. Symbol mapper entity view The fig 2., Shows the top level entity view of symbol mapper block. Depending on the modulation type selected symbol mapping is performed. The I and Q are set to different amplitude values in 2s complement number representation. The symbol shaping is achieved by realizing the Root Raised Cosine (RRC) filter with 4 sets of coefficients for different roll-off factors. The figure.3, shows the impulse response of RRC filter for rolloff factor of 0.9.

Fig 4. Transposed form FIR filter architecture C. Complex NCO and Multipliers The complex NCO generates COS and SIN carrier signals. In the design they are fixed at specific value. Since the sample rate and the frequency are fixed, this block is optimized by implementing the ROM with numerical period of the COS and SIN sequences. This approach saves FPGA area in comparison with implementing full NCO.

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JOURNAL OF TELECOMMUNICATIONS, VOLUME 11, ISSUE 2, DECEMBER 2011 51

The generated COS and SIN are multiplied with the RRC filter outputs. The resulting signal is the modulated signal with carrier frequency as that of NCO.

clk2

D. Modulation controller The modulation controller configures the blocks as per the modulation scheme that is selected. In current implementation 4 types of modulation schemes are selected. They are BPSK, QPSK, OQPSK and pi/4 QPSK. Modulation controller also selects the required filter coefficients from the ROM to realize the RRC filter with selected roll off factor.

Mod-4 counter

clk2

clk2 = 4 X clk1 Fig 5. Area optimized DUC architecture

The modulation controllers also adjusts the frequency tuning command for the digital up converter. External modules shall only communicate to modulation controller to configure the parameters. E. Chipscope The Xilinx Chipscope is instantiated in the design to observe the output at various stages, while the logic is running in FPGA. The Chipscope ILA is used to observe the output and validate the results.

III.

DIGITAL UP CONVERTER WITH POLYPHASE DESIGN

The digital up converter stage consists of complex NCO for spectrum shifting to the required band of interest and also increase the sampling rate to make it compatible with external DAC. The complex NCO is generated with Xilinx DDS core with 28 bit phase increment word. At the highest sampling rate that is selected of 100 MHz the 28 bit phase increment word can give 0.37 Hz resolution in frequency tuning. The DUC consists of interpolator followed by anti-imaging filter. For example a DUC with interpolation factor M introduces (M-1) zeros in between two successive samples coming at the input side. As a result the output sample rate is M times as that of input sample rate. Normal implementation of anti-imaging filter becomes inefficient as the multiplications with zeros doesn’t contribute to output but consume FPGA cells and power. An area efficient architecture is realized for anti-imaging filter which is conceptually reverse of polyphase filter in DDC. The figure 5 shows the implementation of such architecture for 8 tap anti-imaging filter and for interpolation factor of 4.

clk1 C7 C6 C5 C4

The architecture proposed above is based on the principle of avoiding zero multipliers and adders adding such zero multiplied outputs. That is only the multiplications which are with non-zero input sample values are computed. The clk1 is the input sample rate and clk2 is the output sample rate. It is to be noted that the input register chain is driven with clk1 and other registers and Mod-4 counter is driven with clk2. Since the data is crossing from one clock domain to other clock domain directly both the clock signals must be synchronized. Xilinx DCM_SP is used for realizing the clock generation logic. The clk1 is input to the DCM and output CLK_FX with multiply factor of M (4 in above example) is used. Since the clk2 is high frequency clock the multipliers are implemented with pipelining option. This effects only the latency but throughput is not affected. The Mod-4 counter running at clk2 is used to select the multiplexer output. This ensures in one clock period of clk1, all the possible coefficients at multiplier 1 shall be multiplied with the corresponding input. It can be observed that this implementation directly reduces the multipliers and adders by factor of M. This implementation reduces the area and power requirements for realizing DUC. In complete transmitter design the FPGA output must drive the DAC. In such scenario the DUC is also used to match the DAC’s suitable sampling rate.

IV.

RESULTS

In this section the simulation and chipscope results are presented. The Modelsim 6.2g is used for functional simulation. Figure 6, shows the simulation results.

C3 C2 C1 C0

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JOURNAL OF TELECOMMUNICATIONS, VOLUME 11, ISSUE 2, DECEMBER 2011 52

The synthesis report for the whole project is given below. The timing summary shows that the design can run at maximum 78 MHz on Spartan 3E FPGA.

Fig 6. Simulation results – symbol generation and RRC filtering

Fig 7. Simulation results – Complex NCO Xilinx Chipscope is used for accessing the waveforms while the logic is running in FPGA. The Xilinx’s Spartan 3E starter kit with XC3S500E FPGA is used for verifying the design. The Figure 8 shows the chipscope verified results.

The design is also analyzed with Xpower tool for power estimation. The Xpower tool shows 80 mW power consumption including both static and dynamic power components. It is also to be noted that this power analysis is on Spartan 3E FPGA. Hence the power consumption can be expected to be very low when realized on Xilinx’s 7 series FPGAs. Conclusions and future scope The presented work realizes FPGA based reconfigurable architecture with DUC addressing the low power and reconfigurability requirements. The simulation and chipscope results are verified for 4 different modulation schemes. Using Xilinx tools area and power requirements are estimated. The suitability of the proposed architecture for future mobile adhoc networks is studied.

Fig 8. Chipscope verified results

The work is aimed to be continued in the direction of studying and realizing suitable architectures for reconfigurable receiver modules for mobile adhoc networks.

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JOURNAL OF TELECOMMUNICATIONS, VOLUME 11, ISSUE 2, DECEMBER 2011 53

ACKNOWLEDGMENT

[2]

The Authors acknowledge the support given by ECE dept of ATRI college, Hyderabad, for providing the FPGA development tools and boards. The authors also would like to acknowledge the support given by JNTU ECE dept for regular review and suggestions on the presented work.

[3] [4]

REFERENCES

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[1]

F. Jondral, "Parameterization-a technique for SDR implementation," In W. Tuttlebee (ed.), Sofware Defned Radio Enabling Technologies (pp. 233-256) Wiley , 2002. Wideband Digital down converter IP NSS Communications. Indranil Hatai and Indrajit Chakrabarti, “Parameter Controlled Reconfgurable Baseband Modulator for SDR Architecture” 201O 2nd International Conference on Mechanical and Electronics Engineering (ICMEE 2010) Pentek DDC in FPGA-http://www.pentek.com/tutorials/17_3/DDCs.cfm Luis G. Barbero and John S. ThompsonM “FPGAs Enable NextGeneration Multiple-Antenna Wireless Communications’

Z. Zhang, “Routing in Intermittently Connected Mobile Ad Hoc Networks and Delay Tolerant Networks: Overview and Challenges” IEEE Communications Surveys and Tutorials. January 2006 JNTUH FFCs; Governing Body Member of several JNTUH affiliated

Authors

colleges. She is an expert member of selection committee of APPSC, ICFAI University and other affiliated colleges, Ph. D adjudicator for Anna

S. Latha

University, Satyabhama Deemed University and Satya Sai Deemed

She has completed her B.Tech in the year 2001 from Gokaraju Rangaraju

University. She was an expert member of various conferences viz. SPPRA

Institute of Engineering and Technology Hyderabad, M.Tech in the year

– 2009, Austria, ICRSPS-2008, AP, Board of Studies member of JNTUH,

2007 from JNTUH. She is currently working as Associate Professor in

KLU and Academic council member of KLU. She is the key person in

Aurora’s Technological Research Institute, Hyderabad. She has a total

establishing the MOU with Cadence Design Systems, Mentor Graphics,

working experience of 10years (Teaching). Her research area is in the field

Bangalore, brought complete suite of Cadence Tools (for 10 users, worth of

of Software Defined Radios and Signal Processing.

Rs.10 Lakhs) & Mentor Graphics Tools (for 20 users, worth of Rs. 20 Lakhs) and SEER Akademi as part of activities of CVED. She has visited

Dr. M. Madhavi Latha, Ph. D (JNTU), Professor She obtained B. E (NU) in 1986, M. Tech (JNTU) in 1993 and the first internal Ph. D (JNTU) in 2002. She has more than 3 years of teaching

10 European countries including Sweden as the Coordinator of M. TechDDP program with BTH, Sweden, and Singapore.

experience in C. R. Polytechnic College, 4 years of Industrial experience in ECIL, Power Electronics, Midfield Steels Ltd., 16+ years of teaching experience in JNTUH since 1994, where she is currently working as Professor of ECE & Professor In-Charge of JNTUH Library. She established the first Digital Signal Processing Laboratory under AICTETAPTEC Project & also in support of Texas Instruments, Austin, USA and Analog Devices, USA. She has good rapport with Ni2 Designs, Cadence Design systems, Mentor Graphics, Synopsys Intl., Xilinx, Trident Tech Labs, VEDA IIT, AMD industries and NRSA, CDAC, DLRL and RCI organizations. She established the first Center for Excellence in VLSI & Embedded Systems Design (CVED) in ECE department and is the coordinator of CVED. She published 69 papers in National / International Journals / Conferences held at USA, Austria, Greece, Singapore and IEEE region-9 conference at Russia. She coordinated 20 UGC/JNTUH refresher courses / workshops in VLSI, Signal / Image Processing areas and community services. She held the position of Chairman, Women in Engineering (WIE) society – IEEE Hyderabad section, conducted Women Student Congress-2008 and many other activities and received the appreciation certificate from IEEE, USA. She was the Member, Board of Studies for EIE / BME / ETM /ICE group board, is the member, Board of studies for ECE/ETM groups and proposed MATLAB simulation, DSP laboratory and ECAD & VLSI laboratories & many subjects. She was the member of AICTE Inspection Committee and is one of the Chairman of

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