ISSN 0018-1439, High Energy Chemistry, 2009, Vol. 43, No. 3, pp. 204–212. © Pleiades Publishing, Ltd., 2009. Original Russian Text © D. Shamiryan, V. Paraschiv, W. Boullart, M.R. Baklanov, 2009, published in Khimiya Vysokikh Energii, 2009, Vol. 43, No. 3, pp. 250–258.

PLASMA CHEMISTRY PLENARY REPORTS FROM THE 5th INTERNATIONAL SYMPOSIUM ON THEORETICAL AND APPLIED PLASMA CHEMISTRY (September 3–8, 2008, Ivanovo, Russia)

Plasma Etching: From Micro- to Nanoelectronics D. Shamiryan, V. Paraschiv, W. Boullart, and M. R. Baklanov IMEC, Kapeldreef 75, 3001 Leuven, Belgium e-mail: [email protected] Received October 20, 2008

Abstract—The role of plasma etching in the semiconductor technology upon switching from the microscale to the nanoscale dimensions is discussed. The continuing miniaturization has led to impossibility of simple scaling and further use of the conventional materials of silicon microelectronics. New materials and functional elements of integrated circuits call for revision of the existing plasma etching processes and development of novel processes. This situation brings plasma etching along with photolithography to the forefront of nanoelectronics technology. DOI: 10.1134/S0018143909030084

The permanent miniaturization of functional elements of integrated circuits (ICs) is a driving force of technical progress in microelectronics. Miniaturization follows Moore’s law, which states that the number of transistors on an IC crystal doubles every two years. Particular specifications are defined by the International Technology Roadmap for Semiconductors (ITRS). One the critical processes of the semiconductor technology is the transfer of a design pattern onto an IC crystal. Over a few last decades, miniaturization reduced only to a physical decrease in the size of components; the key role was played by photolithography whose capabilities determined the critical dimension (CD). However, the simple reduction in the dimension does not respond anymore to the ITRS requirements on enhancement of the IC throughput speed. For example, the requirement to decrease the thickness of the gate dielectric led to the situation that leakage currents through a very thin oxide layer brought to naught the efforts to increase the MOS transistor speed. Similarly, a decrease in the dimension of metallization was accompanied by an increase in the resistance and capacitance of interconnections, thereby substantially increasing delays in signal propagation along RC circuits that connect IC components into a single whole. It turned out that such problems could not be resolved by simple scaling and, thus, demanded a search for new materials, architecture solutions, and procedures for design pattern transfer onto a crystal. Plasma etching began to play a key role in all these processes, together with photolithography. Plasma processes are widely used in the semiconductor technology. Versions of this technology include

processes based on the reactions of chemically reactive radicals, as well as processes initiated by intense ion bombardment (e.g., reactive ion etching or chemical sputtering). The former processes, e.g., are important in the cases of deposition of dielectric layers and photoresist removal when the impact of energetic ions is undesirable, whereas the ion-induced processes find wide application in processes of precision pattern transfer. It is these processes that are used for pattern transfer onto an IC crystal and will mainly be the subject matter of this paper [3]. Below, by plasma etching we will largely mean reactive ion etching processes. The main advantage offered by plasma etching as compared to wet etching is its high anisotropy, namely, i.e., the ability to provide a high vertical etching rate (in the direction normal to the substrate) at a practically complete absence of lateral etching (in the direction parallel to the substrate). The high anisotropy of plasma etching makes it possible to fabricate structures of a submicronic size. Over a few decades, plasma etching in the semiconductor technology reduced to the etching of a limited number of materials: polycrystalline silicon (polysilicon) as a gate, silicon dioxide as a dielectric, and aluminum as a metallization material. The etching mechanisms are well documented [4] and the optimization problem of etching processes mainly reduces to tuning the etching recipes: enhancement of the etch rate homogeneity, an increase in selectivity, improvement in reproducibility of results, etc. However, the simple reduction in the dimension lately failed to meet the demand of increase in the throughput speed, since the classical materials and tran-

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(b)

Si

Si

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Metal gate (≈10 nm) SiO2

High-k (1–3 nm)

Si

Si

Fig. 1. Sketch of a gate block (a) in the classical version and (b) with the use of a metal gate and a high-k dielectric.

sistor fabrication schemes reached their limit. As a result of further miniaturization, new materials have appeared in the semiconductor technology, thereby greatly complicating the plasma etching processes at practically all IC fabrication steps. ETCHING OF NEW MATERIALS Silicon and its compounds (dioxide SiO2 and nitride Si3N4) have been the base material of microelectronics for years. Silicon dioxide has a number of advantages: good dielectric properties, an almost ideal interface with silicon, and the ease of processing. However, the universality of SiO2 turned from its merit to demerit: different application areas of dielectrics demanded different dielectric properties. For example, an increased relative dielectric permittivity is required for gate dielectrics, whereas a low relative permittivity k (k = ε/ε0, where ε0 is the dielectric permittivity of vacuum) is preferred for dielectrics designed for insulation of interconnections in devices. As a result, two new classes of dielectrics, high-k [5] and low-k dielectrics, have appeared [6]. Since the relative permittivity of SiO2 (k = 4) is a reference standard, a dielectric with k < 4 is classified as a low-k dielectric and that with k > 4 is grouped with high-k dielectrics. Hafnium dioxide HfO2 is most frequently used as a high-k dielectric; however, other metal oxides, such as ZrO2, TiO2, Ta2O5, Al2O3, Sc2O3, Dy2O3 can also be used, as well as the silicates of these metals. Low-k dielectrics can be organic polymers, as their permittivity is small owing to a low polarizability of chemical bonds, or the so-called silicon oxycarbides SiOCH, which are the silicon dioxide matrix in which a portion of oxygen atoms are replaced with CH3 groups. For a further decrease in the permittivity, these materials are made porous. HIGH ENERGY CHEMISTRY

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Polysilicon as a gate material began to be replaced with the so-called metal gate electrodes, which are free of an unfavorable property inherent in polysilicon, such as depletion of the layer adjacent to a dielectric because of an insufficiently high concentration of charge carriers. In addition, the problem of diffusion of dopants from polysilicon is eliminated. As metal gates, metals (e.g. W, Mo, Ru), their oxides (MoO2, RuO2), and nitrides (TiN, TaN, HfN, etc.) are used. A typical scheme of the field-effect transistor gate is presented in Fig. 1. A thin metal layer is inserted between the silicon gate and the dielectric. Such a scheme makes it possible to minimize the effect of new materials on the established fabrication process: photolithography is performed on silicon, and gate etching combines the etching of the conventional polysilicon gate with the necessity of etching of the thin metal layer only at the end of the process. The introduction of new materials in many cases required a change in the chemical composition of plasma used for etching. Frequently, changes involved the recipes of etching of classical materials, e.g., silicon. GATE ETCHING For years, plasmas containing Cl2, HBr, CF4, and O2 were used to etch polysilicon gates. The chemical nature of these gases ensured passivation on the gate walls from 8 nm at the top to 2 nm at the bottom. At gate dimensions approaching 10 nm, such passivation became unacceptable, and the chemical composition of plasma for silicon gate etching was changed for CH2F2/CF4 or CH2F2/SF6/N2. Using the competing process of polymer film deposition from a fluorohydrocarbon gas (CH2F2) and etching (SF6 or CF4), it is possible to achieve homogeneous passivation of gate walls,

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10.7 nm

791.68 nm 13.87 nm

500 nm Fig. 2. Etch profiles of (a) a polysilicon gate of 10 nm thickness and (b) a polysilicon structure with an aspect ratio of 1 : 40.

thereby allowing vertical polysilicon etching profiles to be obtained. These possibilities are shown in Fig. 2, which depicts the cross sections of a gate structure of 10 nm length and a silicon structure with an aspect ratio of 1: 40. Because of a great variety of materials for metal gates, it is impossible to propose a universal plasma etching recipe. Most metals form volatile chlorides (e.g., TiCl4, TaCl5); fluorides can be both more volatile (WF6, TaF5) and less volatile (TiF4) than chlorides. Group VIIIB transition metals do not form volatile halides, as well as Group IB and IIB metals, and are generally not used as metal gates because of complexity of plasma etching. The exception is ruthenium, which forms the volatile tetroxide RuO4; thus, ruthenium gate can be etched in oxygen plasma. There is a great number of publications concerning the plasma etching of metal gates, and even a short review of their results goes beyond the scope of this paper; therefore we will dwell on the most general problem, the simultaneous etching of two complementary metal gates. One of the problems with metal gates is the necessity of equalizing the Fermi level of the gate with the top edge of the valence band of the p-channel transistor or the bottom of the conduction band of the n-channel transistor [8]. In silicon gates, such leveling was achieved by doping the gate with an appropriate dopant. In the case of metal gates, it is necessary to use metals with different work functions for n-MOS and p-MOS transistors (~4 and 5 eV, respectively). The scheme of fabrication of a complementary set of transistors with different gate materials is given in Fig. 3. It is easy to see that, at the last step of fabrication, it is necessary to perform simultaneous etching of two different metals, which is a difficult task in view of the tight requirements on the geometric similarity of n- and

p-channel transistors. In more sophisticated cases, transistors can have different dielectrics along with different gate materials. REMOVAL OF HIGH-k DIELECTRICS After gate etching, it is necessary to remove the high-k dielectric from the silicon substrate. This can be done with the use of either wet etching or plasma etching. Wet etching makes it possible to achieve a high substrate selectivity; however, the process results in gate undercut by virtue of its isotropy. In addition, wet etching is responsive to the crystallinity of a high-k dielectric: frequently, a dielectric is nonetchable unless it occurs in the amorphous state. Plasma etching makes it possible to achieve a high degree of anisotropy, but it has a serious limitation associated with the volatility of the products. In addition, it is more difficult to observe the requirements of substrate selectivity upon plasma etching. As mentioned above, high-k dielectrics are transition metal oxides, of which hafnium dioxide HfO2 is the most popular. The first attempts to etch HfO2 were made with the use of fluorinated plasma. It was found that fluorine reacts with hafnium oxide, but the etch rate was unacceptably low because of a low volatility of hafnium tetrafluoride [10, 11]; in addition, the HfO2 surface after etching was coated with various hafnium fluorides [12, 13]. Silicon is also known for its high etching rate in fluorinated-gas plasmas; therefore, it was impossible to reach a high substrate selectivity. In the case of Cl2 plasma, the etching products are sufficiently volatile; however, the reaction HfO2 + 6Cl HfCl4 + 2ClO (–264 kJ/mol) spontaneously does not occur, since the Hf–O bond (801 ± 13.4 kJ/mol) is stronger than the Hf–Cl bond HIGH ENERGY CHEMISTRY

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(b) Metal gate B (≈10 nm)

(‡) Metal gate Ä (≈10 nm) High-k (1–3 nm)

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Ä Si

Å

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-MOS

Fig. 3. Scheme of transistor fabrication with different gate materials: (a) after deposition of metal A and its removal from the p-region, (b) after the deposition of metal B, (c) after silicon deposition, and (d) after gate etching and mask stripping.

(497.2 kJ/mol) [14]. As a result, the etching rate is low [15, 16], whereas the etching rate of silicon in a chlorine plasma is quite high and the selectivity turns out to be unsatisfactory as in the case of fluorinated plasma. Currently, the most appropriate process is HfO2 etching in boron trichloride (BCl3) plasma. The specific feature of the HfO2 reaction with BCl3 is that the boron can reduce hafnium dioxide, thereby lowering the energy barrier required for the formation of the final products of the reaction: 3HfCl4 + 2(BOCl)3 (–62.7 kJ/mol), 3HfO2 + 6BCl3 since the B–O bond (808 kJ/mol) is stronger than the Hf–O bond and (BOCl)3 is a stable volatile compound with a high negative enthalpy of formation (−1630.2 kJ/mol). The rate of HfO2 etching in BCl3 plasma is acceptable (tens of nanometer per minute) [15, 17]. In addition, the silicon etching rate is substantially lower than that in Cl2 plasma because of the formation of a passivating boron-containing film on the silicon surface [18, 19], which allows a satisfactory substrate selectivity to be achieved. ETCHING OF LOW-k DIELECTRICS As has been noted above, the requirements to reduce the resistance and capacitance of interconnections between transistor led to the replacement of aluminum and silicon dioxide with copper and low-k dielectrics, respectively. There are two possible ways to lower the dielectric permittivity of a material, to decrease the polarizability of molecules and to reduce the density of HIGH ENERGY CHEMISTRY

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the dielectric material (by imparting porosity). The most popular low-k dielectrics are manufactured from silicon dioxide in which some Si–O bonds are replaced with Si–CH3 bonds. A bond of this type, first, reduces the bulk polarizability of the material and, second, imparts hydrophobic properties to the dielectric. Since water has a relative permittivity of 80, hydrophobicity is especially important for porous dielectrics. Inasmuch as copper is highly resistant to plasma etching, the only possibility to accomplish copper metallization is the etching of trenches in a low-k dielectric followed by their filling with copper. Excess copper is removed by chemical-mechanical polish, making plasma etching of copper unnecessary. A simplified metallization scheme is sketched in Fig. 4. The main problem in etching of low-k materials is how to retain their dielectric properties. As a result of plasma treatment, a dielectric can be damaged and will become unsuitable for further use. The most harmful effect is produced by oxygen plasma, as oxygen radicals easily break the Si–CH3 bond, replacing it with the Si–O bond. As a result, the low-k dielectric turns into a porous hydrophilic material with a high permittivity. The higher the porosity of a low-k dielectric, the greater the extent of substitution of oxygen for carbon [20]. Since oxygen plasma is widely used for photoresist (organic polymer) removal, it is necessary to find new solutions that will preserve the chemical structure of low-k dielectrics. This can be achieved with the use of either hydrogen plasma for photoresist removal or an additional hard (usually, metal) mask. Hydrogen atoms can remove a photoresist under certain conditions with-

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(b) Diffusion barrier

(c)

Mask

Cu

Cu

Substrat

Substrat

Low-k

Substrate

Fig. 4. Simplified scheme of copper metallization: (a) after deposition of a low-k dielectric and masking, (b) after etching of the low-k dielectric and barrier and copper coating, and (c) after chemical-mechanical polishing of copper.

out affecting the Si–CH3 bond [21]. When an extra mask is used, it is etched first, then the photoresist is stripped, and the low-k dielectric [22] is finally etched. Thus, at the end of etching, the low-k dielectric is not exposed to the photoresist-stripping plasma. ETCHING OF NEW FUNCTIONAL ELEMENTS Along with the use of new materials, one of the ways to continue miniaturization is the application of new technologies to fabrication of semiconductor devices or the use of new functional elements. New techniques can include double exposure, which makes it possible to substantially enhance the feature density in photolithography. New functional elements include nonplanar mutltigate transistors (finFET), strainedchannel transistors, 3D packages (through-silicon vias), etc. Plasma etching plays a key role in the overwhelming majority of these approaches. DOUBLE EXPOSURE Double exposure makes it possible to extend the capabilities of photolithography with the use of plasma etching. A simplified scheme of double exposure for patterning gates and trenches is shown in Figs. 5 and 6, respectively. Assume that it is possible by means of photolithography to create a pattern with a critical line dimension of 60 nm and a minimal distance between the lines of 60 nm as well, i.e., the pitch is 120 nm. After patterning, the line size is changed by plasma etching. When narrow lines are required, the linewidth is reduced with the use of the so-called trimming resist—isotropic etching of the resist [23] (Fig. 5b). If it is necessary to fabricate narrow trenches, isotropic deposition of a polymer film immediately in the etching chamber is practiced; as a result, the resist lines become wider and the spacewidth becomes smaller (Fig. 6b). By trimming, the line size can be decreased to 30 nm (or deposition makes it possible to shorten the spacewidth to 30 nm). Note that the

periodicity of the pattern remained unchanged, 120 nm, with a change in the critical dimension. Thus, if the line size decreases to 30 nm, the distance between the lines increases to 90 nm. After changing the critical dimension, hard-mask etching and resist removal are carried out. Then, the second exposure with a line shift by 60 nm is performed and the process of alteration of the critical dimension is repeated. As a result, a pattern with a pitch of 60 nm can be obtained: 30 nm linewidth and 30 nm spacewidth. Thus plasma etching enhances the resolution by a factor of 2. The key points of double exposure in relation to plasma etching are the homogeneity of change in the critical dimensions (trimming of polymer deposition) and the choice of hard-mask material. SPECIFICS OF ETCHING OF MULTIGATE (finFET) TRANSISTORS In view of a wide variety of functional elements used to solve the linear scaling problems, let us limit ourselves to consideration of the quite popular example of tri-gate transistor. Unlike the classical planar fieldeffect transistor in which the channel is arranged in the substrate plane and the gate is created on one side of the channel, the channel in the 3D transistor is vertical (perpendicular to the substrate plane) and the gate is built on both sides of the vertical channel (Fig. 7). The gate material is also applied on the top of the channel, connecting the gates with each other. This configuration makes it possible to circumvent the short-channel effects at a channel length less than 20 nm [24]. CHANNEL AND GATE PATTERNING From the standpoint of plasma etching, channel fabrication is not complicated and reduces to the use of trimming for decreasing the linewidth to 15–20 nm. The most difficult operation is gate etching, since the difference in height between the channel and the substrate is usually 60–70 nm. In the case of this configuration, the thickness of the gate material near the chanHIGH ENERGY CHEMISTRY

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(b) 30 nm

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(d)

(e)

60 nm 60 nm

30 nm

(f) 30 nm 30 nm

PR

PR

PR

Si

Si

Substrate

Substrate

Substrate

Fig. 5. Simplified scheme of double exposure for the case of line (gate) fabrication: (a) after the first exposure, (b) after a decrease in the critical line dimension by plasma trimming, (c) after etching of the hard mask, (d) after the second exposure, (e) after the second decrease in the critical dimension, and (f) after gate etching and photoresist (PR) stripping.

nel can be substantially greater than that over the channel (Fig. 8b), whereas the maximal topography in the case of etching of the classical planar gate is determined by the difference in height between the isolator and the substrate and usually does not exceed 10–15 nm (Fig. 8a). On one hand, a large difference in thickness of the material subjected to etching leads to the situation that the horizontal channel and drain/source surfaces are exposed to the action of plasma long ahead the removal of the whole amount of the gate material. This imposes strict limitations on the selectivity of the etching process. On the other hand, the formation of the gate on the side walls of the channel starts at the end point of etching the gate off the horizontal surfaces. Thus, a gateforming plasma must meet at least two requirements, (1) to provide for a preset gate profile and (2) to ensure both channel and source/drain selectivity. In the case of etching of the classical 2D transistor, there is no problem of this sort, since the specified profile is provided by plasma before reaching the surface and a highly selective plasma is used for the removal of a few residual nanometers when the requirements on the profile are not very strict. Modern multigate transistors are used in combination with metal gates and high-k dielectrics. Although the optimization of etching processes becomes rather HIGH ENERGY CHEMISTRY

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difficult in such cases, it is nonetheless feasible [25, 26]. The results of gate plasma etching for the case of 3D transistor with a metal gate (TiN of 10 nm thickness) and a high-k dielectric (hafnium silicate of 2 nm thickness) are presented in Fig. 9. CONCLUSIONS The miniaturization of components of integrated circuits has brought about the appearance of new materials, flowcharts, and functional elements in the semiconductor technology. After switching from the microto the nanoscale (less than 100 nm) dimensions, the classical microelectronics materials, such as silicon and silicon dioxide, reached the limit of their application. Silicon gates are replaced with metal gates, silicon dioxide is replaced with dielectrics having a higher or a lower permittivity, and copper becomes a substitute for aluminum in metallization. In addition to the use of new materials, new functional elements, such as finFET transistors, strained-channel transistors, and 3D integrated circuits (through-silicon vias) are introduced. The capabilities of photolithography are extended by the double exposure technique. These innovations demand novel plasma processes. Thus, plasma etching, which has been considered an

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Fig. 6. Simplified scheme of double exposure for the case of trench fabrication in a low-k dielectric: (a) after the first exposure, (b) after a decrease in the critical trench dimension by plasma deposition of polymer film, (c) after etching of the hard mask (HM), (d) after the second exposure, (e) after the second decrease in the critical dimension, and (f) after HM etching and photoresist stripping. The next step if the etching of the low-k dielectric.

ain Dr

Dr

ain

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Gate

Fig. 7. Sketch of a finFET transistor. The gates are connected with each other from the top (not shown). HIGH ENERGY CHEMISTRY

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Fig. 8. Sketch of (a) a classical planar transistor and (b) 3D transistor. Situation before etching.

30

Source

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ain

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Fig. 9. SEM (scanning electron microscope) image of the 3D (finFET) transistor after etching.

auxiliary process for years, becomes a determining step in the semiconductor technology. 9.

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10.

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