A NEW FLEXIBLE METHOD FOR RE-RUNNING REGIONAL OPC TO MEET THE ECO REQUIREMENTS Yufu Zhang, Hongbo Zhang, Zheng Shi Institute of VLSI Design, Zhejiang University, Hangzhou, 310027, China Email: {zhangyufu, zhanghb, shiz}@vlsi.zju.edu.cn Abstract- For emerging deep-subwavelength lithography technologies (65 nm and following) the computation cost and complexities of the conventional Resolution Enhancement Technologies (RET) such as Optical Proximity Correction (OPC) are themselves becoming bottlenecks in the IC manufacturing flow. This has motivated the recent calls for faster and more flexible solutions. In this paper, we present a new algorithm and a general flow which can be used for implementing regional OPC to meet the increasing needs of Engineering Change Order. Using this new method, approximately 80% run-time is saved and the same accuracy maintained as compared to the conventional OPC methods. Several new concepts such as segmentation matching and smooth transition are brought forward to overcome the ripple effects and stitch the Regional OPC result back into the whole layout. Keywords: RET, OPC, Sub-wavelength Lithography, ECO, Hierarchy, Re-use.

INTRODUCTION The continuous shrink in the critical dimension (CD) of the layout design has spurred the development of RETs including OPC methodologies. Cobb[1] described an effective model-based OPC framework based on greedy strategy in 1996. However, for emerging technologies (65nm and following) the conventional way of full-chip OPC has encountered considerable obstacles. The data volume and computational cost of OPC increase dramatically and will soon become economically unacceptable in IC manufacturing. Besides that, the flexibility of ECO modification is greatly undermined because once the OPC is done the cost of re-running full-chip correction due to only regional changes seems extraordinarily high and over calculated. These new challenges have motivated the recent calls for faster and more flexible solutions. Gupta et al. [3] have advanced a new method called “cellwise OPC”. In this method some “dummy features” are inserted into a cell’s bounding area to simulate its environment. Wang et al. [4] came up with a notion of combining pre-corrected cells with their surrounding regions in the actual layout. Though they made some progresses, the propagating effects in the regional OPC are still a big problem and the accuracy of their results is not fully justified. In this paper, an effective solution called Smooth-Fix Process (SFP) is presented, which extends the conventional flow to implement regional OPC and to meet the ECO needs. The experimental results showed that SFP achieved approximately 80% run-time saving due to the reduction in total polygon number involved and maintained the equivalent accuracy. Using this new flow, the cost of ECO modifications to a post-OPC design is greatly reduced and a promising way for realizing hierarchical OPC can be explored.

DESIGN TARGET AND WORKING FLOW In the complicated design-to-manufacture flow, there are occasional needs to make certain modifications to the post-OPC layout in order to improve the manufacturability and yield. These increasing ECO needs call for a new flexible solution which should be able to satisfy the following requirements. (a) There should be a general flow which can be inserted into the prevailing OPC method or framework. (b) When re-running correction in the specific

region, the interactions between adjacent features should be well considered and properly handled so that the result can be put back into the original post-OPC layout seamlessly. (c) Redundant calculation should be avoided and the same degree of accuracy should be preserved. To meet the requirements mentioned above, we came up with a new solution called Smooth-Fix Process. The working flow is shown in figure 1.

Figure 1. Working flow

Figure 2. Region specification

After reading in the layout and the recipe, we first identify the hot spots surrounding which different processing regions are defined as in figure 2. Here Environment Region is the outmost part in this process. All the patterns in this region shouldn’t be changed in order to seamlessly stitch the SFP result back into the whole layout. The conventional way of correction should be applied to Regular Region which contains the hot spots or the ECO modifications. Buffer Region is the most important part in SFP which works as the transition area between Environment Region and Regular Region. In the next step we define a new variable--Smooth Factor (SF). In the Buffer Region, SF changes as a linear function (from 0 to 1) of the distance of a segment to its region boundary (figure 3). Each segment’s final position is calculated using this variable according to the following equation (illustrated in figure 4): Final Position = Original Position + Calculated Offset×SF (1)

Figure 3. SF function

Figure 4. Segment offset calculation

By this way, each segment’s relative offset can be controlled to realize a smooth transition between the modified region and its environment (as discussed in section 3). Before this procedure, however, another pretreatment step called “Polygon Comparison” needs to be taken to match the new segmentation in SFP with the previous one in full-chip OPC and prepare for the smooth transition. This step is necessary because without the matched segmentation it would be impossible to find the segment’s original position. However, the “Polygon Comparison” contains too many algorithm details to fit into this paper. It will be presented later in our following paper.

EXPERIMENTS AND RESULTS

The poly layer of a 0.473mm×0.221mm, 90nm process node design is used to test our Smooth-Fix Process. Table 1 shows the parameters of the simulation model. Table 1. Parameters of the simulation model λ

NA

Sigma

Inner-Sigma

Ambit

193nm

0.65

0.73

0.43

1.071μm

We first did a less aggressive conventional OPC on the full-chip layout and then applied a more aggressive one using SFP in the specified critical region. The simulated result (dark area) in figure 5 shows that the different regions in the layout undertook different depth of OPC, thus achieving the smooth transition from Regular to Environment Region. (a)

Figure 5. Refined critical region (top right corner) compared with the other parts of the layout (amplified)

(b)

(c)

(d)

Figure 6. The correction and simulation result before SFP (amplified)

The flexibility of manually modifying the post-OPC layout to meet certain ECO needs is also of great advantage to manufacturing. For example, the hammer head of a line end needs to be prolonged (the shadowed area in figure 6-a) to correct an error found in the post-OPC verification. Yet the simulated contour without re-running OPC is not satisfactory (figure 6-b) and the cost of re-running full-chip OPC is too high. Table 2. Run-time saving in our experiments

Example 1 Example 2

Run-time (full-chip OPC) 59.42min 59.14min

Run-time (SFP) 14.85min 11.76min

Performance Gain 4.00X 5.03X

This is the circumstance where our Smooth-Fix Process fits in. Applying this method only in the modified region, SFP achieved 4X to 5X performance gain (table 2) and equivalent accuracy (shown in figure 6-c, d).

REFERENCES 1. 2. 3.

N. Cobb and A. Zakhor, “A mathematical and CAD framework for proximity correction”, SPIE, Vol.2726, 1996, p.208-222. Puneet Gupta, Fook-Luen Heng and Mark A. Lavin, “Merits of cellwise model-based OPC”, SPIE, Vol 5379, 2004, p.182-189. Xin Wang, Mark Pilloff, Hongbo Tang and Clive Wu, “Exploiting hierarchical structure to enhance cell-based RET with localized OPC reconfiguration”, SPIE, Vol. 5756, 2005, p.361-367.