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Code : 98C52 Register Number

VHDL PROGRAMMING Time: 3 Hours I

(ii)

A is compulsory. Answer any two full.questions from each of the remaining sections, Section

-

SECTION

Fill in the blanks :

5

ik

(ii)

-A

ib

(a)

l.

100

g.

: (i)

IMax. Marks:

lo

Note

co m

'V Semester Diploma Examination, Nov./Dec. 2015

type is used to describe user defined operations.

(v) (b)

ed ia

HDL code.

w

(iii) The only predefined physical data type in VHDL is

The internal details of an entity are specified by an

Explain entity declaration with example.

(a)

.p

SECTION

2.

body.

-

B

Explain structure of VHDL module with an example.

5

Explain the process of simulation in VHDL.

4

Explain configurition declaration and package declaration in vHDL.

6

(a)

Discuss constant, variable and signal type of Data objects.

9

(b)

What are identifiers ? Explain the different types of identifiers with examples.

6

(a)

Write behavioural description of 3-bit binary counter using case statement with logic symbol and truth table. g

w

(b)

w

(c)

w

3.

4.

(b)

Explain a report statement with syntax and

example.

6

ITurn over

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:i , '': i, ., 1 Ah^*t^a'

SECTION-C

:.

i

5. (a)

"(6)"

'

2

,.-

i,,, i

,'.," i i;r '

>i

Explain concuffent sigr,ral asSignment statqment with syntax and

*r

i

2J95'

l;i

'rri '1':r i:i::;r'i

'r'i

example.

:1

6

Wriie the VHDL code with.logic symbol and truth table for half adder using

m

9p€52:..,i

.:

Explain with syntax and example of component declaration and component

(b)

Write the structural description of full adder by generating library for the

.co

6. (a)

6

table.

lo g

component used along with relevant logic diagram and truth

7. (a) Write the switch level description for SR Latch. (b) Write the switch level description for an Inverter.

9 6

ib

:

9

SECTION. D

ik

8. (a) Explain the operator overloading and subprogram overloading. (b) Using procedure, write the VHDL description of Full Adder.

e.

ia w

.

'A' XOR 'B'

(a)

Write VHDL function to calculate

(b)

Write VHDL code for finding the Greatest element of an array using mixed

10.

.p ed

type description.

(a)

What are packages ? Explain package declaration and package body with syntax and

I

List different types of verilog

operatqrs.

w

w

w

I

(b)

example.

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I 7

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