USO0RE41485E
(19) United States (12) Reissued Patent
(10) Patent Number: US (45) Date of Reissued Patent:
Tanaka et a]. (54)
(56)
MULTI-STATE EEPROM HAVING WRITE
References Cited
VERIFY CONTROL CIRCUIT
U.S. PATENT DOCUMENTS
(75) Inventors: Tomoharu Tanaka, Yokohama (JP); Gertj an Hemink, Kawasaki (JP)
4,279,024 A 4,761,764 A
DE JP
(Continued)
5,570,315
Maier & Neustadt, L.L.P.
Issued:
Oct. 29, 1996
Appl. No.: Filed:
08/308,534 Sep. 21, 1994
(57)
Division of application No. 09/134,897, ?led on Aug. 17, 1998.
Sep. 21, 1993
(JP)
........................................... .. 5-234767
Dec. 13, 1993
(JP)
........................................... .. 5311732
(51) Int. Cl.
(58)
includes a plurality of data circuits for temporarily storing data for controlling Write operation states of the plurality of memory cells, a Write circuit for performing a Write opera tion in accordance With the contents of the data circuits
Foreign Application Priority Data
G11C 16/04
ABSTRACT
An EEPROM having a memory cell array in Which electri cally programmable memory cells are arranged in a matrix and each of the memory cells has three storage states,
US. Applications:
(52)
4/1993 5/1983
Primary ExamineriAndrew Q Tran (74) Attorney, Agent, or FirmAOblon, Spivak, McClelland,
Related US. Patent Documents
(64) Patent No.:
Watanabe ............ .. 365/185.21
42 32 025 58-86777
Jun. 13, 2006
Reissue of:
(30)
8/1988
FOREIGN PATENT DOCUMENTS
(21) App1.No.: 11/451,587
(62)
7/1981 Schrenk *
(Continued)
(73) Assignee: Kabushiki Kaisha Toshiba, KaWasaki-shi (JP)
(22) Filed:
RE41,485 E Aug. 10, 2010
(2006.01)
respectively corresponding to the memory cells, a Write verify circuit for con?rming states of the memory cells set upon the Write operation, and a data updating circuit for updating the contents of the data circuits such that a reWrite operation is performed to only a memory cell, in Which data is not suf?ciently Written, on the basis of the contents of the
US. Cl. ........................... .. 365/185.22; 365/185.21;
data circuits and the states of the memory cells set upon the
365/185.24; 365/185.18; 365/185.03; 365/185.17;
Write operation. A Write operation, a Write verify operation,
365/185.12
and a data circuit content updating operation based on the contents of the data circuits are repeatedly performed until the memory cells are set in predetermined Written states.
Field of Classi?cation Search ........... .. 365/185.22,
365/185.03, 185.17, 185.24,185.21, 185.12, 365/185.18
See application ?le for complete search history.
7 Claims, 29 Drawing Sheets
WRITE CONTROL SIGNAL
GENERATION CIRCUIT T WRITE VERIFY GEN
.
DATA UPDATE
LINE
‘0
CELL ARRAY
CONTROL SIGNAL
c T
ROW
C DECODER
C'R U‘
ezusnmou cmcun
DATA WRITE END DETECTION CIRCUIT
C DRIVE 7,1
B11 uNE CONTROL CIRCUIT
1'51": £8111?“ RSION
CIRCUIT
16 Q COLUMN DECODER
I
5
DATA INPUT/ OUTPUT BUFFER
US RE41,485 E Page 2
US. PATENT DOCUMENTS 4,887,242 A
5,168,465 5,172,338 5,218,569 5,321,699 5,394,362 5,521,865 5,652,719 5,781,478 5,920,507
* 12/1989
A A A A A A A A A
12/1992 12/1992 6/1993 6/1994 2/1995 5/1996 7/1997 7/1998 7/1999
5,978,308 A
* 11/1999
6,069,823 A 6,147,911 A
5/1989 10/1989
Hashimoto ........... .. 365/185.29
JP
2_232900
4/1990
JP JP JP JP JP JP JP JP JP
2.260298 359886 3.237692 3.286497 4.88671 4.119594 4_254994 4.507320 516681
10/1990 3/1991 10/1991 12/1991 3/1992 4/1992 9/1992 12/1992 1/1993
Kato ................... .. 365/230.06
5/2000 Takeuchiet a1. 11/2000 Takeuchiet 31.
62-257699
l-23878 1-46949
Harari Mehrotraet 31. Banks Endoh et a1. Banks Ohuchiet 31. Tanakaet a1. Takeuchiet a1. Takeuchiet 31.
FOREIGN PATENT DOCUMENTS JP
JP JP
11/1987
JP
5-144277
6/1993
JP JP JP JP
5.182476 5160199 2007-184102 2007-184103
7/1993 9/1993 7/2007 7/2007
* cited by examiner
US. Patent
Aug. 10, 2010
Sheet 1 0f 29
US RE41,485 E
WRITE CONTROL SIGNAL
‘
GENERATlON cmcun \ 9 q‘ Wm“; VERIFY
gg?gggl?gglsg?aLcun _ DATA UPDATE
MEMORY '0
WORD LINE
CELL ARRAY
Row
QIIDRWE
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CONTROL SIGNAL GENERATION CIRCUIT
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US. Patent
Aug. 10, 2010
Sheet 7 0f 29
( START OF DATA
WRITE OPERATION LOAD DATA
PERFORM VERIFY READ OPERATION
Q'ART OF ADDITIONAL DATA WRITE OPERATION READ
I LOAD DATA
PERFORM VERIFY READ OPERATION
US RE41,485 E
)
US. Patent
2.50
Aug. 10, 2010
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Sheet 9 0f 29
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US RE41,485 E
33
US. Patent
Aug. 10, 2010
Sheet 11 or 29
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US RE41,485 E
US. Patent
Aug. 10, 2010
Sheet 12 or 29
US RE41,485 E
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US. Patent
Aug. 10, 2010
Sheet 15 0f 29
US RE41,485 E
4 PAGE LOGICAL
?
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ADDRESS 0 l 2 —————— --3| 32 —-.—— ---- 53--_-N-3| _______ “N
AREA 1
AREA 2
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22 MEMORY CELLS _.
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US. Patent
Aug. 10, 2010
Sheet 16 0f 29
US RE41,485 E
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US. Patent
Aug. 10, 2010
Sheet 18 0f29
US RE41,485 E
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THE NUMBER OF MEMORY CELLS
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25
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B IT LINE OUTPUT VOLTAGE
