USO0RE41021E
(19) United States (12) Reissued Patent
(10) Patent Number:
Tanaka et a]. (54)
(45) Date of Reissued Patent:
MULTI-STATE EEPROM HAVING
5,168,465 A
12/1992 Harari
5,172,338 A 5,218,569 A
12/1992 Mehrotra et 31 6/1993 Banks
-
-
i *
~
,
GertJan Hem1nk,KaWasak1 (JP) .
.
.
.
.
1ang
5,412,599
Kawasakl'shl (JP)
A
*
7/1997 Tanaka et a1.
5,781,478 A
7/1998 Takeuchi et al.
7/1999 Takeuchi et a1.
(22)
Filed:
6,069,823 A
6,005,815 A
* 12/1999
6,147,911 A
_
DE
42 32 025
4/1993
Primary ExamineriAndrew Q Tran
(74) Attorney, Agent, or FirmAOblon, Spivak, McClelland, Maier & Neustadt LLP
Division of application No. 09/134,897, ?led on Aug. 17,
’
(57)
Foreign Application Priority Data
Sep. 21, 1993 Dec.13,1993
. . . . . . . . . . . . . . . . . . . . . . . . ..
(Commued)
_
1998
ABSTRACT
An EEPROM having a memory cell array in Which electri
(JP) ........................................... .. 5-234767 (JP) ........................................... .. 5311732
Cally Programmable memory Cells are arranged in a matrix and each of the memory Cells has three storage states,
includes a plurality of data circuits for temporarily storing data for controlling Write operation states of the plurality of
Int‘ Cl‘ GH C 16/34 US. Cl-
(200601)
memory cells, a Write circuit for performing a Write opera tion in accordance With the contents of the data circuits
. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
respectively
365/185-18; 365/185-17; 365/185-03; 365/185~12 (58)
Sung
.
U'S' Apphcanons'
(51)
11/2000 Takeuchi et al.
Sep. 21, 1994 _
365/185.14
FOREIGN PATENT DOCUMENTS
Oct. 29, 1996 09/308,534
Filed:
....... ..
Nakano .................... .. 365/201
*
5,570,315
Issued: Appl. No.:
.
5/2000 Takeuchi et al.
Related U_sI Patent Documents
(64) Patent No.:
Daniele et al.
5,652,719 A
5,920,507 A
Reissue of:
5/1995
5/l996 Ohuchiet a1‘
App1_ NO; 11/451,533
365/l85 l9
................... ..
21995 Banks
5,521,865 A
(21)
Jun. 13, 2006
§nd°h et al'
,
5,394,362 A
(73) Ass1gnee: Kabush1luKa1shaT0sh1ba,
(30)
Dec. 1, 2009
WRITE-VERIFY CONTROL CIRCUIT
(75) Inventors: Tomoharu Tanaka, Yokohama (JP);
(62)
US RE41,021 E
Corresponding
to
the
memory
Cells’
a
Write
verify circuit for con?rming states of the memory cells set
Field of Classi?cation Search ........... .. 365/ 185.22,
upon the Write operation, and a data updating circuit for
365/185.03, 185.17, 185.33, 185.12, 185.18, 365/185.21 See application ?le for complete search history.
updating the contents of the data circuits such that a reWrite operation is performed to only a memory cell, in Which data is not suf?ciently Written, on the basis of the contents of the data circuits and the states of the memory cells set upon the
(56)
References Cited
Write operation. A Write operation, a Write verify operation,
US. PATENT DOCUMENTS
and a data circuit content updating operation based on the contents of the data circuits are repeatedly performed until
4,057,788 A
* 11/1977 Sage ................... .. 365/18519
4,279,024 A 5,146,106 A
the memory Cells are Set in Predetennined Written States‘
7/1981 Schrenk *
9/1992 Anderson et a1. ........... .. 327/50
1 Claim, 29 Drawing Sheets
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FOREIGN PATENT DOCUMENTS
JP
4-88671
3/1992
4-119594 4-254994 4-507320 5-6681 5-144277 5-182476 5-60199 2007-184102 2007-184103
4/1992 9/1992 12/1992 1/1993 6/1993 7/1993 9/1993 7/2007 7/2007
JP JP JP JP JP JP JP JP
58-86777 62-257699 1-23878 1-46949 2-232900 2-260298 359886 3437692
5/1983 11/1987 5/1989 10/1989 9/1990 10/1990 3/1991 10/1991
JP JP JP JP JP JP JP JP JP
JP
3-286497
12/1991
* cited by examiner
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US RE41,021 E
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