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The Design of CMOS LNA in 0.1 um technology for the mobile receiver system Hyungkook Joo, Woongjae Han

Abstract— In this paper, a CMOS Low Noise Amplifier (LNA) with operating frequency range from 2.402 GHz to 2.480 GHz is designed for use in the mobile receiver system that recovers 4-GFSK modulated signals. A link budget of this system is calculated and the LNA gain and the noise figure required to achieve an acceptable BER are also determined. The LNA has a gain (S21) of 15.44 dB and a noise figure of 4.38 dB. The Cadence design tool is used to implement the LNA and the results of the simulation is presented in this paper. Index Terms— Low Noise Amplifier, Bluetooth, RF CMOS, Wireless, Personal area network devices(PAN). I. INTRODUCTION The purpose of this project is to design a LNA for use in a personal area network (PAN) receiver. The front end of device receives the signals which is sent from a smart phone. Due to the path losses the receiver receives very low signals. Therefore, the signals must be amplified properly with LNA so that we can achieve an acceptable BER of 10e-9. The link budget analysis is performed along with the system specifications so that the LNA can meet the constrants. Since the LNA which is the first device in the reciever after the antenna feed has significant effects on the system, the LNA is desired to have high gain and low noise figure to satisfy the receiver BER at the date output. Finally, the LNA with prpoer gain and noise figure is designed to be used in the receiver. The Commom-Souce LNA is used because it has good noise performance. Since the impedance matching of LNA does not give the best noise performance we should trade off the noise figure against power transfer. The constraints of LNA design are following: Vdd is 1.8 V; Noise figure may not exceed the ¼ of LNA gain in decibels; Center frequency is 2.441 Ghz; Bandwidth is from 2.402 to 2.480; Input VSWR is 1.5:1; Output VSWR is 2:1; IIP3 should be greater than -1dBm; Q is 6 at 2.441 GHz; The LNA provide enough gain and support the 4-GFSK modulation scheme with a required BER.

This project is submitted on May 2 2014. Hyungkook Joo and Woongjae Han are with the Electrical Engineering Department , University of Southern California, Los Angeles, CA 90007 USA (email: [email protected], [email protected])

TABLE I LINK BUDGET

Parameter Data Output Power Tx Amplifier Gain Feed Loss Antenna Loss Power at Base Station Rain and Environmental Loss Distance Free Space Loss Total Space Loss Rx Input Power Total Receiver Gain Rx Power at Receiver Output Equivalent Noise Factor LNA gain Noise Factor of LNA Noise Figure of LNA Link Margin

Value 0.001 15 3 3 9 15 33 70.56 85.56 -76.56 -22.5 -99.06 161.6321 13.07 2.1232 3.27 2

Units Watts dB dB dB dBm dB m dB dB dBm dB dBm dB dB dB

II. DESIGN AND METHODOLOGY First of all, the necessary LNA gain and noise figure values are required for designing. A Link budget is calculated for getting the necessary values. The Table 1 shows that the link budget of receiver considered with the receiver specifications. Since the receiver BER at the Data output cannot exceed 1e-9, so that Eb/No is set equal to 7dB. From the table 1., it shows that necessary LNA gain to be 13.07dB, and the noise figure to be around 3.27dB for link margin 2dB. Then, in order to design and simulate the LNA, single-ended Inductive source degenerated LNA is chosen. The Inductive Source Degeneration is selected because it is very popular for narrow band design and it also has the advantage of high gain and low noise figure.[3] We designed the LNA with three NMOS transistors of 0.1 um technology. The design of LNA is similar to the Fig. 1. Transistor width is the first parameter to be determined. From small signal analysis, we get the parameter values such as Cgs and Lgs. Once we get every required LNA components value, then compute those values to the Cadence simulator.

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Fig. 1. Inductive Source Degeneration LNA [3] III. SIMULATION AND RESULTS The designed LNA is simulated and each parameters of LNA is plotted below by Cadence. The simulation result of S21, Noise Figure, VSWR, IIP3 parameters are plotted. Table 2 summarizes the performance of the designed LNA.

Fig. 4. VSWR1 Parameter Plot

Fig. 2. S21 Parameter Plot

Fig. 5. VSWR2 Parameter Plot

Fig. 3. Noise Figure Parameter Plot

Fig. 6. IIP3 Parameter Plot

3 ACKNOWLEDGMENT The schematic of designed LNA and test bench is shown below:

The authors are very grateful to Dr. Zahid and Aaron Friesz who gave us an opportunity to design LNA with Cadence simulator. Since both of us are communication background person, we had no experience about circuit design at all. However, thanks to this project the authors learned so much about LNA design. We also would like to show our appreciation to University of Southern California offering the Server and Program to fulfill this project. REFERENCES [1] B. Razavi, “CMOS Technology Characterization for Analog and RF Design,” IEEE Journal of Solid-State Circuits, vol. 34, no. 3, March. 1999. [2] Rashad. M. Ramzan, Tutorial-2, CMOS Low Noise Amplifier Design. [3] S. Jagarapu and R.K. Kavitha, “A 2.4 GHz Low Noise Amplifier in 0.18um CMOS Technology,” International Conference on VLSI, Communication & Instrumentation (ICVCI) , 2011. [4] D. Ho and S. Mirabbasi, “Low-Voltage Low-Power Low-Noise Amplifier for Wireless Sensor Networks,” University of British Columbia, June 2013

Fig. 7. LNA Schematic

Fig. 8. Test bench Schematic TABLE II SIMULATION RESULT

Parameter S21 NF VSWR1 VSWR2 IIP3

Specification

Results

13.07 dB 3.27 dB 1.5:1 2:1 >-1dBm

15.44 dB 4.39 dB 3.17 dB 6.76 dB 25.91dBm

IV. CONCLUSION The LNA designed in this project can be used in personal area network such as Bluetooth in mobile communication system. The LNA is designed with emphasis on gain and noise figure in this project. The system constraints and the simulation results are compared in the Table 2. This LNA is not ideal since there is more room for improvements.