CAD/Graphics’2001 August 22-24, Kunming International Academic Publishers

MODULE PLACEMENT ON ARBITRARILY RECTILINEAR REGIONS USING LESS FLEXIBILITY FIRST PRINCIPLES 1

Dong Sheqin1 Hong Xianlong1 Wu Yuliang2 Xiu Zhong 1 Gu Jun3 Department of Computer Science and Technology, Tsinghua University, Beijing, P.R.China, 100084 Tel:+86-010-62785564 Fax:+86-010-62781489 Email:[email protected] 2 Department of Computer Science and Engineering, The Chinese University of Hong Kong 3 Department of Computer Science, Science & Technology University of Hong Kong

ABSTRACT Module placement in a rectilinear area is one of the most important problems in IC/PCB design. A deterministic algorithm for VLSI block placement in a rectilinear area was developed in this paper through human’s accumulated experience in solving “packing” problem. Rectangle packing problem is just a simplified case of the polygon-shape stone plate packing problem that the ancient masons needed to face. Several “packing” principles derived from the so-called “less flexibility first” experience of the masons. A k-d tree data structure is used for manipulating the packed rectangles under the derived packing principles. Experiment results demonstrate that the algorithm is effective and promising in rectilinear area placement application.

KEYWORDS Placement, Algorithm

VLSI

VLSI Placement, Constraint Physical Design, Deterministic

1. INTRODUCTION In very large scale integrated circuit chip design, it often happens that the locations of some macro cells, such as RAM, ROM, and central processing unit (CPU) core, are fixed a priori and the other components are subject to be placed in the rest of the chip area. Also in printed circuit board (PCB) design, it is common that the exact coordinates of connectors are determined before designing the placement of the other components. These situations were often formulated as a problem called rectangle packing with preplaced rectangles. Generally speaking, it requires some modules are preplaced in advance, and the other modules are requested to be placed without overlap with each other and with these This work is supported by National Science Foundation (No.60076016) and 973 National Key Project (No. G1998030411)

preplaced modules. As a case of preplaced modules placement, when preplaced modules were placed in the corners and central hollow space of the board or chip, this is the case placement in a rectilinear area. Different from the general preplaced module placement, the requirement of the placement in a rectilinear area is that all modules are guaranteed to place in the rectilinear area while the total wire length is optimized as short as possible. It has been proved that the simplest version problem of VLSI Building Block Layout, the rectangle block “packing” problem, is a NP-hard problem. So a preplaced rectangle placement problem is also a NPhard problem. Chi[1] studied a similar problem for standard cell layout, in which all the free modules are restricted to have a regular height. Force directed relaxation method can be easily tailored to handle the obstacles, but the method has inherent drawbacks in the sensitiveness to the initial placement and in the incompleteness of the overlap elimination. Sung-Soo Kim et al [2] proposed a self-organization assisted placement for circuit placement in arbitrarily shaped regions, including two dimensional rectilinear regions. The algorithm is based on a learning algorithm for neural networks. It is not effective for macro cell placement. The most practical way would be to use a stochastic algorithm, such as simulated annealing[3] or genetic algorithm[4], if a proper coding scheme is available. A coding technique for the slicing structure[5] is not useful for rectangle packing with preplaced rectangles since the preplaced modules might be given nonslicibly. For general placements including both slicible and nonslicible cases, many coding schemes are recently proposed, namely sequence pair [6] and bounded sliceline grid(BSG) [7] , O-tree, Corner Block List(CBL)[8]. The first two had been used for preplaced placement. Although these algorithms are efficient in some sense, the difficulty to determine the cooling

schedule for a placement input determines that they are inherent inefficiency. Human has accumulated experience in solving similar packing problem in everyday life. For example, the building block placement problem is just a simplified case of the polygon-shape stone plate packing problem that the masons needed to face in their everyday work. They try to use up the more restricted resource and fulfill the requests with more requirements and tend to leave the more “general” items at the later stage of processing to have a higher chance to find a match. These effective techniques, named as the less flexibility first principles, have survived over generations [9]. We derived some new heuristics from these techniques to cope with the similar problem in VLSI block placement. Experiment results prove that the algorithm based on this quantitative flexibility is both efficient and effective, although it is a deterministic algorithm. The rest of the paper is composed as follows: in Sec. 2 several the less flexibility first principles and their definitions are developed. Sec. 3 describes the algorithm and its implementation. Sec.4 presents our experimental results for MCNC benchmarks. Sec. 5 is the conclusions.

2. THE LESS FLEXIBILITY FIRST PRINCIPLES An experienced professional believes that a packing work inside a working area, such as bounded floor, wall … etc., must have a most “reasonable” priority order. This packing order can maintain the form and shape of the working space as much as possible. It tends to retain the working area “less fragmented”, “without hole” and “in the original form”. One should abide by the primary principle that when a new packing step is taken, the deformation of the working space must keep as minimal as possible. For an empty space in the working area, a rectangle has three choices to pack in it: pack the rectangle in a corner; pack it along a boundary side and pack it in other empty part. Obviously, the deformation to the working space of corner packing is minimal among the three whereas the deformation of side packing is smaller than that of space packing. The latter two will have more chances to cause partitioning of working space and space packing will create “holes” in the work area. To pack the rectangles tighter, one should use up all space in the work area with the rectangles. Intuitively, one would try to use up the more restricted resource and fulfill the requests with more requirements, and tend to leave the more “general” items at the later stage of processing to have a higher chance to find a match. This schedule sequence of packing tasks can be named as “the Less Flexibility First: LFF”

principle. The major objectives of VLSI block placement are chip area minimization and interconnection wire-length minimization. It is clear that VLSI block placement is more complicated than a packing problem. Triggered by “the less flexibility first” principle, for a VLSI block placement problem, we develop its own “the less flexibility first” principles as follows.

(1)Problem Definition A set B={B1, B2, …, Bn} of rectangular blocks lie parallel to the coordinate axes. A set of nets specifying the interconnections between pins of blocks and a set of pads (external pins) are also given. A placement P={(xi , yi )
1 < = i < = n} is an assignment of coordinates to the lower left corners of n rectangular blocks such that there is no two rectangular blocks overlapping. Each Bi is defined by a tuple (hi , wi) , where hi and wi are the height and the width of block Bi, respectively . A preplaced module is a module whose coordinates are specified. A free module is a module whose coordinates are not specified. Set Bp of preplaced modules is given such that no two preplaced modules overlap each other and all of them lie in the first quadrant of the plane. Set F=B-Bp is also given. The area of the smallest rectangle that encloses the placement is called the working area of the placement. The working area lying in the first quadrant and the set Bp form the rectilinear region in which free blocks will be arranged (Fig. 1). The objective of the rectilinear area placement is to find an assignment of set F so that all free blocks are arranged in the rectilinear region and interconnection wire-length between blocks are minimized while satisfying the given constraints, if any.

Fig. 1 The dark preplaced modules form the rectilinear placement region

(2)Flexibility of Placement Flexibility of empty space For a rectangle to be packing, there are three kinds of space in the working area, corner space, side space and central hollow part of the working area. Each of the three has different flexibility. In a working area, if a side of a rectangle is not fixed or bounded by a side of the working area or a side of other rectangles, the rectangle will have a flexibility to move at the direction which is perpendicular to the side and pointing out of the rectangle. For example in Fig. 2(a), the corner packed rectangle, its two sides is bounded by the boundary of the work area, so it cannot move horizontally to the right and cannot move down vertically. But it can move to the left horizontally and move up vertically, it also can move along the joint (up right) direction between the directions pointing to the left horizontally and pointing up vertically. The joint direction of the two perpendicular sides of a rectangle is along the equinoctial line of the right angle formed by the two sides and point out of the rectangle. If a rectangle can move along the directions between two perpendicular directions, we say that the rectangle will have a flexibility to move along the joint direction of the two perpendicular directions. If we define one direction of move flexibility is one freedom, obviously, the corner packed rectangle will have 3 freedoms, a side packed rectangle has 5 freedoms and a rectangle packed at hollow space has total 8 freedoms. This is depicted in Fig. 2. We measure the flexibility of an empty space in the working area by freedoms of a rectangle packed in that space. Definition [Flexibility of empty space: P f ] The flexibility of a corner packing is Pcf = 3/8; The flexibility of a side packing is Psf = 5/8; The flexibility of a hollow space packing is Phf = 8/8 = 1. We have the formula : (1) Pcf < Psf < Phf .

(a)

(b)

Y

X O

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Flexibility of empty space (a)flexibility of corner packing Fig. 2 (b) flexibility of side packing (c) flexibility of hollow space packing (d) local reference frame of a block

By the less flexibility first principle, a reasonable packing order will be: a corner packing Pcf always take precedence of side packing, a side packing always takes precedence of hollow space packing. Flexibility of a rectangle to be packed The rectangles to be packed have different degrees of flexibility depending on their shapes and sizes. It is generally agreed that a rectangle with large size or a rectangle with longer side will have less flexibility. For example, in Fig.3, block B and C have less flexibility than block A. Block B and block C can only be packed in the corresponding place with the same name in the working area, respectively. However, rectangle A has many choices. Definition [Flexibility of a rectangle: Ri f ] Assume Bi is the area of rectangle i, wi is its width and hi is its height, Pa is the area of the working space, W is the width of the working area and H is its height. The flexibility of a rectangle is: Ri f = r1 * (1 – Bi / Pa ) + r2 * ( 1– max( wi , hi )/ max( W, H )); (2) where r1 + r2 = 1 By the less flexibility first principle, a rectangle with less Rif will be packed first, that is to say a rectangle of larger size or a longer rectangle will have priority to be packed. A C

B

B C

Fig.3 Flexibility of rectangle to be packed, a large size of or longer rectangle has less flexibility

Flexibility between two blocks For VLSI block placement, optimization of interconnection wire length among VLSI blocks is very important. It is impossible to calculate the exact wire length at placement stage where detailed routing has not yet been carried out. We estimate the length of each net as one-half of the perimeter of the bounding box of the net. Any two VLSI building blocks may have interconnections between them. Obviously, for a placement, the more number of nets between two blocks, the longer wire length between them, the tighter they must be packed each other. For example, in Fig.4, the number of nets between block A and block C is greater than the number of nets between block A and block B, then block C will be packed first in the place Px or other place such that the total wire length between the two

blocks is smallest. f

Definition [Flexibility between two blocks: Cij ] Assume Wij is the number of all nets between block Bi and block Bj , Wnet is the number of all nets of the placement. The flexibility between two blocks is: (3) Cijf = 1– Wij / Wnet By the less flexibility first principle, a packing step which has less Cijf of two blocks Bi and Bj will take first.

the definition of the flexibility of a rectangle in the last section. 3

B

Px C

A

F ig.4 Flexibility betw een tw o blocks, the num ber of nets b etw een A and C is greater than the num ber of nets betw een A and B , C w ill be packed in the place of Px

3. ALGORITHM AND ITS IMPLEMENTATION (1)Implementation As discussed in the last section, it is reasonable that packed rectangle must occupy at least on empty corner of the current packing configuration. Therefore, there are many candidate corners for a packing step and one corner have two packing orientations for a rectangle. For example, in Fig.5 there are total 7 corners in the configuration, and block B can be packed at any one of them with two possible orientations. That is to say there are 14 packing choices for block B. In the terms of the flexibility definitions discussed above, we define one choice of this kind as a Candidate Corner Packing Step (CCPS). A CCPS can be represented by a six-tuple as < block_id, length, width, orientation, x, y> The block_id is block name, the length and width are values of the longer and shorter sides of the packed block, orientation indicate if the rectangle is placed with its longer side laid horizontally or vertically. (x, y) is the left-lower corner coordinate of the suggested location. Firstly, based on the current packing configuration, a list of all candidates CCPSs for all unpacked blocks are generated. The candidate CCPS list is then sorted in a lexicographical order, where an earlier CCPS possesses a higher priority. The sorting of the list is according to

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F ig . 5

Interconnect betw een tw o blocks

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C an d id a te p ac k in g co rn ers fo r a b lo c k B

In terms of selection among qualified candidate CCPSs, we combine all the strategies shown above. For each of the rectangles to be packed, a set of its feasible CCPSs, based on current packing configuration, are obtained. Then the CCPSs are gathered as a list and sorted as described above. For each of these candidates CCPSs, a “Fitness Value (FV)” will be calculated as follows: Fist, the candidate CCPS is pseudo-packed into the current working space. The term “pseudo” means that it is just a test and the packing process can be reverted. The other left-over rectangles are then pseudopacked with a greedy strategy following the list order until no rectangle can be packed. The strategy is “greedy” in the sense that it tries to pack the rectangles at the front of the list first and to pack as many rectangles as possible following the list order. The FVi of this candidate CCPS i is then calculated as: FVi = 1 * Ap + 2 * Cnet Where the item Ap is the total area of all rectangles had been packed, Cnet is the total number of nets among the block to be packed and the already packed blocks in one corner. 1 and 2 are the weights. The candidate CCPS with the highest fitness value will be selected as the next packing candidate. The process repeats until all rectangles are really packed or the list becomes null while there are still unpacked rectangles. (2) Algorithm A deterministic rectilinear region placement algorithm, named LFF, is derived by using the Less Flexibility First (LFF) principle. The advantage of deterministic algorithm is that its implementation is straightforward and easy to comprehend. Assume that: BBS: Free block set to be packed UBS: Unpacked free block set indexed by I Cpp is the preplaced corner packed block set Opp is the preplaced hollow space packed block set PBS: Packed block set indexed by j including preplaced blocks Ratio: Required ratio of length and width of the placement PL: Current placement configuration AreaN: Sum of net area of all blocks in BBS

Pa : The area of the placement, Alpha = AreaN / Pa Then, we can get the width and length of PL straightforward. Because AreaN is already known, Ratio and Alpha can be given by user. Deterministic algorithm : Rcti_LFF Input: array of blocks with width, height, and pin positions and I/O pad positions and networks and package positions of preplaced modules Output: blocks with position and orientation UBS = BBS Updated the Placement with an estimated blank rectangle with required ratio of length and width; Preplace Cpp and Opp and form the rectilinear region PL while UBS is not empty and there is space for packing in PL for each block i in UBS Based on the current PL , find all overlap-free CCPSs and form a list end for Sort all of the CCPSs in the list in lexicographical Order for each candidate CCPS i in the list Pseudo-pack this CCPS in PL Pseudo-pack all the remaining rectangles in the current CCPSs list and with a greedy approach, until no more CCPS can be packed Calculte: FVi = 1 * Ap + 2 * Cnet Note: Before the test calculation for the next candidate CCPS is tried, the previous pseudopacked CCPSs will be restored.

end for Pick the candidate CCPS with the highest FVi and update PL with really pack the corresponding block according to the CCPS with highest FVi. Add the block of the highest FVi to PBS Remove the block of the highest FVi from UBS end while Optimize the total wire length by vertical or horizontal reflection of each block in the final PL
. (3) Complexity of the Algorithm A k-d tree data structure [10] is used in our implementation for manipulating the packed rectangles. It is actually a multidimensional binary tree which can be used for supporting area operations on 2-space. It provides fast O(log n) region searching operations which keeping the time for insertion and deletion small. A packing step will consume one or more corners and generate some new corners. After the first packing step, the corners of the current packing configuration PL will be 5, one corner packing step will at least create one new corner in most cases. So at ith step we may have

(4+i)*2*(n-i) CCPSs, where n is the total number of rectangles to be packed, when taking n/2 (an integer not smaller than n/2) packing step, The number of CCPSs will be (4+n/2)*n. Therefore, for each object to be packed, the length of the list of CCPSs generated will be bounded by O(n2). For each entry in the list, a pseudo-packing for each remaining rectangle will be done. As a result, the complexity of one iteration will be O(n2 *n2 * log n) . The process is repeated once for each rectangle packed, so the worst case complexity will be O(n5 * log n). Actually, the average time complexity will be smaller due to the shortening of CCPSs list after each successful pseudo-pack.

4. EXPERIMENT RESULTS We implemented the algorithm using C programming language and run it on a 250M Sun Spark station. To examine the efficiency of the proposed algorithm, we apply our algorithm to the MCNC benchmark circuits. In order to find the minimum bounding box sizes for successful solutions, we continued our experiments with the size of bounding box increased gradually. The sides of the box are increased one unit a time and the experiments are repeated until a successful solution is obtained. Our experiment results are presented in the table below. For floorplanning, VLSI modules are soft, (a soft module is a module whose area is fixed while the aspect ratio is variable within a specific range), so it can get higher area usage and shorter wire length. For placement, all modules are hard blocks, so it is more difficult to get higher area usage and shorter wire length. Compared with the floorplan results in [11](on the same type computer), our placement results are comparable in area usage while the total wire length( we use the half perimeter model to measure the total wire length) is optimized in the same placement process. Whereas, [11] didn’t optimize wire length in their program, if they did the same as our program, their time would increase a great deal. It is obviously that we get better results for more difficult benchmarks in a very short time. 5. CONCLUSION Human have ever done a good job in solving packing problems, Our work has proved that imitate human behavior in solving complex problems, such as NP-hard problems, is an effect way to find efficient algorithms. For more the other packing problems, such as abutment constraint packing, packing with some soft blocks, etc., human also has accumulated experience to solve. To find this kind of effective heuristics and implement them in our algorithm is our next work.

REFERENCES [1] M.C.Chi, An automatic rectilinear partitioning procedure for standard cells, in Proc. 24th ACM/IEEE DAC, 50-88. 1987 [2] Sung-Soo Kim and Chong-Min Kyung, Circuit placement on arbitrarily shaped regions using the self-organization principle, IEEE Trans. On Computer-Aided Design, Vol.11, No.7, 844-854, Jul. 1992, [3] S.Kirkpatrick, “Optimization by simulated annealing”, Science 100, 671-680, 1983 [4] M.Rebaudengo, M.S.Reorda, “GALLO: A genetic algorithm for floorplan area optimization”, IEEE Tran. On CAD, vol.15, no.8, 943-951. [5] D.F.Wong, C.L. Liu, A new algorithm for floorplan design, Proc. of 23rd ACM/IEEE DAC, 101-107, 1986 [6] H. H.Murata, K.Fujyoshi, M.Kaneko, VLSI/PCB placement with obstacles based on sequence pair, IEEE Trans. On Computer Aided Design of Intigrated Circuits and Systems. Vol.17, No.1, 60-67,

circuits

Ami33 Ami33 Ami49 Ami49 Ami49 Ami33 Ami49

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Qty.of C pp + O pp 4+0 1+1 4+0 1+1 4+1

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ami33 placement

Jan. 1998 [7] S.Nakatake, M. Furuya and Y.Kajitani, Module placement on BSG-structure with preplaced modules and rectilinear modules, ACM/IEEE Asia Pacific Design Automation Conference, 1998 [8] Xianlong Hong, Gang Huang , Yici Cai, Jiangchun Gu, Sheqin Dong, C,-K Cheng, Jun Gu, Corner Block List: An Efficient and Effective Topological Representation of Non-Slicing Floorplan, ACM/IEEE International Conference on Computer Aided Design, 6-10, Nov., 2000 [9] Yuliang Wu, Wenqi Huang, Siu-chung Lau, C.K. Wang and Gilbert H. Young, An Effective QuasiHuman Based Heuristic for Sloving Rectangle Packing Problem, in press. [10] Jon L. Bentley, Multidimensional binary search trees used for associative searching, Communication of ACM, Vol.18, no.9, 509-517, 1975 [11] Huang Gang, Hong Xianlong, et al, VLSI floorplanning in arbitrarily-shapled rectilinear regions. Journal of software, supplement, 239-242, Jun, 1999

Table: Our Placement results Area Size of the Wire usage chip length (mm) % 94.7251 1251*1251 63.400 93.3193 1240*1250 70.477 97.0871 6701*6701 1376.27 95.0545 6702*6702 1472.97 93.4514 6908*6908 1516.05 Floorplan results in [11] 95.8 1258*1258 null 94.0 6939*6939 null

Time (sec.) 85.38 64.83 601.45 497.42 544.53 526 778

examples

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Fig. 7 [11] [11]

F ig . 7 a m i 4 9 p l a c e m e n t