Multi-level Arc Fault Circuit Interrupter with Collaborative Communications for Smart Grid HyungSeok Kim†‡ , SeongWoo Kim† , GiPoong Gwon† , DongRyul Lee‡ , and SeungWoo Seo† † Department of Electrical Engineering and Computer Sciences Seoul National University ‡ Sanion Co., Ltd., Seoul, South Korea Email: [email protected], {swkim, gpgwon}@cnslab.snu.ac.kr, [email protected], [email protected]

Abstract—An arc fault circuit interrupter (AFCI) is a device that provides protection from the effects of arc faults by deenergizing a circuit within a specified time after an arc fault is detected. In the United States, AFCI installation in bedroom receptacle outlets has been mandated since 2002. As AFCIs have been widely adapted to real situations, several kinds of AFCIs have been developed including branch/feeder, cord, outlet box, and portable designs. Using various types of AFCIs creates a hierarchy consisting of multi-level AFCIs such as a portable AFCI serially connected to an outlet box AFCI. This multilevel AFCI structure causes a serious problem by enabling an upper level AFCI to detect an arc fault occurring in the surveillance area of lower level AFCIs. This problem results in de-energizing the whole area covered by the upper level AFCI. In this paper, we propose a solution to the multi-level AFCI problem that occurs when several types of AFCIs are used in the same hierarchy. To provide a practical solution, we first present the theoretical background of a multi-level AFCI and suggest a solution that integrates collaborative communication and computing power into a conventional AFCI device. Finally, we introduce a prototype implementation of our approach. Our proposed approach can protect people and facilities against electrical fire hazards, which is one of major challenges that the smart grid aims to overcome using information technology.

I. I NTRODUCTION The Smart Grid is a technology intended to enhance the stability and security of power systems by providing optimal electric power to the right place at the right time, thereby protecting people and property from fire hazard caused by electrical faults, and increasing the dependability and quality of electricity. The smart grid works by integrating information technology including computer, communication, and network technologies into conventional electrical power systems. Numerous Smart Grid studies have been conducted by industry and academia recently. In this paper, we attempt to enhance fire safety, specifically with respect to electrical fires caused by arc faults [2], by integrating computer and communication technologies into conventional electrical safety devices. According to survey data from a major insurance company, up to 40,000 home fires can be associated with arcing and sparking. More than 350 people die and over 1,400 are injured each year in these fires. Property losses are well over 500 million dollars per year [1]. Normal circuit breakers open only in the presence of a short, and may not trip before a fire has begun due to arcing. Gregory et al. [3], [4] introduced

an arc fault circuit interrupter (AFCI) intended to mitigate the effects of arcing by de-energizing the circuit when an arc fault is detected. Since then, the AFCI has been standardized [6] and commercially developed. Consequently, in the United States, AFCI installation in bedroom receptacle outlets has been mandated since Jan. 1, 2002. Several kinds of AFCIs have been developed and extensively adapted in practical applications [5]. For example, a branch/feeder AFCI is a device intended for installation in a cabinet panel to protect distribution circuits and power lines. A cord AFCI is a plug-in device intended for an outlet connection, and an outlet box AFCI is installed as an outlet box. Residential houses and other facilities can also have more than one outlet containing an AFCI. Thus, as various AFCIs are used in various ways, a hierarchy between AFCIs can be established. For example, consider a portable AFCI connected to an outlet as a plug-in. In this case, the AFCI hierarchy consists of two AFCIs. In contrast to an unintentional hierarchy, an intentional AFCI hierarchy can provide intelligent protection for spacious facilities. The AFCI hierarchy causes a significant problem by enabling more than one AFCI to detect an arc fault, which typically causes unwanted areas to be de-energized. Hence, we aim to minimize de-energized areas by integrating communication and computing power into a conventional AFCI system, specifically by employing collaborative communication between AFCI devices. Our contributions from this study are summarized as follows: 1) The multi-level AFCI problem was analyzed in detail. 2) We proposed a solution to resolve the arc fault multidetection problem of multi-level AFCIs using collaborative communication between conventional AFCI systems. 3) We successfully implemented a multi-level AFCI prototype based on our approach, and introduced its specifications and protocols in detail. Our proposed approach can protect people and facilities against electrical fire hazards, which is one of major challenges that the smart grid aims to overcome using information technology. The remainder of this paper is organized as follows. Section II describes the arc fault analytically with single level AFCI

Current (Amp)

i0 i0'

(a) Fig. 1.

K arc i0

Ideal current Arc current Time

Fig. 2. Shoulder effect caused by arc faults. The AFCI can detect arc faults by measuring current drop of as much as Karc i0 .

(b) Single level AFCI.

examples. Section III deals with the problem of multi-level AFCI adoption and provides theoretical solutions. Section IV provides detailed information for practical implementation. Section V presents our conclusions.

Consequently, when an arc fault occurs, the current difference due to the arc fault is Karc i0 at the AFCI0 . This appears as a shoulder effect with high frequency noise, as shown in Fig. 2. The AFCI can detect arc faults by measuring the current difference Karc i0 as shown in Fig. 2.

II. S INGLE - LEVEL AFCI

III. M ULTI - LEVEL AFCI

In this section, we present a theoretical background that describes how a conventional single level AFCI detects an arc fault and opens the circuit.

In this section, we introduce a multi-level AFCI circuit, and describe why it is not straightforward to make the multi-level AFCI to work well, by using a circuit example consisting of one upper level AFCI and four lower level AFCIs.

A. Normal operation in single level AFCI circuit Figure 1(a) shows normal circuit operation connected with VAC220V without arc faults. The relationship between current, voltage, and impedance is represented by V0 = i0 Z0

(1)

where i0 and V0 are the current and voltage of AFCI0 , respectively. Impedance Z0 is a time-varying function according to the characteristics of load or user manipulation; however, we assume that Z0 is time-invariant for simplicity. B. Arc fault in single level AFCI circuit Figure 1(b) shows a circuit in which an arc fault occurs. With respect to voltage, the following equality is established: VAC220V = V0 = V0′ .

(2)

From the viewpoint of AFCI0 in Fig. 1(b), the relationship between V0′ , i′0 , Z0 , and arc impedance Zarc is as follows: V0′ = i′0 (Z0 + Zarc ). Although Zarc is also a time-varying function, we used Zarc instead of Zarc (t) for simplicity. From Eqs. (1) and (2), V0′ = V0 = i0 Z0 . Therefore, we can derive i0 Z0 = i′0 (Z0 + Zarc ). Then, i′0 is given by i′0 =

Z0 Zarc i0 = (1 − )i0 . Z0 + Zarc Z0 + Zarc

By substituting follows:

Zarc Z0 +Zarc

into Karc , we can derive

i′0 = (1 − Karc )i0 .

i′0

A. Normal operation in multi-level AFCI circuit Figure 3 shows a multi-level AFCI circuit connected to 220 V alternating current (ac) without arc faults. We derive the relationship between components as follows: V0 = V1 = V2 = V3 = V4 = VAC220V

(4)

i0 = i1 + i2 + i3 + i4

(5)

1 1 1 1 1 = + + + . Z0 Z1 Z2 Z3 Z4

(6)

In Eq. (6), Z0 is a compound resistance. From the viewpoint of AFCI1···4 , the relationship between voltage, current, and impedance is satisfied by V1 = i1 Z1 , · · · , V4 = i4 Z4 .

Accordingly, by Eqs. (1), (4), and (7), the following equality is established: i0 Z0 = i1 Z1 = i2 Z2 = i3 Z3 = i4 Z4 .

(3)

(8)

B. Upper level arc fault in multi-level AFCI circuit Figure 4 shows a situation in which an arc fault occurred at the upper level in a hierarchical circuit. The relationship between components in AFCI0 is the same as that described by Eqs. (4) to (6). From the point of view of AFCI1···4 , the following equality is satisfied: V1′ = i′1 Z1 , · · · , V4′ = i′4 Z4 .

as

(7)

(9)

Since the structures of AFCI1···4 are the same, we can analyze AFCI1 . Because the impedance of a serial arc fault occurred between the upper level and lower level (viz., Zarc in Fig. 4),

Fig. 3. Normal circuit operation of a multi-level AFCI circuit consisting of one upper level AFCI and four lower level AFCIs.

Fig. 4. Arc fault occurred between AFCI0 and AFCI1···4 ; i.e., at Zarc , in the multi-level AFCI circuit.

a voltage drop occurred. This phenomenon can be formulated as follows:

1 1 1 1 1 = + + + . ′′ Z0 Z1 + Zarc Z2 Z3 Z4 As we considered in Section II-B, from the viewpoint of AFCI1 , V1′′ = i′′1 (Z1 + Zarc )

V1′ = V2′ = V3′ = V4′ = V0′ − i′0 Zarc . Using Eqs. (2) and (4), V0′ = V0 = V1 , therefore V1′ = V0′ − i′0 Zarc = V1 − i′0 Zarc . We can say V1 = i1 Z1 and V1′ = i′1 Z1 by Eqs. (7) and (9), so i′1 Z1 = i1 Z1 − i′0 Zarc .

′′ )i1 . i′′1 = (1 − Karc ′′ is defined as follows: In this context, Karc ′′ Karc =

By Eq. (3), i′0 = (1 − Karc )i0 , and we can derive i′1 Z1 = i1 Z1 − (1 − Karc )Zarc i0 . If we organize above Eq. with respect to

i′1 ,

then

(1 − Karc ) Zarc i0 Z1 (1 − Karc ) Z1 = i1 − Zarc i1 Z1 Z0 Zarc (1 − Karc ) + Zarc )i1 = (1 − )i1 = (1 − Z0 Z0 + Zarc Z0 = i1 = (1 − Karc )i1 . (10) Z0 + Zarc

Equation (10) shows that the lower level arc fault detector can detect an arc fault occurring in the upper level. Table I shows the arc fault detection possibility and AFCI list which must be opened when an arc fault occurs in the area of the upper level of a multi-level AFCI circuit.

V2′′ = i′′2 Z2 ,

Figure 5 shows a situation in which an arc fault occurs at a lower level in the hierarchical circuit. We can first derive the relationship between components as follows: =

=

i′′0

V2′′

=

i′′1

= +

V3′′ i′′2

=

+

V4′′

i′′3

+

= VAC220V i′′4

(11) (12)

V3′′ = i′′3 Z3 ,

V4′′ = i′′4 Z4 .

′′ Moreover, by Eqs. (4) and (11), the relationship between V2···4 ′′ and i2···4 is

V2′′ = V2 , i′′2 = i2 ,

V3′′ = V3 , i′′3 = i3 ,

V4′′ = V4

i′′4 = i4

(14)

This means that the arc fault that occurred in the area covered by AFCI1 does not affect AFCI2···4 which is based on the assumption that their power supplies are infinite. TABLE I D E - ENERGIZING LIST AND DETECTION PROBABILITY

C. Lower arc fault in multi-level AFCI circuit

V1′′

Zarc Z1 + Zarc

From the viewpoint of AFCI2···4 , the relationship between and ′′ ′′ is described as follows: , i′′2···4 and Z2···4 V2···4

i′1 = i1 −

V0′′

(13)

voltage

current

detection possibility

should be opened

AFCI0

V0

(1 − Karc )i0

Y

Y

AFCI1

V1

(1 − Karc )i1

Y

N

AFCI2

V2

(1 − Karc )i2

Y

N

AFCI3

V3

(1 − Karc )i3

Y

N

AFCI4

V4

(1 − Karc )i4

Y

N

Fig. 6. Single level AFCI embedding micro-controller and communication functionality.

Start

Fig. 5. Arc-fault occurred at between AFCI0 and AFCI1 in the multi-level AFCI circuit.

Initialization

Now, we derive the current of If we subtract Eq. (12) with Eq. (5), i2···4 and i′′2···4 are removed from Eq. (14). Consequently, i′′0 − i0 = i′′1 − i1 .

Arc-fault type

′′ ′′ i1 )i1 − i1 = i0 − Karc i′′0 = i0 + (1 − Karc Z0 ′′ = (1 − K )i0 . Z1 arc

Control msg received?

voltage

current

(15)

Z0 K ′′ )i Z1 arc 0 ′′ )i − Karc 1

detection possibility

should be opened

AFCI0

V0

(1 −

Y

N

AFCI1

V1

(1

Y

Y

AFCI2

V2

i2

N

N

AFCI3

V3

i3

N

N

AFCI4

V4

i4

N

N

Parallel Arc-Fault

Serial Arc-Fault Waiting time calculation & detection report

TABLE II D E - ENERGIZING LIST AND DETECTION PROBABILITY

Break the circuit

Yes

If we organize the preceding expression with respect to i′′0 , then

Equation (15) means that AFCI0 can detect an arc fault occurring between AFCI1 and Z1 . However, if AFCI0 opens its circuit, the whole area covered by AFCI0 is de-energized including AFCI2 , AFCI3 and AFCI4 . In this case, it is good enough to open the circuit of AFCI1 for minimizing deenergized areas. Thus, an arc fault should be dealt with the least level AFCI among AFCI detecting the arc fault. Table II shows the arc fault detection possibilities and the AFCI list which has to be de-energized when the arc fault occurs in the lower level area of a multi-level AFCI circuit. From the viewpoint of implementation, a higher AFCI which detects an arc fault can decide whether to open its circuit, after receiving signals from its lower level AFCIs. Hence, communication functionality and processing power are necessary to deliver such signals.

No

Arc-fault detection?

AFCI0 , i′′0 .

Control msg

Yes

Message type

Waiting msg

No No

Waiting time expired? Yes

Fig. 7.

Sequence diagram for implementing the multi-level AFCI.

IV. I MPLEMENTATION OF M ULTI - LEVEL AFCI In this section, we present a multi-level AFCI implementation of our approach with detailed specifications and an embedded protocol. To implement a multi-level AFCI, we built a single level AFCI embedding micro-controller and communication functionality. We used a Texas Instruments 16 MHz MSP430 16bit MCU (Microcontroller Unit) equipped with 116 Kbyte flash memories and 8 Kbyte random access memory (RAM). Communication was conducted through a RS-232C at 8400 bps. Our implementation of the single level AFCI is shown in Fig. 6. Figure 7 shows a sequence diagram for implementing the multi-level AFCI using this single level AFCI. The details of the difference between serial arc and parallel arc shown in Fig. 7 are explained in [4]. Figure 8 shows an experiment with the multi-level AFCIs. The assumptions and time parameters in our design are defined as follows: 1) An arc fault is caused from load current. Therefore, if

between arc detection and the time when its current is actually de-energized. 3) Signal Waiting Time: This means the remaining time after the AFCI detects an arc fault, which can be calculated from subtracting the de-energizing delay time from the de-energizing time. Based on the received messages from other AFCIs through collaborative communications, the AFCI can decide whether open the circuit or not during this signal waiting time. Additionally, from the analysis results described in Sections III-B and C, we can create an activity table; i.e., describe how the AFCI must be operated based on its measurement data or received data from other AFCIs. Table III is an example in which an arc fault occurred in the surveillance area of AFCI1 . In this case, AFCI0 and AFCI1 detected the arc fault at the same time, but only AFCI1 was required to open the circuit. (More tables can be constituted, but we omit these due to space limitations.) Fig. 8.

V. C ONCLUSION

Real-experiment with the multi-level AFCIs.

In this study, we analytically and experimentally investigated multi-level AFCI problems. We propose a solution to resolve the arc fault multi-detection problem of multi-level AFCIs using collaborative communication in conventional AFCI systems. We successfully implemented a multi-level AFCI prototype, and we provided specifications and embedded protocols. Our proposed approach can protect people and facilities against electrical fire hazards, which is one of major challenges that the smart grid aims to overcome by using information technology. R EFERENCES

Fig. 9. Arc test clearing times. Solid line and dotted line represent TC (Time-Current) curves with respect to 20 A and 15 A, respectively.

load current does not exist, the AFCI does not detect an arc fault. 2) The probability that an arc fault occurs in several lines at the same time is quite low. 3) When an arc fault occurs in the load of an AFCI, the AFCI detects it 100% percent. 4) There is no cross talk between AFCIs when an arc fault occurs.

[1] “Arc fault circuit interrupters (AFCI) reduce fire hazards.” [Online]. Available: http://ground-fault-circuit-interrupter.blogspot.com/2009/10/arcfault-circuit-interrupters-afci.html [2] T. Gammon and J. Matthews, “Instantaneous arcing-fault models developed for building system analysis,” IEEE/ACM Transactions in Industry Applications, vol. 37, no. 1, pp. 197–203, Jan/Feb 2001. [3] G. D. Gregory and G. W. Scott, “The arc-fault circuit interrupter: an emerging product,” IEEE/ACM Transactions in Industry Applications, vol. 17, no. 5, pp. 928–933, Sep/Oct 1998. [4] G. D. Gregory, K. Wong, and R. F. Dvorak, “More about arc-fault circuit interrupters,” IEEE/ACM Transactions in Industry Applications, vol. 40, no. 4, pp. 1006–1011, Jul/Aug 2004. [5] G. Parise, L. Martirano, and R. G., “Arc-fault protection of branch circuits, cords and connected equipment,” in IEEE Technical Conference Industrial and Commercial Power Systems, May 2003, pp. 85–88. [6] Underwriters Laboratories Inc., “Arc-fault circuit-interrupters, UL 1699,” Tech. Rep., Jan. 1999.

TABLE III A N ACTIVITY TABLE EXAMPLE

Based on the preceding assumptions, we define the following time parameters: 1) De-energizing Time: Using the table from UL (Underwriters Laboratory) 1699 [7], the AFCI must open the circuit within a specified time after the arc fault is detected. The time is the arc test clearing time shown in Fig. 9. 2) De-energizing Delay Time: This means the time taken

current flows to load

arc-fault detected

AFCI opens circuit

fault area

AFCI0

Y

Y

N

N

AFCI1

Y

Y

Y

Y

AFCI2

Y

N

N

N

AFCI3

Y

N

N

N

AFCI4

Y

N

N

N