Prototyping with Software-defined Radio Platform NI Test Technology Forum 2015 Yonsei University, Korea April 23rd, 2015 Presenter : MinKeun Chung

TRADITIONAL WIRELESS COMMUNICATION RESEARCH

Analysis Simulation

Idea

Implement / Test

Hand over to RTL designer (C/C++/HDL)

TRADITIONAL APPROACH FOR WIRELESS COMMUNICATION

Baseband

x

y = hx h

y

Gaussian Random Base Station

User Equipment

SIMULATION IS USEFUL BUT…



Wireless channel is fundamentally unpredictable



A perfect simulation does NOT guarantee perfect system operation in real world



Need to prototype

NEW WIRELESS COMMUNICATION RESEARCH

Analysis Simulation

Idea

Prototyping with SDR

NEW APPROACH FOR WIRELESS COMMUNICATION Up Conversion (e.g. 2.5GHz)

Down Conversion RF

Realistic “h”

x Base Station

y User Equipment

SOFTWARE-DEFINED RADIO A radio communication system where components that have been typically implemented in hardware (e.g. mixers, filters, amplifiers, modulators/demodulators, detectors, etc.) are instead implemented by means of software on a personal computer or embedded system

Software

Hardware

WHAT IS LABVIEW? •

LabVIEW uses a patented dataflow programming model



NOT sequential programming architecture of text-based prgramming languages



The graphical code is similar to block diagrams and flowcharts



The flow of data between nodes determines the execution order in LabVIEW



Multiple blocks can execute in parallel



Ideal for implementation that involves multitasking and multitreading (e.g. in FPGA)

WHAT IS AN USRP?

NI USRP-2920/2922 Frequency (Hz)

50 MHz to 2.2 GHz/ 400 MHz to 4.4 GHz

Bandwidth

20MHz

DAC/ADC

DAC : 16 bit , 400 MS/s ADC : 14 bit, 100 MS/s

Output Power

17 dBm to 20 dBm

Processing

Host

WHAT IS AN USRP? Network Cable

Host Computer Network Cable

USRP Tx 1

MIMO Cable

USRP Tx 2

Gigabit Ethernet Switch

Network Cable

USRP Rx 1

MIMO Cable

USRP Rx 2

WHAT IS REAL-TIME SYSTEM?

Real-time Response The ability to reliably and, without fail, respond to an event or perform an operation within a guaranteed time period

WHAT IS PXI PLATFORM? NI PXIe-1075 Chassis

NI PXIe-8133 Controller

Power Supply / Cooling PXI Backplane (Bus technology / Timing / Synchronization)

NI 5791 RF FAM / NI PXIe-7965R FlexRIO

Transceiver ADC/DAC RF Up/Down Conversion

FPGA Module for Real-time Testbed (Xilinx Virtex-5)

Quadcore Controller Window OS LabVIEW (Software)

WHAT IS AN FPGA? •

Field Programmable Gate Array



A silicon chip with unconnected gates and other hardware resources



Enables user to define and re-define functionality Interconnect Resources

I/O Cells

Logic Blocks

WHAT IS AN FPGA? High

Microprocessors General Purpose Short design cycles

Low

Flexibility

FPGAs Reconfigurable array of fixed resources Longer design cycles than Microprocessor

Performance

Low

ASICs Specific Purpose Long design cycles

High

HOW DOES AN FPGA WORK?



Circuit behavior is defined using software



Circuit specification (gate connection, etc) is loaded into the hardware



No operating system is needed for execution of logic

APPLICATION: REAL-TIME FULL DUPLEX RADIOS

WHAT IS FULL DUPLEX RADIOS? Time

Time Uplink

Uplink

Downlink

Downlink

Freq.

Time Division Duplex

Freq.

Frequency Division Duplex

WHAT IS FULL DUPLEX RADIOS? Time

Uplink / Downlink Simultaneously

Full Duplex

Freq.

WHAT IS A KEY ISSUE? •

Full Duplex SIC RF Front-End (Analog Cancellation)



PXIe based Full Duplex Testbed (Digital Cancellation)

Full Duplex Infrastructure

Uplink RX RF Front-End

RX RF

Uplink Signal

Self-interference Cancellation Downlink Signal

TX RF Downlink TX RF Front-End

KEY FACTORS FOR SIC REQUIRED



Dynamic range / Resolution of ADC



Range of the expected signal strengths

WHAT IS THE DYNAMIC RANGE? The ratio between largest and smallest acceptable values of a variable of interest.

DR (dB) = 6.02 x n +1.76dB n: The number of bits in the DAC/ADC Resolution NI 5791 RF Transceiver: 14-bit ADC, DR (dB) = 86dB

* * *

Macro Cell TX Power: 46dBm Small Cell TX Power: 24dBm Mobile TX Power: 23dBm WiFi TX Power: 23dBm

-4dBm

14-bit ADC Dynamic Range =86dB

No Saturation

*

Saturation

HOW MUCH SIC IS NEEDED?

High PAPR = 7dB Small Cell TX Power

Gain Compression Point

Thermal Noise Floor

31dBm 24dBm

-15dBm

-90dBm

WHAT IS A GAIN COMPRESSION?

Linear Region Saturation Region

Gain Compression Point

EQUIPMENT

NI PXIe 5791 RF FAM [2pcs]

NI 7965R FlexRIO FPGA Module [4pcs]

RESOURCES & PARAMETERS (1) Center Frequency : 2.52 GHz

BW : 20MHz (Subcarrier Spacing :15kHz)

RESOURCES & PARAMETERS (2)

LTE slot : 0.5 ms (LTE downlink release 8) 15360 Samples (6 OFDM Symbols) Sampling Frequency : 30.72 MHz

CP

CP

CP

CP

66.7 us / 2048 Samples 16.7 us / 512 Samples

CP

CP

Expanded CP FFT Size : 2048

RESOURCES & PARAMETERS (3)

QPSK

16QAM

64QAM

BLOCK DIAGRAM OF A FULL DUPLEX RADIO ARCHITECTURE

SYNCHRONIZATION & CHANNEL ESTIMATION

Primary Sync Signal (Time Sync.) Root Index : 25

Primary Sync Signal (Time Sync.) Root Index : 29

Resource Element R0

R0

R0

R0

R0

R0

R0

R0

R1

Orthogonal Pilot Allocation Not allocated

R1

R1

R1

R1

R1

R1

R1

SYNCHRONIZATION & CHANNEL ESTIMATION

Time Sync. [Far-End FD] Primary Sync. Signal (Root Index : 25)

20MHz Channel Estimation [Far-End FD]

Time Sync. [Near-End FD (SI)] Primary Sync. Signal (Root Index : 29)

20MHz Channel Estimation [Near-End FD (SI)]

ANALOG SIC PERFORMANCE Analog Passive Cancellation 40MHz

-35dB (Cancellation)

2.52GHz

ANALOG SIC PERFORMANCE Analog Active Cancellation

-60dB (Cancellation) 20MHz 2.52GHz

DIGITAL SIC PERFORMANCE Calculating Digital SIC Performance Self-interference QPSK

Digital SIC (SI : QPSK)

Cancel Out

- 43dB (Avg.)

CONTELLATION RESULT THROUGH SIC Only Analog Passive SIC Desired Symbol : 64 QAM Self Interference : QPSK (Noise)

Analog Passive SIC+ Digital SIC

EXPERIMENT SETUP

Uplink Signal

Downlink Signal

Self-interference Cancellation 1.2m

EXPERIMENT SETUP @ GLOBECOM 2014 Full Duplex RF

Uplink Signal Self-interference Cancellation Downlink Signal

NI PXIe 5791 RF FAM [2pcs]

DEMO AT IEEE GLOBECOM IN AUSTIN, TX, USA, DEC. 2014

NI 7965R FlexRIO FPGA Module [4pcs]

THROUGHPUT ANALYSIS

QSPK

16QAM

64QAM

Half Duplex

21.57Mbps

43.14Mbps

64.71Mbps

Full Duplex

41.01Mbps

82.01Mbps

122.6Mbps

Throughput Gain

1.9x

1.9x

1.89x

APPLICATION: HYBRID BEAMFORMING FOR SMART SMALL CELL

WHY HYBRID BEAMFORMING? • 

For many RF antennas such as massive MIMO, full digital beamforming requires considerable RF hardware cost

• 

By combining analog/digital beamforming, low RF hardware cost compared to full active digital beamforming

HYBRID BEAMFORMING PROTOTYPE

HYBRID BEAMFORMING PROTOTYPE

THANK YOU ANY QUESTION? [email protected]
 https://sites.google.com/site/minkeunchung

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