Process Variation and NBTI Tolerant Standard Cells to Improve Parametric Yield and Lifetime of ICs Shubhankar Basu and Ranga Vemuri Dept. of ECE, University of Cincinnati, Cincinnati, Ohio, USA {basusr,ranga}@ececs.uc.edu Abstract Negative bias temperature instability (NBTI) has become a growing concern in nanometer technologies. It may reduce the lifetime of reliable operation of PMOS transistors in the design. Process variation has started impacting the nanometer ICs by reducing the parametric yield. Process variation together with NBTI can further reduce the reliable lifetime of ICs. Conventional ASIC design methodology uses pre-characterized standard cells to optimize the design as per specifications. The standard cells occupy nearly 75% of the chip real estate in a sea-of-gate design. Therefore process variation and NBTI tolerant robust standard cells may help in reducing the margin of performance variation thereby increasing the lifetime of reliable operation. The use of robust cells may further help in reducing the design time overhead. In this work, we model the combined effect of process variation and NBTI on intrinsic gate delay using a reduced dimension modeling technique. We use the models to optimize the standard cells in the presence of NBTI and process variations with a target lifetime of 10 years. Experimental results show that the use of optimized robust standard cells can considerably improve the tolerance of circuit in the self-timed sections of critical timing paths.

1

Introduction

Reliability of performance and lifetime of an IC are succeptable to the effects of process variations and NBTI. [6] cites the importance of adopting new design methodologies and integration at early design stages to account for such effects. Designs in modern technologies have a demand for high drive current at lower operating voltage. This has made NBTI [5] a serious threat which shifts the threhold voltage (Vth ) considerably and reduces the drive current (Idsat ). NBTI degradation affects the PMOS devices when the gate voltage is negative (Vgs = −Vdd ). It occurs due to an electromechanical reaction involving the electric field, holes, Si-H bonds and temperature. NBTI stress may be subdivided into two different types: (1) Static (DC) stress, and (2) Dynamic (AC) stress. Static NBTI stress occurs due to an extended ON state of the PMOS and has a much larger impact on the Idsat due to a larger variation in Vth . Dynamic NBTI stress follows a reaction-diffusion mechanism. In dynamic state, a transistor switches from an ON state to an OFF state and vice

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versa. Part of the stress created due to the generation of the interface traps during the ON state is passivated (annealed) during the OFF state, when the hydrogen atoms recombine with the silicon ion to form the Si-H bond. Therefore degradation due to dynamic stress is much less as compared to the static stress. The degradation in performance of PMOS devices due to NBTI is agravated in the presence of process variation. The worst case variation in zero-biased threshold voltage due to process defect together with the NBTI effect may even fail to turn the transistor ON, as (V gs − Vth ) reduces significantly. The identified methods of mitigating the NBTI effects are Vdd tuning and PMOS transistor sizing. In this work we concentrate on the self-timed (combinational) standard cells which are a part of the critical timing paths and have a high switching activity. Therefore we model for the dynamic NBTI stress effect on the intrinsic gate delay. The need for a combined Vdd tuning and PMOS sizing method has been identified as a better optimization technique through a series of experiments conducted on the standard cells and circuits. In [11], we demonstrate the need to adopt statistical techniques to capture the randomness in process parameters in our performance model. The randomness also necessitates the consideration of relative variation amongst parameters of different transistors in the circuit. We presented a novel technique to combine the randomly varying process parameters of devices to generate equivalent models for reduced dimensional statistical modeling of intrinsic gate delay of standard cells. In this work, we evaluate the NBTI induced Vth shift (∆Vt0 ) using the upperbound model proposed in [12] for a target lifetime of 10 years. We develop equivalent parameters that analytically combine the random variables (physical parameters), using the statistical techniques presented in [11] based on their combined sensitivity to the performance function. The model captures the statistical variations in intra-gate transistor parameters and NBTI impact on PMOS threshold voltage for different combination of inputs, and uses statistical ’min’ and ’max’ functions to capture the real worst case scenarios. The statistically generated performance models are used to optimize the standard cells in the presence of process variation and NBTI effects. Fig. 1 presents our entire methodology as a flow diagram. In a sea-of-gate design technique, pre-designed standard cells occupy almost 75% of the chip real estate. While a lot of research has taken place in post-layout Statistical Static

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Timing Analysis (SSTA) techniques [2, 7], optimally designed variation-tolerant standard cell libraries are still inadequate. These cells can help reduce the design cycle overhead due to respin. Moreover these robust standard cells should also be tolerant towards degradations due to NBTI effects. The rest of the paper is organized as follows. Section 2 proposes a gate delay model using reduced dimension equivalent parameters and Response Surface Method (RSM) taking into consideration the intra-gate variability and NBTI degradation over 10 years. Section 3 describes the optimization procedure for developing variation-tolerant standard cells. Section 4, details the experimental results obtained for several combinational gates, and using them in digital circuits. Finally, Section 5 states the conclusion.

2 Reduced Dimension Gate Delay Modeling In this work we use response surface methods(RSM) [10] to model gate delay as a function of the randomly varying physical parameters of devices. The randomness of the physical parameters is a result of intra-gate variability due to process irregularities. The threshold voltage of the PMOS transistors in the gates are further modulated with the ∆Vt0 due to the dynamic NBTI stress for a lifetime of 10 years. For the purpose of transistor sizing to generate a variationtolerant gate, we define gate delay (tdlay) to be a performance metric as:

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!2b −a k=1

t(l−h)k +

1 a

!a

l=1 t(h−l)l

2

(1)

where ’b’ is the number of inputs to the gate and ’a’ denotes the number of combinations that causes the output of the gate to discharge (h-l). This metric is used to optimize the gates in the presence of randomly varying intragate physical parameters and NBTI.

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Modeling of dynamic NBTI effect

We adopt the reaction-diffusion model [3, 4] for estimating the long term degradation of PMOS transistors due to the NBTI effect. In [5] the authors present the physics of NBTI mechanism. A Si atom has 4 electrons in its valence band. Due to crystal mismatch at Si−SiO2 interface, traps are present in the form of Si dangling bonds after the growth of gate oxide. These are called interface trap (Nit ), which induce stress in the interface. A portion of these dangling electrons may combine with ambient hydrogen to form Si−H bond which anneals the stress. Under the influence of a negative gate voltage in the PMOS transistors (Vgs = −Vdd ), when the PMOS is in an ON state, the inversion layer in the devices have a high density of holes which under the influence of the electric field (Eox ) reacts to break the Si − H bonds, creating an interface trap (Nit ) and one H atom for each bond that diffuses away from the interface into the oxide towards the gate. The Nit causes the positive charge (Qit ) to increase which in turn causes the Vt0 to degrade [3]. In the OFF state, portion of the H atoms diffuse back through the oxide layer and recombine with the dangling Si bonds to form Si − H which anneals the stress. However the entire amount of Nit generated is not possible to be passified by the H atoms. With time the H atoms diffuse sufficiently enough through the oxide to reach the gate in which case, it can no longer diffuse back towards the substrateoxide interface. This results in the absence of H atoms to recombine. This state is called lock-in and the degradation is permanent. We now present the model presented by Bhardwaj et al in [12] in the context of our work. 2.1.1

Stress and Recovery cycle in dynamic NBTI

During switching a PMOS transistor goes through an alternate stress (Vgs = −Vdd ) and recovery (Vgs = 0) periods. Therefore for one cycle of stress and recovery the ∆Vt may be expressed as: Stress: ∆Vt = (Kv (t − t0 )1/2 +

" ∆Vt0 )2n

(2)

ξ2 C(t − t0 ) √ ) Ct

(3)

2n

Recovery: ∆Vt = Vt0 (1 −

2ξ1 te +

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TDlay (Seconds)

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6

7

8

9

0 0

10

Time (Years)

1

2

3

4

5

6

7

8

9

10

Time (Years)

Figure 2. ∆Vt0 for PMOS transistors in NAND2

Figure 3. Comparing TDlay of NAND2X1

where: Kv C te

√ qtox 3 2 2Eox ) K Cox (Vgs − Vt ) Cexp( ) (4) "ox E0 −Ea ) (5) = T0−1 exp( kT = tox (6)

= (

In our modeling we choose a H-based model. The parameter values were chosen from the 65nm NBTI model proposed in [1]. In our model we assume that a fast recovery is possible for the entire duration of 10 years due to the presence of H in the oxide. Therefore te is chosen to be equal to tox . 2.1.2

Long term Vt degradation for PMOS

Dynamic NBTI over a long period of switching is dependent on the number of cycle completed (m) during the time(t). Therefore m = t/Tclk

(7)

where Tclk is the period of operation of the clock. As cited in [12], for a very long term and for a very high frequency, experimental results have shown that ∆Vt is independent of frequency. The duty cycle (α) is assumed to be 0.5. Using the above assumptions, we use the upper bound expression as derived in [12] as follows:

∆Vth ≤ (

√

∆Vtgate =

1/2n

√

Vt = init Vt0 worst + ∆Vt0

(8)

Fig. 2 shows the ∆Vt0 for each PMOS transistor in a 2-input nand gate using 65nm predictive technology model over different time duration of operation. 2.1.3 NBTI effect on delay of gate It may be noted that the change in the threshold voltage (∆Vt0 ) reduces the drive current (Idsat ) significantly during NBTI which also causes the low to high transition time

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Si ∆Vt0

(9)

where ’n’ is the number of transistor in the gate and ∆Vt0 is the degradation in the PMOS transistors. Si denotes the sensitivity of the transistor to the intrinsic delay of the standard cell. Degradation in the threshold voltage of individual transistor is not the same under the impact of intra-gate variation due to process defects when each transistor’s oxide thickness (tox ) and intial(zero-biased) threshold voltage (init Vt0 ) assume random and different values. Under this scenario, the relative impact of the degradation has to be considered. [13] cites the gaussian variation for typical parameters for different technology nodes. If we consider a uniform worst case value of initial threshold voltage for all PMOS transistors, we compute threshold voltage of each PMOS transistor as:

)

2ξ1 te + ξ2 C(1−α)Tclk √ 2tox + CmTclk

n # i=1

Kv2 αTclk 2n

1−βm

where: βm = 1 −

(tl−h ) of each PMOS transistor to increase. In order to optimize the gate delay, we need to consider a combination of all the PMOS devices based on their topology and the different combination of the inputs. Using nominal values for parameters, all PMOS transistors would have same degradation due to NBTI effect. Therefore the equivalent degradation in threshold voltage over all PMOS transistors (∆Vtgate ) may be expressed as:

(10)

However, this would lead to a very pessimistic modeling of NBTI effect on the combination of the transistors in the gate topology. Fig. 3 plots the TDlay of the 2-input NAND gate with nominal parameter values under NBTI effect and process varying parameter values and NBTI effect. It is visible that with process variation, the effect of NBTI results in 30 times more degradation in intrinsic gate delay (TDlay).

2.2

Statistical modeling of transistor parameters

The transistor characteristics are linked to its physical parameters [9]. In this work we consider the transistor oxide thickness (T ox), zero-biased threshold voltage (Vt0 ), effective width (Wef f ) and effective channel length (Lef f ) as

the physical parameters. The physical parameters of each transistor can be expressed as a vector p = (p1 , p2 , ..., pn )

T

where T denotes a transistor. Under the conditions of intergate and intra-gate variation, each physical parameter may be expressed as: p= pµ + pg + pr

(11)

where pµ represents the mean value of the parameter, pg denotes the inter-gate variation and pr represent the intragate variability. The intra-gate variability is a combination of correlated and uncorrelated random variables. Representing each transistor’s physical parameters as a separate random variable, increases the dimensionality of the RSM significantly, often requiring large run time and introducing unwanted error.

2.3 Derivation of gate delay model In [11], we develop a reduced dimension statistical technique to develop intrinsic gate-delay model for the standard cells. We model the delay as a function of the intra-gate varying random component of process parameters(pr ) of the transistors based on their combined sensitivity to the delay. We used response surface regression modeling technique to develop the gate-delay model with the equivalent parameter models(pr eq ) as independent variables. The uncorrelated parameters xr eq are derived from the correlated variables pr eq using PCA[8] as follows: pr eq = Dr eq Ur eq Λ1/2 r eq xr eq

(12)

Considering the mean value of the parameters(pµ ) and the inter-gate variation component of the parameters (pg ) as constants for all transistors in the standard cells, we express the intrinsic gate-delay of a standard cell using linear response surface model(RSM) and after transforming the correlated components to uncorrelated components as shown in [11]:

! tdlay pr eq = c0 +

p #

1/2

cj Dj Uj Λj xr eqj

(13)

j=1

where ’p’ is the nos. of principal components.

2.4

Under the effect of process variations, the physical parameter values become random in nature. A uniform distribution of samples is obtained using a limited number of monte carlo simulation runs, called the design of experiments. The equivalent parameter worst and best cases are sampled using a statistical ’min’ and ’max’ function and are expressed as:

Statistical Equivalent Parameter Model

In our work [11], we combine the physical parameters of transistors in a statistical equivalent intra-variability model, which follows the concept of transistor sizing by relating each parameter to a RC equivalent circuit and the way they are sensitive to the gate delay in the charging and discharging paths. We define Path PUN and Path PDN as: Path PUN implying a path from Vdd to Output which consists of series-parallel combination of transistors Path PDN implies a path from Output to Gnd which consists of seriesparallel combination of transistors.

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pd eq w = max(pd P ath P U Nj ) + max(pd P ath P DNk ) pd eq b = min(pd P ath P U Nj ) + min(pd P ath P DNk ) pi eq w = min(pi P ath P U Nj ) + min(pi P ath P DNk ) pi eq b = max(pi P ath P U Nj ) + max(pi P ath P DNk )

where w implies worst case, b implies best case, j implies P ath P U N index and k implies P ath P DN index. The goodness of fit measure for the RSM model is obtained using a residual computation and R2 technique [10] within 99% confidence interval. Our target is to obtain the value of R2 ≈ 1.

3 Optimizing the standard cells In this work we optimize the transistor sizes using the " reduced dimension statistical model for gate delay (tdlay) in order to reduce the worst case variation due to intra-gate parameter variation and NBTI effect after 10 years of operation. Our algorithm uses deterministic gate sizing. The objective of the deterministic sizing in our work is to compute the sizes of transistors such that the standard cell meets the worst case gate-delay constraints while consuming the minimum power and having the least area penalty. The optimization is performed over various combinations of input slew and load capacitance for the standard cells. Our optimization problem can be defined as: ∀(slew,!CL ) m Minimize k Wk s.t. " s,c + β1 ∗ (Avg P ow) β0 ∗ tdlay l

!pg ) + β1 ∗ (Avg P ow nominal) ≤ β0 ∗ (t0 + tdlay

where Wk is the cost due to the width of a transistor in the gate. β0 and β1 are the weights assigned to gate delay and power respectively based on the tradeoff decision of the design implementation. The algorithm starts from the minimum sized transistors, and picks up the combination of candidate transistor sizes, that satisfies the cost function. The values of equivalent parameters are chosen from the design of experiments data. The optimization is considerably faster than a monte-carlo based simulation-in-loop optimization method. Our results show that they are within 10% accuracy of monte carlo based methods, while achieving a three times reduction in run time.

Table 1. Preopt and opt TDlay for NAND2

Case Preopt Postopt

worst delay 3.95e-10 1.87e-10

mean delay 2.31e-10 8.37e-11

−10

x 10

σ 6.769e-11 1.89e-11

4

3

2

1

Table 2. Preopt and opt TDlay of INV1

Case Preopt Postopt

worst delay 3.659e-10 2.537e-10

mean delay 8.942e-11 7.82e-11

0 3.5

NBTI + Process

Improvement 30.68%

3

Only NBTI

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x 10

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2

Experimental Results

1.8 1.6

We classify our experimental results into two sections:

1.4 1.2 1

• Compare the effect of process variation and NBTI on preoptimized(preopt) and optimized(opt) standard cells.

0.8 0.6 0.4 3.5

• Compare the effect of process variation and NBTI effects on performance of digital circuits (TDlay) using preopt and opt standard cells. For our experiments we use an academic standard cell library(IITLIB) which have been scaled to be used with 65nm ASU Predictive Technology Model [1]. Due to the unavailability of layout technology rules for 65nm, we have developed a class of process variation and NBTI standard cells using TSMC 0.18µ technology with the process variation percentages as cited in [13] for 70nm technology. Spice netlist is extracted from the layout and simulated using HSpice in a monte carlo method. All experiments are performed on a Sun Blade 5000 machine with sparcV9 processor at 750MHz frequency.

4.1 Standard cells We present results for 65nm and 0.18µ technologies. 4.1.1 65nm Technology We compare the results of two standard cells, INV1 and NAND2 using 65nm PTM [1] for HSpice simulation. Fig. 4 shows the pre-optimized and post-optimized worst case delay variation for the NAND2. The parameters of the gate are random gaussian with the distribution cited in [13]. The threshold votage of the PMOS transistors are further modulated by ∆Vt0 due to NBTI stress with a target lifetime of 10 years. Fig. 4 shows, how the optimization helped in reducing the worst case variation in intrinsic gate delay (TDlay) in the presence of process variation in physical parameters and dynamic NBTI degradation after 10 years. Table 1 and Table 2 compare the worst case gate delay of the pre-optimzed and post-optimized NAND2 and INV1 cells respectively using a montecarlo simulation and statistical analysis.

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3 7

x 10

2.5 Secon d Pri

2

1.5

ncip

1

al Com

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7 First

8.5

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8

x 10

Figure 4. a) Pre-opt TDlay b) Post-opt TDlay Table 3. Preopt and opt standard cells in 0.18µ

Cell INV1 NAND2 NAND3 XOR2 4.1.2

ND 4.114e-11 5.138e-11 6.877e-11 9.096e-11

PV 5.930e-11 5.361e-11 7.413e-11 9.767e-11

PVNB 5.162e-10 3.960e-10 3.362e-09 4.022e-10

PVNBO 4.005e-10 3.655e-10 3.364e-10 5.113e-10

0.18µ Technology

For the standard cells in TSMC 0.18µ technology, our experiments showed that under the influence of NBTI effect and process variation, the PMOS transistors fail to turn ON over a lifetime of 10 years.. Therefore the standard cells have been designed with a target lifetime of 5 years using this technology. Table 3 presents the results of comparison of the performance(TDlay) of preoptimized and optimized cells for the following cases: • Nominal delay (ND) • Worst delay for preoptimized case due to process variation only (PV) • Worst delay for preoptimized case due to NBTI and Process variation after 5 years (PVNB) • Worst delay for optimized case due to NBTI and Process variation after 5 years (PVNBO) As we can observe, for some of the standard cells the optimized gate has a larger worst case delay than the preoptimized cell. However it has been noted that in those cells the standard deviation for all the delays for different combination of parameters is far less than the preoptimized cell. This is an important result as this can help in better predictibity and margin of performance within random variation of parameters.

Nominal Process Variation Process + NBTI (preopt): 1yr Process + NBTI (preopt): 5yr Process + NBTI (postopt): 5yr

Table 5. Preopt and opt worst path delay 8.00E-04

1.40E-04

7.00E-04

1.20E-04 1.00E-04 8.00E-05 6.00E-05 4.00E-05 2.00E-05

Average Power (Watt)

1.60E-04

6.00E-04 5.00E-04 4.00E-04 3.00E-04 2.00E-04 1.00E-04

Average Power (Watts)

Nominal Process Variation Process + NBTI (preopt):1yr Process + NBTI (preopt):5yr Process + NBTI (postopt): 5yr

Figure 5. (a) C17 worst average power comparison (b)Mod3 Counter worst average power comparison

4.2 Digital Circuits We present the results of comparing the worst path delay of three digital circuits, viz. 15-stage ring oscillator, C17(ISCAS’85) and Modulo3 counter. We perform two sets of experiments, once with the preopt standard cells and next with all the preopt standard cells replaced by optimized standard cells. The ring oscillator experiment is performed using 65nm cells while the remaining two circuits have been implemented with 0.18µ standard cells. In our experiment we use HSpice to perform a monte carlo simulation where the physical parameters are randomly selected from the gaussian distribution and with 104 iterations. Table 4 shows the improvement (Impr.) obtained in the path delay (1/freq) and average power consumption in the ring oscillator using the optimized gates. Table 4. Ring Oscillator - Path Delay and average power comparison

Preopt Postopt

Path Delay (ns) Worst 2.34 2.01

Avg. 0.56 0.45

ND 2.29e-10 3.48e-10 3.99e-10

PV 2.42e-10 3.87e-10 4.32e-10

PVNB 2.40e-09 6.18e-08 6.24e-08

PVNBO 1.72e-09 2.62e-08 4.24e-08

0.00E+00

0.00E+00

Case

Design C17 M3Count(P1) M3Count(P2)

Impr. 12.5%

Avg. power (mW) Worst 0.49 0.47

Impr. 2.25%

Table 5 presents the result of comparison of the worst path delay for the two designs(C17 and Mod3-Counter) under the influence of process variation and NBTI effect using preopt and opt standard cells which use the same cases (ND, PV, PVNB, PVNBO) as for the standard cells in 0.18µ experiments. It may be observed that for C17, the worst path delay has improved by 28% using the optimized standard cells with a penalty of 25% increase in power consumption. It is also observed that for the Mod3-Counter, the worst path delays improve by 31.9% and 57.59% for path1 and path2 respectively. The average power consumption of the circuit increases by 14.4%. Fig. 4.2(a) shows the comparison of worst average power consumption for the C17 circuit for different cases. Fig. 4.2(b) shows the comparison of worst average power consumption in Mod3-Counter for different cases.

5 Conclusion As technology continues to scale further down, the needs for performance continue to increase with lowered operat-

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ing voltage. Making tradeoff decisions between area, reliability of performance, lifetime and cost are becoming a tough problem. In this work, we presented a methodology to develop process variation and NBTI tolerant standard cells which may be used in timing critical sections of circuit. A library of optimized and characterized standard cells has been developed for 0.18µ technology. This would be extended for 65nm technology.

References [1] Predictive technology model. Technical report, http://www.eas.asu.edu/ ptm. [2] A. Agarwal et al. Statistical timing analysis for intra-die process variations. In IEEE ICCAD, 2003. [3] M. Alam. A critical examination of the mechanics of dynamic nbti for pmosfets. Technical report, IEEE International Electron Devices Meeting 2003. [4] B. Paul et. al. Temporal performance degradation under nbti: Estimation and design for improved reliability of nanoscale circuits. In IEEE Design Automation and Test in Europe, 2006. [5] Dieter Schroder and Jeff A Babcock. Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing. Journal of Applied Physics, 94(1), July 2003. [6] ITRS. Semiconductor roadmap 2005. Technical report, International Technology Roadmap for Semiconductors. [7] J.A.G. Jess et al. Statistical timing for parametric yield prediction of digital integrated circuits. In IEEE Design Automation Conference, 2003. [8] Juha Karhunen. Adaptive algorithms for estimating eigenvectors of correlation type matrices. In IEEE Intl. Conf. on Acoustics, Speech, and Signal Processing, 1984. [9] K. Okada et al. A statistical gate-delay model considering intra-gate variability. In IEEE ICCAD, 2003. [10] Khuri and Cornell. Response Surfaces, Designs and Analyses. Marcel Dekker Inc., NY, USA, 1996. [11] S. Basu and R. Vemuri. Process variation tolerant standard cell library development using reduced dimension statistical modeling and optimization techniques. In IEEE Intl. Symposium On Quality Electronic Design, 2007. [12] S. Bhardwaj et. al. Predictive modeling of the nbti effect for reliable design. In IEEE CICC, 2006. [13] X. Li et al. Asymptotic probability extraction for nonnormal distribution of circuit. In IEEE ICCAD, 2004.