Code No: RR320405
RR
SET-1
.in
B. Tech III Year II Semester Examinations, December-January, 2011-2012 VLSI DESIGN (ELECTRONICS AND COMMUNICATION ENGINEERING) Time: 3 hours Max. Marks: 80 Answer any five questions All questions carry equal marks --1.a) b)
Implement the 2- Input AND gate with CMOS Logic and explain its working Derive the equation for IDS of saturated region for NMOS transistor. [16]
2.a) b)
Explain CMOS fabrication using N well process? Explain BICMOS inverter with schematic and fabrication process.
3.
Design a stick diagram for CMOS logic shown below. Y = ((A+B) (C+D))1.
[16]
4.
Design a layout for CMOS NAND gate.
[16]
5.
Write short notes for following: a)FPGA b) PLA c)GLA
or ld
[8+8]
d)standard cells.
[16]
Design a PLA schematic for function F=∑(2,4,8,11,13,15).
[16]
7.a) b)
Explain in detail about circuit design flow. Explain about Design verification tools.
[8+8]
8.a) b)
Explain in detail about plasma oxidation process. Explain about IC packing techniques.
[8+8]
uW
6.
Aj
nt
--ooOoo--
Code No: RR320405
RR
SET-2
1.
Design a stick diagram for CMOS logic shown below. Y = ((A+B) (C+D))1. Design a layout for CMOS NAND gate.
3.
Write short notes for following: a)FPGA b) PLA c)GLA
[16]
[16]
or ld
2.
.in
B. Tech III Year II Semester Examinations, December-January, 2011-2012 VLSI DESIGN (ELECTRONICS AND COMMUNICATION ENGINEERING) Time: 3 hours Max. Marks: 80 Answer any five questions All questions carry equal marks ---
d)standard cells.
[16]
Design a PLA schematic for function F=∑(2,4,8,11,13,15).
[16]
5.a) b)
Explain in detail about circuit design flow. Explain about Design verification tools.
[8+8]
6.a) b)
Explain in detail about plasma oxidation process. Explain about IC packing techniques.
[8+8]
7.a) b)
Implement the 2- Input AND gate with CMOS Logic and explain its working Derive the equation for IDS of saturated region for NMOS transistor. [16]
8.a) b)
Explain CMOS fabrication using N well process? Explain BICMOS inverter with schematic and fabrication process.
Aj
nt
uW
4.
--ooOoo--
[8+8]
Code No: RR320405
RR
SET-3
1.
Write short notes for following: a)FPGA b) PLA c)GLA
d)standard cells.
.in
B. Tech III Year II Semester Examinations, December-January, 2011-2012 VLSI DESIGN (ELECTRONICS AND COMMUNICATION ENGINEERING) Time: 3 hours Max. Marks: 80 Answer any five questions All questions carry equal marks ---
[16]
Design a PLA schematic for function F=∑(2,4,8,11,13,15).
3.a) b)
Explain in detail about circuit design flow. Explain about Design verification tools.
4.a) b)
Explain in detail about plasma oxidation process. Explain about IC packing techniques.
5.a) b)
Implement the 2- Input AND gate with CMOS Logic and explain its working Derive the equation for IDS of saturated region for NMOS transistor. [16]
6.a) b)
Explain CMOS fabrication using N well process? Explain BICMOS inverter with schematic and fabrication process.
7.
Design a stick diagram for CMOS logic shown below. Y = ((A+B) (C+D))1.
[16]
Design a layout for CMOS NAND gate.
[16]
uW
Aj
nt
8.
[16]
or ld
2.
--ooOoo--
[8+8]
[8+8]
[8+8]
Code No: RR320405
RR
SET-4
.in
B. Tech III Year II Semester Examinations, December-January, 2011-2012 VLSI DESIGN (ELECTRONICS AND COMMUNICATION ENGINEERING) Time: 3 hours Max. Marks: 80 Answer any five questions All questions carry equal marks --1.a) b)
Explain in detail about circuit design flow. Explain about Design verification tools.
2.a) b)
Explain in detail about plasma oxidation process. Explain about IC packing techniques.
3.a) b)
Implement the 2- Input AND gate with CMOS Logic and explain its working Derive the equation for IDS of saturated region for NMOS transistor. [16]
4.a) b)
Explain CMOS fabrication using N well process? Explain BICMOS inverter with schematic and fabrication process.
[8+8]
5.
Design a stick diagram for CMOS logic shown below. Y = ((A+B) (C+D))1.
[16]
6.
Design a layout for CMOS NAND gate.
[16]
7.
Write short notes for following: a)FPGA b) PLA c)GLA
[8+8]
or ld
uW
d)standard cells.
Design a PLA schematic for function F=∑(2,4,8,11,13,15).
Aj
nt
8.
[8+8]
--ooOoo--
[16] [16]
