B. Tech III Year II Semester Examinations, December/January -2011-12 ADVANCED COMPUTER ARCHITECTURE (COMPUTER SCIENCE AND ENGINEERING, INFORMATION TECHNOLOGY)
Max. Marks: 80 Answer any five questions All questions carry equal marks ---
.in
Time: 3 hours
Discuss parallelism in uniprocessor systems. Explain architectural classifications schemes.
2.a) b)
Explain the principles of linear pipelining. Write a note on interleaved memory organization.
3.
Discuss in detail matrix multiplication on array processors.
[16]
4.a) b)
Discriminate loosely coupled and tightly coupled multiprocessor systems. Explain banyan networks with their features.
[16]
5.
Briefly discuss data flow computer architecture with suitable diagrams.
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or ld
1.a) b)
[16]
[16]
[16]
6.
Describe VLSI computing structure and arithmetic processor.
7.
Explain in detail image processing on massively parallel processing systems. [16]
8.a) b)
Give a detail note on Cray computer. Discuss the features of Hydra operating systems.
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[16]
[16]
Code No: RR320501
RR
SET-2
B. Tech III Year II Semester Examinations, December/January -2011-12 ADVANCED COMPUTER ARCHITECTURE (COMPUTER SCIENCE AND ENGINEERING, INFORMATION TECHNOLOGY)
Max. Marks: 80 Answer any five questions All questions carry equal marks ---
.in
Time: 3 hours
Discuss in detail matrix multiplication on array processors.
2.a) b)
Discriminate loosely coupled and tightly coupled multiprocessor systems. Explain banyan networks with their features.
3.
Briefly discuss data flow computer architecture with suitable diagrams.
or ld
1.
[16]
[16]
[16]
Describe VLSI computing structure and arithmetic processor.
5.
Explain in detail image processing on massively parallel processing systems. [16]
6.a) b)
Give a detail note on Cray computer. Discuss the features of Hydra operating systems.
[16]
7.a) b)
Discuss parallelism in uniprocessor systems. Explain architectural classifications schemes.
[16]
8.a) b)
Explain the principles of linear pipelining. Write a note on interleaved memory organization.
[16]
Aj
nt
uW
4.
******
[16]
Code No: RR320501
RR
SET-3
B. Tech III Year II Semester Examinations, December/January -2011-12 ADVANCED COMPUTER ARCHITECTURE (COMPUTER SCIENCE AND ENGINEERING, INFORMATION TECHNOLOGY)
Max. Marks: 80 Answer any five questions All questions carry equal marks ---
1.
.in
Time: 3 hours
Briefly discuss data flow computer architecture with suitable diagrams.
[16]
Describe VLSI computing structure and arithmetic processor.
3.
Explain in detail image processing on massively parallel processing systems. [16]
4.a) b)
Give a detail note on Cray computer. Discuss the features of Hydra operating systems.
[16]
5.a) b)
Discuss parallelism in uniprocessor systems. Explain architectural classifications schemes.
[16]
6.a) b)
Explain the principles of linear pipelining. Write a note on interleaved memory organization.
[16]
7.
Discuss in detail matrix multiplication on array processors.
[16]
8.a) b)
Discriminate loosely coupled and tightly coupled multiprocessor systems. Explain banyan networks with their features.
[16]
Aj
nt
uW
or ld
2.
******
[16]
Code No: RR320501
RR
SET-4
B. Tech III Year II Semester Examinations, December/January -2011-12 ADVANCED COMPUTER ARCHITECTURE (COMPUTER SCIENCE AND ENGINEERING, INFORMATION TECHNOLOGY)
Max. Marks: 80 Answer any five questions All questions carry equal marks ---
.in
Time: 3 hours
Explain in detail image processing on massively parallel processing systems. [16]
2.a) b)
Give a detail note on Cray computer. Discuss the features of Hydra operating systems.
3.a) b)
Discuss parallelism in uniprocessor systems. Explain architectural classifications schemes.
[16]
4.a) b)
Explain the principles of linear pipelining. Write a note on interleaved memory organization.
[16]
5.
Discuss in detail matrix multiplication on array processors.
[16]
6.a) b)
Discriminate loosely coupled and tightly coupled multiprocessor systems. Explain banyan networks with their features.
[16]
7.
Briefly discuss data flow computer architecture with suitable diagrams.
uW
Describe VLSI computing structure and arithmetic processor.
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RR. Set No. 2. II B.Tech II Semester Supplementary Examinations,May 2010 ... Code No: RR220801. RR. Set No. 2. (b) One kg of steam having a volume of 180 ...
3. Sketch the root locus of the given system GH(s) = K / (s+1) (s+3) (s+6) · (a) Find the break ... amplifier gain KA=5. Also find steady state error to unit ramp input.