DESIGN OF 10 BIT 100MS/s PIPELINED ADC

A PROJECT REPORT Submitted by

AMRITH SUKUMARAN (20043204) DINESH BABU.M.M

(20043220)

E.ILAMPARITHI

(20043227)

in partial fulfillment for the award of the degree of

BACHELOR OF ENGINEERING IN

ELECTRONICS AND COMMUNICATION ENGINEERING

MADRAS INSTITUTE OF TECHNOLOGY, CHROMEPET ANNA UNIVERSITY: CHENNAI 600 044 APRIL 2008

ANNA UNIVERSITY: CHENNAI 600 025

BONAFIDE CERTIFICATE Certified that this project report “DESIGN OF 10 BIT 100Ms Per Sec

PIPELINED ADC.” is the bonafide work of AMRITH SUKUMARAN (20043204) DINESH BABU.M.M

(20043220)

E.ILAMPARITHI

(20043227)

who carried the project work under my supervision.

SIGNATURE

SIGNATURE

DR.V.VAIDEHI

MR.D.MEGANATHAN

HEAD OF THE DEPARTMENT

SUPERVISOR Lecturer

Department of Electronics

Department of Electronics

Madras Institute of Technology

Madras Institute of Technology,

Chromepet,Chennai-600044

Chromepet, Chennai-600044

ACKNOWLEDGEMENT We are highly indebted to the Dean, Dr.P.KANAGASABAPATHY for providing with sufficient facilities that contributed to the success in this endeavor. We are very thankful to our Head of the Department, Dr.V.VAIDEHI, for her continuous encouragement during the project work. We would also like to specially thank Mr.M.KANNAN for his extended help in providing us with technical facilities.

With esteemed respect, we express our heart-felt gratitude to MR.D.MEGANATHAN, Lecturer, Department of Electronics and Communication for his guidance throughout the project. We sincerely thank our panel members, Mr.M.KANNAN, Ms. S.P.JOY VASANTHA RANI and R.KAYALVIZHI for their valuable suggestions for the improvement of our project. We also thank all the staff members of Department of Electronics and Communication for their encouragement throughout the project work. We express our affection and thanks to our parents and friends who stood as a supporting pillar in our rigorous course.

AMRITH SUKUMARAN (20043204) DINESH BABU.M.M

(20043220)

E.ILAMPARITHI

(20043227)

ABSTRACT Reduction of the power dissipation associated with high-speed sampling and quantization is a major problem in many applications. Analog switched-capacitor circuits play a critical role in mixed-signal, analog to digital interfaces, which could aid in power reduction. Their implementation makes them suitable for integration with complex, digital-signal-processing blocks in a compatible, low-cost technology–particularly CMOS processes.

In this work, the design of a 10 bit pipelined ADC using capacitor and stage scaling is proposed. Also, area saving architectures are used for both the sample and hold amplifier and the MDAC. The 10-bit resolution is achieved using 8 analog stages followed by a two-bit flash. A 1.5 bit per stage architecture is chosen to facilitate error correction and thereby digital error correction has also been applied.

KEY WORDS: Flip around, Scaling, Sample and Hold, 1.5 Bit, MDAC, Digital Error Correction, RSD algorithm, Switched Capacitor.

i

TABLE OF CONTENTS CHAPTER NO

1.

TITLE

PAGE NO

ABSTRACT

i

LIST OF FIGURES

iii

LIST OF ABBREVIATIONS

iv

INTRODUCTION

1

1.1 COMPARISON

1

1.1.1 WITH FLASH ADC

2

1.1.2 WITH DELTA-SIGMA ADC

3

1.2 PIPELINED ADC APPLICATIONS

4

1.3 WORKING OF PIPELINED ADC

5

1.4 IMPORTANT ADC TERMS

7

1.4.1 STATIC NON-LINEARITIES 1.4.1.1 OFFSET ERROR

7

1.4.1.2 GAIN ERROR

7

1.4.1.3 DNL

7

1.4.1.4 INL

8

1.4.2 DYNAMIC NON-LINEARITIES

2.

7

8

1.4.2.1 SNR

8

1.4.2.2 SFDR

8

1.4.2.3 THD

8

1.4.2.4 SNDR

9

1.4.2.5 ENOB

9

1.4.2.6 DYNAMIC RANGE

9

SAMPLE AND HOLD ARCHITECTURE

10

2.1 COMMMON PARAMETERS

10

2.1.1 AQUISITION TIME

10

2.1.2

APERTURE TIME

10

2.1.3

APERTURE JITTER

10

ii

2.1.4

DROOP RATE

10

2.1.5

PEDESTAL VOLTAGE

10

2.2 TOP PLATE SAMPLING

11

2.3 BOTTOM PLATE SAMPLING

12

2.4 GENERAL SAMPLE AND HOLD

14

2.5

FLIP AROUND SAMPLE AND HOLD

15

2.6

BOOTSTRAPPED SWITCHES

16

2.7

FFT COMPARISON BETWEEN THE THREE SWITCHES

18

2.8

CLOCK WAVEFORMS

20

2.9

TRANSIENT OUTPUT RESPONSE

21

2.10

OVERALL SHA ACHIEVED SPECIFICATIONS

3.

21

OPERATIONAL TRANSCONDUCTANCE AMPLIFIER 22 3.1 TOPOLOGY

22

3.2 TOPOLOGY SELECTION

23

3.2.1 ARCHITECTURE CHOSEN

24

3.2.2 POLE SPLITTING

25

3.2.3 SC-CMFB

26

3.2.4 DESIGN ISSUES OF AN OTA

28

3.2.5 BIASING

29

3.2.6 ACHIEVED RESULTS ACROSS TEMPRATURE AND CORNERS

30

3.2.7 PERFORMANCE COMPARISON

35

3.2.8 TRANSIENT OUTPUT

36

3.2.9 AC RESPONSE

36

3.2.10 TRANSIENT RESPONSE FOR UNIT STEP INPUT

37

3.2.11 CMRR AND PSRR

38

3.3 BANDGAP REFERNCE 3.3.1

CTAT AND PTAT iii

39 39

3.3.2 SIMULATION RESULTS

4.

43

MULTIPLYING ANALOG TO DIGITAL CONVERTER 44 4.1

1.5 BIT PER STAGE PIPELINED ADC

44

4.2

FLIP AROUND ARCHITECTURE

46

4.3

SWITCHES AND DIGITAL LOGIC

48

4.4

SIMULATION OF MDAC BLOCKS

51

4.5

AUTO-ZERO TECHNIQUE

52

4.6

INTEGRATION

52

4.7

STAGE SCALING

54

4.8

DIGITAL CORRECTION TECHNIQUE

56

5.

SIMULATION RESULTS

59

6.

CONCLUSION

64

7.

REFERENCES

65

iv

LIST OF FIGURES Figure No. 1.1

Figure Name

Pg.No

ADC CHOICE VS FREQUENCY

1

AND RESOLUTION 1.2

PIPELINED ADC APPLICATIONS

5

1.3

OFFSET ERROR

7

1.4

GAIN ERROR

7

2.1

SAMPLE AND HOLD PARAMETER DEFINITIONS

10

2.2

TOP PLATE SAMPLING

11

2.3

FFT SPECTRUM a) TOP PLATE SAMPLING FFT

13

b) BOTTOM PLATE SAMPLING FFT

13

2.4

SAMPLE AND HOLD CIRCUIT IMPLEMENTATION 15

2.5

BOOTSTRAPPED ARCHITECTURE

16

2.6

BOOTSTRAPPED CIRCUIT IMPLEMENTATION

17

2.7

VOLTAGE WAVEFORMS AT SOURCE, DRAIN AND GATE RESPECTIVELY

2.8

18

FFT COMPARISON OF SWITCHES a) BOOTSTRAPPED SWITCH

18

b) NMOS SWITCH

19

c) CMOS SWITCH

19

2.9

CLOCK GENERATION

20

2.10

FFT OF SINE WAVE OUTPUT OF SHA

20

2.11

SAMPLED SINE WAVE OUPUT OF SHA

21

3.1

TWO STAGE OPERATIONAL TRANSCONDUCTANCE AMPLIFIER

23

3.2

SC-CMFB

27

3.3

SC-CMFB IMPLEMENTATION

28

3.4

TRANSIENT RESPONSE OF OTA

36

3.5

AC RESPONSE OF OTA

36

3.6

TRANSIENT RESPONSE FOR UNIT STEP INPUT a) 200 mV DIFFERENTIAL INPUT

37

b) 1V DIFFERENTIAL INPUT

37

v

c) 2V DIFFERENTIAL INPUT

37

3.7

COMMOM MODE REJECTION RATION OF OTA

38

3.8

POWER SUPPLY REJECTION RATION

3.9

a) PSSR +

38

b) PSSR –

38

BANDGAP REFERENCE GENERATION CIRCUIT IMPLEMENTATION

3.10

40

VARIATION OF REFERENCE VOLTGE WITH TEMPERATURE

3.11

43

VARIATION OF REFERENCE VOLTAGE WITH ± 10% SUPPLY VARIATION

43

4.1

1.5 BIT/STAGE PIPELINED ADC

45

4.2

FLIP AROUND ARCHITECTURE IN MDAC BLOCK 47

4.3

MDAC SECTION IMPLEMENTATION

48

4.4

SWITCH IMPLEMENTATION IN MDAC BLOCK

49

4.5

LOGIC DECODER USING NAND GATES

49

4.6

NAND GATE IMPLEMENTATION USING CMOS TRANSISTORS

50

4.7

CMOS INVERTER IMPLEMENTATION

50

4.8

TRANSMISSION GATE SWITCH

50

4.9

FIRST STAGE RESIDUE PLOT

51

4.10

SECOND STAGE RESIDUE PLOT

51

4.11

WHOLE PIPELINED ADC IMPLEMENTATION AFTER INTEGRATION

53

4.12

TWO STAGE FLASH ADC IMPLEMENTATION

53

4.13

TRANSIENT OUTPUT OF MDAC BLOCK

54

4.14

DIGITAL CORRECTION a) PROPAGATION OF THE RESIDUE VALUE AND ADSC OUTPUT OF THE IDEAL 10BIT PIPELINED ADC

b) DIGITAL CORRECTION ALGORITHM

vi

57

57

4.15

a) PROPAGATION OF THE RESIDUE VALUE AND ADSC OUTPUT OF THE 10BIT PIPELINED ADC WITH COMPARATOR OFFSET ERROR IN

5.1

STAGE 2 AND STAGE 7.

58

b)

58

DIGITAL CORRECTION ALGORITHM

RECONSTRUCTED RAMP SIGNAL USING IDEAL DAC

59

5.2

DNL PLOT

59

5.3

INL PLOT

60

5.4

RECONSTRUCTED SINE WAVE FROM IDEAL DAC

5.5

60

FFT SPECTRUM OF RECONSTRUCTED SINE WAVE

61

5.6

ENOB VS INPUT FREQUENCY

61

5.7

SFDR VS INPUT FREQUENCY

62

5.8

SFDR VS SAMPLING FREQUENCY

62

vii

Table No.

LIST OF TABLES

Pg No.

2.1

SAMPLE AND HOLD ACHIEVED SPECIFICATIONS

21

3.1

OTA1 ACHIEVED SPECIFICATIONS AT –55O C

30

3.2

O

30

O

OTA 1ACHIEVED SPECIFICATIONS AT 27 C

3.3

OTA1 ACHIEVED SPECIFICATIONS AT 85 C

31

3.4

OTA2 ACHIEVED SPECIFICATIONS AT –55O C

31

3.5

OTA2 ACHIEVED SPECIFICATIONS AT 27O C

32

3.6

O

OTA2 ACHIEVED SPECIFICATIONS AT 85 C O

32

3.7

OTA3 ACHIEVED SPECIFICATIONS AT –55 C

33

3.8

OTA3 ACHIEVED SPECIFICATIONS AT 27O C

33

3.9

OTA3 ACHIEVED SPECIFICATIONS AT 85O C

34

3.10

PERFORMANCE COMPARISON OF SAMPLE AND HOLD AMPLIFIER

35

4.1

STAGE SCALING FOR OTAS AND CAPACITORS

55

5.1

SUMMARY OF THE SIMULATED PERFORMANCE

63

viii

LIST OF ABBREVIATIONS ADC

ANALOG TO DIGITAL CONVERTER

CMFB

COMMON MODE FEEDBACK

DAC

DIGITAL TO ANALOG CONVERTER

DNL

DIFFERENTIAL NON-LINEARITY

ENOB

EFFECTIVE NUMBER OF BITS

FFT

FAST FOURIER TRANSFORM

INL

INTEGRAL NON-LINEARITY

MDAC

MULTIPLYING ANALOG TO DIGITAL CONVERTER

OTA

OPERATIONAL TRANSCONDUCTANCE AMPLIFIER

OPAMP

OPERATIONAL AMPLIFIER

PM

PHASE MARGIN

SHA

SAMPLE AND HOLD AMPLIFIER

THA

TRACK AND HOLD AMPLIFIER

SC

SWITCHED CAPACITOR

SC-CMFB

SWITCHED CAPACITOR CMFB

SNR

SIGNAL TO NOISE RATIO

SFDR

SPURIOUS FREE DYNAMIC RANGE

UGB

UNITY GAIN BANDWITH

V

VOLT

W

WATT

ix

CHAPTER 1 INTRODUCTION

In the present day technologies such as software defined radios, cell phones and most other digital equipment dedicated ADC is employed. Choosing the appropriate ADC depends on the application aimed at. Most ADC applications today can be classified into four broad market segments: (a) data acquisition, (b) precision industrial measurement, (c) voice-band and audio and (d) high speed. For low speed, instantaneous or burst mode applications, successive approximation register ADCs are the best candidates. For high-resolution applications such as FM stereo, computer audio, stereo compact disc (CD), digital-audio-tape (DAT), and DVD audio delta sigma ADCs are popular, as a resolution from 12 to 24 bit could be achieved. For those applications that require both high speed and a moderately high resolution (>8 bits), pipelined ADCs are the best-suited candidates. This trend is shown below [17];

Fig 1.1 ADC Choice VS Frequency and Resolution 1

Today, markets that require “high speed” ADCs include many types of instrumentation applications (digital oscilloscopes, spectrum analyzers, and medical imaging). Also requiring high-speed converters are video, radar, communications (IF sampling, software radio, base stations, set-top boxes, etc.), and consumer electronics (digital cameras, display electronics, DVD, enhanced-definition TV, and high-definition TV).

1.1 COMPARISON

1.1.1 WITH FLASH ADC

These are faster than pipelined ADCs and in fact the fasted known analog to digital converters. They have the added advantage that they do not have any latency delay unlike pipelined or delta sigma ADCs. That is, since all the input bits propagate parallely through only a single stage, all reach the output simultaneously involving only the comparator’s delay, which is usually negligible. Its main disadvantage is that area increases exponentially with resolution. A 2-bit flash needs 3 comparators, a 7-bit flash needs 27 –1 comparators. In general, an N-bit flash needs 2N-1 comparators. Hence higher resolutions become impractical to be implemented. Extremely fast 8bit flash ADCs do exist with sampling rates as high as 1.5Gsps. It is much harder to find a 10-bit flash, while a 12-bit (or above) flash ADCs are not commercially possible. This is simply because in a flash ADC the number of comparators increases by a factor of 2 for every extra bit of resolution; simultaneously, each comparator must be twice as accurate. In a pipelined, however, to a first order the complexity only increases linearly, not exponentially, with the resolution [17]. 2

1.1.2 WITH DELTA-SIGMA ADC

Delta sigma converters are converters that are capable of operating for lower bandwidth input signals. They are over sampling converters. Traditionally, over sampling/sigma-delta-type converters commonly used in digital audio have a limited bandwidth of about 22 kHz. Recently some high-bandwidth sigma-delta converters reached a bandwidth of 1MHz to 2MHz with 12 to 16 bits of resolution [17]. These specifications indicate very high-order sigma-delta modulators. Their main applications are in ADSL. A sigma-delta converter needs no special trimming/calibration, even for 16 to 18 bits of resolution. They also require no steep rolling-off antialias filter at the analog inputs, because the sampling rate is much higher than the effective bandwidth. Delta-Sigma converters trade speed for resolution. The need to sample many times to produce one final sample causes the internal analog components in the sigma-delta modulator to operate much faster than the final data rate. The digital decimation filter at the end takes care of decoding the bits. The fastest, high-resolution sigma-delta-type converters are not expected to have more than a few MHz of bandwidth in the near future. Like pipelined ADCs, delta-sigma converters also have latency. Hence deltasigma ADCs are used in low bandwidth and very-high resolution applications, whereas pipelined architectures are used for high bandwidth, high-resolution applications.

3

1.2 PIPELINED ADC APPLICATIONS

They are particularly useful where, low voltage, high speed and highresolution quantization is required. This feature makes it ideal for high volume telecommunications application such as various digital subscriber lines, digital signal processing at video rates, and for stand alone high-speed analog-to-digital converters. Unlike flash converters, for which component counts increase exponentially with converter resolution, the component counts of pipeline ADC converters increase linearly with resolution. Therefore, pipeline ADC converters are relatively compact, inexpensive, and power efficient. Accordingly, pipeline ADC's are widely used in portable signal processing apparatus.” The pipelined analog-to-digital converter has become a popular ADC architecture for use in high-speed applications such as CCD imaging, ultrasonic medical imaging, digital videos, cable modems, and fast Ethernets.” The fig 1.2 gives an idea of the applications corresponding to resolution (taken from [10]).

4

fig 1.2 Pipelined ADC Applications

1.3 WORKING OF PIPELINED ADC

Pipelined ADC operates on the principle similar to that of the long division method. The quotient maps to the digital output bits and the reminder to the residue. An analogy with the above can be provided step by step. First, dividend and divisor are taken. For example to divide 47 by 7; 6 -----7 | 47 42 ---5

5

This is in the decimal system (base 10). Here 6 correspond to the first bit and 5 correspond to residue. Multiply 5 by the base (10). 6.7 -----7 | 47 42 ---50 49 ---1

The above procedure is carried on until the desired resolution is achieved. The number of times the above division is carried on corresponds to the number of stages in the pipelined ADC. One can see that a small error in the subtraction or multiplication could lead to gross errors at the output (especially for high resolutions).

Generally, 1.5 bit per stage pipelined architecture is employed for achieving better resolution and meet the design specification wit ha relatively easier design complexity. Here, 1.5 bit refers to the overlapping of one bit between adjacent stages (each of which would produce a 2 bit output). This added redundancy is popularly called digital correction.

6

1.4 IMPORTANT ADC TERMS

1.4.1 STATIC NONLINEARITIES

1.4.1.1 OFFSET ERROR It is the amount by which the transfer function curve gets offset initially. It can be corrected by adding the offset to the input.

fig 1.3 Offset Error 1.4.1.2 GAIN ERROR It is the amount by which the final value deviates from the ideal final value, due to deviation of the practical slope of the transfer function from the ideal slope.

fig 1.4 Gain Error

1.4.1.3 DIFFERENTIAL NON-LINEARITY (DNL) It is the amount the actual step size deviates from the ideal step size. It must usually be within +/- 1 LSB to avoid missing codes.

7

STEP SIZE (K) - IDEAL STEP (K)

DNL(K) =------------------------------

--(1.1)

IDEAL STEP (K)

1.4.1.4 INTEGRAL NON-LINEARITY (INL) It is cumulative summation of DNLs till any particular code, for which the INL is to be found. This must be within +/-0.5 LSB. K-1 INL(K)=∑ DNL(I) I=1

--(1.2)

1.4.2 DYNAMIC PARAMETERS

1.4.2.1 SNR - Signal-to-noise ratio defined as; sig power

SNR= 10log------------

-- (1.3)

noise power

where noise power does not include the harmonics and dc.

1.4.2.2 SFDR - Spurious free dynamic range SIGNAL POWER

SFDR = -------------

-- (1.6)

LARGEST SPUR

1.4.2.3 THD - Total harmonic distortion TOTAL DISTORTION POWER

THD = -----------------------

-- (1.7)

SIGNAL POWER

By convention, total harmonic distortion power consists of 2nd through 7th harmonic.

8

1.4.2.4 SNDR (SINAD) - Signal-to-(noise + distortion) ratio Same as SNR except for the fact that, noise power includes the harmonics but not dc.

1.4.2.5 ENOB - Effective number of bits SNDR(dB)-1.76dB

ENOB=-----------------

-- (1.4)

6.02dB

1.4.2.6 DR - Dynamic range PEAK SIGNAL POWER

DR = ------------------

(by varying input amplitude) -- (1.5)

NOISE POWER

9

CHAPTER 2 SAMPLE AND HOLD ARCHITECTURE 2.1 COMMON PARAMETERS 2.1.1 Acquisition Time (taq): The time for the storage capacitor voltage to track the input to within a specified precision (e.g.: within 0.1% Of input or 10-bit accuracy) immediately after a full-scale transition of the input voltage. 2.1.2 Aperture Time (ta): The time between the hold clock edge and the opening of the sampling switch. 2.1.3 Aperture Jitter (∆ ∆ta)): The uncertainty (jitter) in the aperture time for successive samples of the input. 2.1.4 Droop Rate: The rate of leakage of the hold-capacitor in the hold mode. dVout DROOP RATE = -----dt 2.1.5 Pedestal voltage: The output voltage error resulting from the clock feed through and channel charge dump of the sampling switch for the transition from sample mode to hold mode. The above terms are shown pictorially below [12]

fig 2.1 Sample And Hold Parameter Definitions

10

2.2 TOP PLATE SAMPLING

A sample NMOS top-plate sampling switch is shown below [3];

Fig-2.2Top plate sampling A switch is mostly designed to be used in two states ON (drain to source resistance = 0) and OFF (drain to source resistance = ∞). Usually one uses either NMOS or PMOS transistors as switches. However they limit the swing (and thereby for the output). Thus transmission gates are used, which will give a better swing as both PMOS and NMOS are connected in parallel here. The above arrangement is called a TOP PLATE SAMPLING circuit. When a switch is used in a circuit as shown above there are a lot of subtle problems associated with that. When Vg is high, the input is sampled to the capacitor at the output, in approximately 5RC constants. Depending on how fast Vo has to come to at least 99% of Vi, one can use the formula as shown below. Vo(t) = Vf(1-exp(-Ts/RC))

---(2.2)

where, Vf is the required final value, Ts is the required settling time and R is the on-resistance of the MOSFET. From the above expression one can choose the output to settle within any particular error and within a particular time by choosing a proper RC value.

11

When the switch is closed, it stores some charge in it due to the application of input at one end. However a problem arises when the switch is operating in its off phase. Once the switch is opened it spits out its stored charge (in the channel) on either side, both from the drain to the left and the source to the right. Since there is a fixed voltage source to the left the charge spitted towards the right dominantly changes the circuit’s output voltage by adding extra charge to the sampling capacitor. During clock transitions or on applying high-frequency clocks, the gate to drain capacitance appears to be a short to the clock and thus is directly coupled to the output, which leads to an error in the output voltage called clock-feed through. A detailed analysis of these can be found in [2].

2.3 BOTTOM PLATE SAMPLING This technique avoids some of the problems associated with the above technique [1]. Here two switches are used as shown below.

Fig2.2 Bottom plate sampling Bottom plate sampling is achieved by operating the switch connected to the bottom plate of the capacitor at an earlier clock than that near the input switch. Hence the bottom plate switch would open before the top plate switch opens thereby preventing charge leakage to the ground. This technique helps in improving the switch linearity as it prevents major loss of charge. 12

A comparison of the linearity of the two switches is shown below.

a) TOP PLATE SAMPLING FFT

b)BOTTOM PLATE SAMPLING FFT Fig2.3 a,b

13

2.4 GENERAL SAMPLE AND HOLD ARCHITECTURE

On writing the charge balance equations with respect to any one of the virtual ground node (say +). The vcmo and vcmi get cancelled while writing the equations, hence they can be neglected. At the nth instant; net charge during phi1: (C1 * (-Vin(n-1))) + C2 * 0;

--(2.3)

Net charge during phi2: C1 * 0 + C2 * (-Vout(n));

--(2.4)

By law of conservation of charges: Net charge during phi1 = Net charge during phi2;

--(2.5)

C1 * Vin(n-1) = C2 * Vout(n);

--(2.6)

Converting it to z-domain; C1*Vin(Z)*Z^-1 = Vout(Z) * C2;

--(2.7)

Thus, |Vout(Z)/Vin(Z)| = C1 / C2.

--(2.8)

For a sample and hold circuit C1 is taken to be equal to C2, thus a unity closed loop gain is achieved. The switches across the feedback capacitors are just to make the charge across the feedback capacitor zero; else it will keep accumulating with every cycle and would become a switched capacitor integrator instead. There are also auto-zeroing techniques employed in these types of circuits. [1, 6, 8] The disadvantage with the above circuit is that it uses two capacitors (one for input sampling and other for feedback). Usually capacitors consume a large area in chips and hence there is a need to either decrease its value or lessen the number of capacitors used. The second one is achieved using a flip around architecture. 14

2.5 FLIP AROUND SAMPLE AND HOLD ARCHITECTURE:

Here, the same capacitor acts as both the input sampling and the feedback capacitor. That is, during one phase it samples the input and during the next phase it goes into the feedback mode. The above can be better understood with help of the diagram shown below. During phi1, input voltage gets sampled across the capacitor C. The switch in the feedback loop would be in the open state thus disconnecting the output from the input. During phi2 the capacitor enters into the feedback mode and thus Vin is passed on to Vout. Since both the phases involve one and the same capacitor the gain as per eq (2.8) is unity. The above has the additional advantage of no having to reset the charge in the capacitor every time [1, 3, and 8].

Fig2.4 Sample and hold circuit implementation 15

2.6 BOOTSTRAPPED SWITCHES

MOS switches introduce more harmonics unlike perfectly ideal switches. The problem here is the nonlinearity introduced in the signal due to the fact that the drain to source resistance of a MOSFET is a function of the input signal amplitude. If gds is the output drain to source transconductance, then, Gds = k * (Vg – Vs – Vt);

--(2.9)

Therefore, Gds = k * (Vclk – Vin – Vt)..

--(2.10)

because the clock is fed to the gate and the input to the source. Hence the output resistance is a function of the input signal amplitude [1, 3]. Boot-strapping technique is used to avoid the above nonlinearity. The idea behind this technique is that a constant voltage is maintained between the source and gate of the MOSFET. This is achieved by placing a capacitor between those terminals and making them hold a constant charge and thereby maintain a constant voltage during the sample phase. Hence there is a constant voltage difference between the source and the gate.

Fig2.5 bootstrapped architecture

16

M11 is the transistor to be implemented as the switch. Idea here is to maintain a constant dc voltage difference between the source and gate terminals of M11. During phid M12 and M3 is ON. And thus VDD is stored across C3. M8 is in OFF state. M10 and M7 are ON. Hence M9 and M11 are OFF. During phi M12, M3 and M4 are OFF. One end of C3 is connected to the gate of M11 through M8 (which is ON). Hence M9 is also ON and the signal appears at the other end if C3. If C3 is chosen to be large enough (at least 6 times the parasitic caps associated with those nodes). The abov e constraint is to ensure that the Vdd voltage stored across C3 does not discharge within a phase. C1 and C2 must be chosen large enough to switch on M1 and M2. M7 is actually not necessary but is just to make M10 see a lesser voltage difference between its source and drain terminals. The W/L ratios of the transistors are not that critical and they can be chosen to be of the minimum size and ratio [1]. Switch comparison is shown in figure (2.7(a,b,c)). Its implementation is shown below.

Fig2.6 Bootstrapped circuit implementation

17

Fig2.7 Voltage waveforms at source gate and drain respectively

2.7 FFT COMPARISON BETWEEN THE THREE SWITCHES (a) BOOTSTRAPPED SWITCH

18

(b) NMOS SWITCH

(c) CMOS SWITCH

fig-2.8(a,b,c) FFT comparison of switches While the NMOS switch is the least linear, the bootstrapped switch is clearly more linear than the CMOS switch.

19

2.8 CLOCK WAVEFORMS Non-overlapping clocks are necessary for the proper operation of almost all circuits. The clock signals generated are as shown below.

Fig2.9 Phi1, phi1a, phi2, phi2a waveforms, respectively. Clock generation

Fig2.10 FFT of the sine wave output of SHA

20

2.9 TRANSIENT OUTPUT RESPONSE

Fig2.11 Sampled sine wave output from SHA

2.10 OVERALL SAMPLE AND HOLD ACHIEVED SPECIFICATIONS PARAMETER

RESULTS

Feedback Factor

0.96

Closed Loop Gain

1.00

Sampling Frequency

100MHz

SNR

69.06dB

SFDR

81.95dB

Input swing (differential)

2V

Output swing (differential)

2V

Total Power Dissipation

5.07 mW.

Table 2.1 Sample And Hold achieved specifications 21

CHAPTER 3 OPERATIONAL TRANSCONDUCTANCE AMPLIFIER.

3.1 TOPOLOGY There are four OTA architectures - differential OTA, two stage OTA, telescopic cascode and folded cascode OTAs. The best topology for an OTA is highly dependent on the desired application. In the single stage differential OTA architecture, high bandwidth can be obtained as the whole system can be approximated to a single pole. Compensation is usually not required. However, low gain with a reasonable output swing could be achieved. In the folded cascade topology the input common mode range can be greatly improved as input pair would usually be a PMOS with only about two to three transistors between rails. Hence better bandwidth can be achieved along with a better output swing too. But the gain would be lesser than that of the differential topology. In the single stage telescopic cascaded architecture, a very high gain and bandwidth could be got. However the input and output signal swings would be drastically reduced due to the higher number of transistors between the rails. In the two stage architecture, higher gain and a reasonable bandwidth could be obtained. However, using compensation techniques bandwidth could be drastically improved. The output stage swing is also improved due to the common source second stage. The second stage further acts as a buffer, since it converts a high impedance output node to a relatively lower impedance output node.

22

3.2 TOPOLOGY SELECTION The OTA used to implement the sampling and amplifying amplifier is the most important component of this design. The two critical design specifications that need to be considered in the design of this OTA are OPEN LOOP DC GAIN and SETTLING TIME. Settling time is directly related to the unity-gain frequency of the amplifier. The op-amp is fully differential. It was found that an open loop gain of at least 66 dB and bandwidth of at least 600 MHz is required to maintain a good SNR [18].

As a two stage topology with first stage being a telescopic cascode and second stage a simple CS (common source) amplifier meets the required specifications, it is chosen. The schematic is shown below.

Fig3.1Two stage Operational Transconductance Amplifier

23

3.2.1 ARCHITECTURE CHOSEN Reason for choosing this topology is because of the higher gain and higher output swing. Sample and hold needs to have a very high output swing in order to handle higher input signals. Hence the disadvantage of telescopic architecture of less swing is overcome by using a 2nd stage with lesser gain. Higher open loop gain increases the IIP3 (Input referred Interception Point of 3rd harmonic with the fundamental) point and thereby reduces the signal distortion due to harmonics. Also, since the maximum sampling rate is 100MS/s, the minimum time period of the clocks is 10ns. The bias current for the input differential pair would be provided using current mirrors mirroring from an off-chip current source. The bias to the gates of the cascade transistors would be provided using biasing networks. The bias current of the input differential stage was taken as 450uA and that of the output cascade transistors was chosen to be 700uA. The gain of the total amplifier is given by [16], A = A1 * A2

-- (3.1)

A1 = gm1 * (R1),

-- (3.2)

Where, R1 = (((gm3*ro3*)*ro1 || ((gm5*ro5)*ro7)))

-- (3.3)

gm1= Transconductance of the input signal transistor A2 = gm12 * (R2), Where, R2 = (ro12 || ro13)

-- (3.4)

gm12 = Transconductance of second stage input transistor The Unity gain Bandwidth of the amplifier is given by, UGB = gm1/Cc

-- (3.5)

24

3.2.2 POLE SPLITTING Two stage amplifiers has poor phase margin due to multiple poles, which comes inside the UGB frequency. Also parasitic capacitances in the first stage output node and the second stage input node is affected by miller effect. For lesser static error there should be higher phase margin. So pole splitting technique is used where a capacitor is introduced between the first and second stage. The capacitor affected by the miller effect will have large capacitance when seen from input side. The introduction of compensation capacitor moves the dominant pole to lesser frequency and also moves the second pole to much higher frequency. It also introduces a positive zero, which reduces the phase margin. To compensate that, a resistor is used in series with the compensation capacitor and by appropriately selecting the resistor; the zero is moved into left half plane, which increases the phase margin. The transconductance of second stage needs to be 3 times that of first stage to ensure a phase margin of 72°. The value of compensation capacitance and resistor is found using the following formula. Without the introduction of compensation capacitor Cc, the first and second dominant pole locations are [16],

ωp1 = 1/ (R1*C1),

--(3.6)

Where C1 = Total capacitance at the output node of the first stage

ωp2 = 1/(R2*CL),

--(3.7)

Where CL = Load capacitance. Assuming CL >> C2, parasitic capacitances at the output node. After the introduction of compensation capacitor Cc, the pole locations are,

ωp1 = 1/ (A2*R1*Cc)

--(3.8)

25

ωp2 = gm12 / (CL)

-- (3.9)

The compensation capacitor also introduces a zero given by,

ωz = gm12 / (CL)

--(3.10)

But the zero introduced is in the right hand side of the plane, which decreases the phase margin. Hence, a compensation resistor Rc is introduced. The location of zero after the introduction of resistor is given by,

ωz = 1 / ((1/gm12)-Rc) * CL)

--(3.11)

By selecting the resistor value such that, Rc < 1 / (gm12)

--(3.12)

The location of zero is moved into left half plane, which becomes a negative zero, which increases the phase margin. The value of Cc is selected from the equation, Cc = gm1 / (UGB)

-- (3.13)

3.2.3 SWITCHED CAPACITOR COMMON MODE FEEDBACK. (SCCMFB) All differential amplifiers employ a common mode feedback to ensure stable output operating points. The SC-CMFB circuit effectively increases the common mode gain of the OTA, without decreasing the differential gain. This is the unique feature that differentiates an SC-CMFB from a resistive CMFB. In a resistive CMFB the averaging resistors appear parallel to the output resistance of the OTA thereby decreasing the OTA’s differential gain. A simple illustration of switched capacitor CMFB is shown in fig 3.2.

26

The capacitor is used to store fixed charge during phi1 and acts as a battery. The capacitors first average out the output common mode voltage [14]. Vav = (Voutp + Voutm) / 2;

--(3.14)

This charge is stored across the output capacitors. The circuit operation could be being discussed in 2 phases, phi1 and phi2. The charge stored across the capacitor during phase phi1 is given by, Vbat = Vcmo – Vb;

--(3.15)

Where, Vcmo = Actual output common mode voltage Vb = the actual bias voltage of the transistor which is being controlled. During phi2, Vcmfb which goes to the gate of the transistor being controlled is given by, Vcmfb = Vav – Vbat

--(3.16)

fig-3.2 SC-CMFB Thus the output common mode voltage is averaged during phase phi2 and compared with the desired output common mode voltage during phase phi1. It is then used to controls the gate of the transistor through negative feedback [14]. For instance, if there is an increase in the common

27

mode output voltage due to some reason, then the CMFB’s output increases which decreases the current flow thereby decreasing the output common mode. Thus a negative feedback loop is formed. The switches are designed using transmission gate switches. Its implementation is shown below [14].

fig-3.3 SC-CMFB implementation

3.2.4 DESIGN ISSUES OF AN OTA Length of the transistor and over drive voltages are chosen as per the requirement to get higher gain and bandwidth. For getting higher transconductance lower overdrive voltage are used and for higher resistance length of the transistor is increased. The transistors near the output node need to have minimum lengths and widths so that the parasitic capacitances might not add to the output node, which might cause frequency degradation. gm = 2 * I / Vov,

--(3.17)

Where Vov = Overdrive voltage. Tail current of the first stage is fixed at 700 uA. That is, each branch of the first stage carries 350 uA. The second stage current is fixed at 850 uA

28

through each branch. The sizing of the transistors was made to satisfy the current requirement and the required swing. The tail transistor is designed using two transistors in cascode so as to increase the resistance at the virtual ground node using the cascoding effect of the transistor. Transistor lengths and overdrives are chosen as shown in the table below. TRANSISTOR

LENGTH

OVERDRIVE

M1,M2

180 nm

100mV

M3,M4

900 nm

200mV

M5,M6

540 nm

250mV

M7,M8

720 nm

250mV

M12,M13

180nm

100mV

M14,M15

360nm

150mV

3.2.5 BIASING

The biasing circuits are implemented using MOS transistors. The gate of the transistor that is to be biased must be biased using a bias circuit, whose output also has the same number of transistors with below the output node. Otherwise matching between the biasing circuit and the to-be-biased circuit will not match and hence could lead to unmatched variations across corners and temperatures [6, 15,16]. In the above work only two biases were needed to be generated, as the other two was supplied by SC-CMFB. The biasing circuit consumes about 300uW power.

29

3.2.6 ACHIEVED RESULTS ACROSS TEMPRATURE AND CORNERS Achieved performance of the OTA1 across the corners (temp=-550C) Sl

Specifications

TT

SS

FF

SNFP

FNSP

1.

Open-loop Gain(dB)

84.21

86.24

77.86

84.00

84.47

2.

UGB(Hz)

1.29G

970M

1.55G

1.23G

1.1G

3.

Phase Margin

500

570

490

490

500

4.

Output Swing

2Vp-p

2Vp-p

2Vp-p

2Vp-p

2Vp-p

5.

PSRR+(dB)

86.07

74.0

99.87

84.08

81.6

6.

PSRR(-) (dB)

82.01

76.40

58.2

62.1

73.27

7.

CMRR (dB)

89.23

70.56

89.66

82.13

88.14

8.

Input referred

53.3

15.56

98.44

84.16

11.2

noise(at 100 MHz)

nV/ Hz

µV/ Hz

nV/ Hz

nV/ Hz

µV/ Hz

Table 3.1 OTA1 Achieved Specifications At –55o C Achieved performance of the OTA1 across the corners (temp=270C) Sl.

Specifications

TT

SS

FF

SNFP

FNSP

1.

Open-loop

77.6

81.9

72.04

79.49

79.07

Gain(dB) 2.

UGB(Hz)

1.1G

755M

1.37 G

740M

755M

3.

Phase Margin

580

650

560

640

650

4.

Output Swing

2Vp-p

2Vp-p

2Vp-p

2Vp-p

2Vp-p

4.

PSRR+(dB)

71.1

57.01

78.8

62.73

64.47

5.

PSRR (-) (dB)

77.2

72.31

78.8

71.13

71.27

6.

CMRR(dB)

74.8

65.07

80.72

69.33

70.97

7.

Input referred-

3.66

3.79

3.47

3.11

3.40

noise(at 100 MHz)

nV/ Hz

nV/ Hz

nV/ Hz

nV/ Hz

nV/ Hz

Table 3.2 OTA1 Achieved Specifications At 27o C

30

Achieved performance of the OTA1 across the corners (temp=850C) Sl

Specifications

TT

SS

FF

SNFP

FNSP

1.

Open-loop Gain(dB)

71.18

76.66

68.13

76.43

76.04

2.

UGB(Hz)

660M

505M

747M

663M

634M

3.

Phase Margin

600

670

540

590

580

4.

Output Swing

2Vp-p

2Vp-p

2Vp-p

2Vp-p

2Vp-p

4.

PSRR+ (dB)

79.38

77

76.01

65.73

49.06

5.

PSRR (-) (dB)

98.42

78.29

76.05

77.23

66.21

6.

CMRR(dB)

79.2

78.4

82.13

89.48

82.18

7.

Input referred

15.48

80.82

81.04

46.04

64.28

noise(at 100 MHz)

nV/ Hz

nV/ Hz

nV/ Hz

nV/ Hz

nV/ Hz

Table 3.3 OTA1 Achieved Specifications At 85o C

Achieved performance of the OTA2 across the corners Sl.

Specifications

TT

SS

FF

SNFP

FNSP

1.

Open-loop Gain(dB)

75.83

81.44

73.60

79.02

79.74

2.

UGB(Hz)

710M

620M

1.28G

1.03G

994M

3.

Phase Margin

700

740

620

680

670

4.

Output Swing

2Vp-p

2Vp-p

2Vp-p

2Vp-p

2Vp-p

5.

PSRR+ (dB)

81.71

64.44

69.07

74.80

81.06

6.

PSRR (-) (dB)

82.14

77.04

78.12

67.11

79.74

7.

CMRR(dB)

80.30

78.65

79.64

86.31 B

78.41

8.

Input referred

63.3

65.56

88.44

64.16

51.2

noise(at 100 MHz)

nV/ Hz

µV/ Hz

nV/ Hz

nV/ Hz

µV/ Hz

No

Table 3.4 OTA2 Achieved Specifications At –55o C

31

Achieved performance of the OTA2 across the corners Sl

Specifications

TT

SS

FF

SNFP

FNSP

1.

Open-loop Gain(dB)

74.34

79.14

70.50

77.20

78.40

2.

UGB(Hz)

660M

605M

1.08G

990M

904M

3.

Phase Margin

700

720

640

690

680

4.

Output Swing

2Vp-p

2Vp-p

2Vp-p

2Vp-p

2Vp-p

5.

PSRR+ (dB)

84.1

74.4

67.7

76.0

88.6

6.

PSRR (-) (dB)

72.4

87.41

88.2

76.14

89.4

7.

CMRR (dB)

81.0

88.5

89.4

88.1 B

88.1

8.

Input referred

43.3

45.56

48.44

44.16

41.2

noise(at 100 MHz)

nV/ Hz

µV/ Hz

nV/ Hz

nV/ Hz

µV/ Hz

Table 3.5 OTA2 Achieved Specifications At 27o C

Achieved performance of the OTA2 across the corners Sl

Specifications

TT

SS

FF

SNFP

FNSP

1.

Open-loop

71.14

76.4

66.0

71.0

71.40

Gain(dB) 2.

UGB(Hz)

600M

650M

980M

890M

804M

3.

Phase Margin

720

760

680

710

780

4.

Output Swing

2Vp-p

2Vp-p

2Vp-p

2Vp-p

2Vp-p

5.

PSRR+ (dB)

88.11

84.14

77.17

96.10

98.16

6.

PSRR (-) (dB)

77.14

77.11

88.12

86.41

79.74

7.

CMRR(dB)

86.40

83.55

86.44

85.41

84.41

8.

Input referred

33.3

35.56

38.44

34.16

31.2

noise(at 100 MHz)

nV/ Hz

µV/ Hz

nV/ Hz

nV/ Hz

µV/ Hz

Table 3.6 OTA2 Achieved Specifications At 85o C

32

Achieved performance of the OTA3 across the corners Sl

Specifications

TT

SS

FF

SNFP

FNSP

1.

Open-loop Gain(dB)

75.03

77.44

63.60

69.02

69.74

2.

UGB (Hz)

680M

600M

900M

733M

794M

3.

Phase Margin

720

780

690

690

700

4.

Output Swing

2Vp-p

2Vp-p

2Vp-p

2Vp-p

2Vp-p

5.

PSRR+ (dB)

91.71

94.44

91.07

94.80

91.06

6.

PSRR (-)

92.4

87.04

88.12

77.11

89.74

7.

CMRR(dB)

85.30

75.65

75.64

85.31 B

75.41

8.

Input referred

33.3

35.56

38.44

34.16

31.2

noise(at 100 MHz)

nV/ Hz

µV/ Hz

nV/ Hz

nV/ Hz

µV/ Hz

Table 3.7 OTA3 Achieved Specifications at –55o C

Achieved performance of the OTA3 across the corners Sl

Specifications

TT

SS

FF

SNFP

FNSP

1.

Open-loop

72.03

75.44

61.60

75.02

75.74

Gain(dB) 2.

UGB (Hz)

600M

660M

960M

763M

764M

3.

Phase Margin

720

780

620

750

750

4.

Output Swing

2Vp-p

2Vp-p

2Vp-p

2Vp-p

2Vp-p

5.

PSRR+ (dB)

98.71

98.44

81.07

84.80

81.06

6.

PSRR (-)

94.5

84.54

84.52

74.51

84.54

7.

CMRR(dB)

96.30

96.65

96.64

86.31 B

96.41

8.

Input referred

23.3

25.56

28.44

24.16

21.2

noise(at 100 MHz)

nV/ Hz

µV/ Hz

nV/ Hz

nV/ Hz

µV/ Hz

Table 3.8 OTA3 Achieved Specifications At 27o C

33

Achieved performance of the OTA3 across the corners Sl

Specifications

TT

SS

FF

SNFP

FNSP

1.

Open-loop

68.03

72.44

66.60

69.02

69.74

Gain(dB) 2.

UGB (Hz)

550M

380M

760M

703M

784M

3.

Phase Margin

750

790

720

750

780

4.

Output Swing

2Vp-p

2Vp-p

2Vp-p

2Vp-p

2Vp-p

5.

PSRR+ (dB)

88.71

97.74

87.77

74.70

71.76

6.

PSRR (-)

64.5

64.64

86.52

76.51

64.54

7.

CMRR(dB)

90.50

95.65

95.64

86.51 B

66.41

8.

Input referred

28.3

28.56

8.44

34.16

11.2

noise(at 100 MHz)

nV/ Hz

µV/ Hz

nV/ Hz

nV/ Hz

µV/ Hz

Table 3.9 OTA3 Achieved Specifications At 85o C

34

3.2.7 PERFORMANCE COMPARISON AMONG PREVIOUS WORKS DONE IN PIPELINED ADC OF SHA Sl.

Specifications

Byung-

Kazutaka Honda

This Work

Moo Min- 2007 [11]

No

2003 [7] 1.

Resolution

10-bit

10-bit

10-bit

2.

Supply Voltage

2.7V

1.0V

1.8V

3.

Technology used 180nm

90nm

180nm

4.

Differential

2Vp-p

0.8Vp-p

2Vp-p

OTA

Gain

Folded cascode

Two-stage

Architecture

Boosted

Used

Telescopic

THA

Flip-around

Capacitive

Flip-around

Architecture

Architecture coupling technique Architecture

output swing 5.

6.

used

based on Flip-around Architecture 11mW

9.

Power

(S/H

Circuit

5.5mW(THA +

5.07mW(THA+

Biasing circuit)

Biasing circuit)

only)

10.

Speed

80MS/sec

100MS/sec

100MS/sec

11.

Open-loop Gain

90Db

74dB

77.6dB

12.

UGB

1GHz

1.5GHz

1.10GHz

Table 3.10 Performance Comparison of Sample and Hold Amplifier

35

3.2.8 TRANSIENT OUTPUT

Fig3.4 Transient response of OTA 3.2.9 AC RESPONSE

Fig3.5 AC response of OTA

36

3.2.10 TRANSIENT RESPONSE FOR UNIT STEP INPUT

a) 200mV differential input

b) 1V differential input

c) 2V differential input Fig3.6 a,b,c Transient response for unit step input

37

3.2.11 CMRR AND PSRR

Fig3.7 Common mode rejection ratio of OTA

POWER SUPPLY REJECTION RATIO (+,-) (respectively)

a) PSRR +

b) PSRR Fig3.8 a,b Power supply rejection ratio of OTA 38

3.3 BANDGAP REFERENCE VOLTAGE GENERATION For a circuit to operate inside a chip, reference voltages are normally generated inside the chip. The generated reference voltage must be independent of both temperature and process defying which the circuit won’t work under change in temperature and process. Bandgap reference voltage generation is such a technique by which a reference voltage independent of temperature, supply and process is generated.

3.3.1 PTAT AND CTAT CTAT (complementary to absolute temperature) varies inversely to temperature variations. The base emitter voltage of a BJT is a CTAT source which varies inversely to change in temperature. In circuit a BJT transistor is used for creating this CTAT source. PTAT (Proportional to absolute temperature) varies proportional to temperature variations. ∆VBE is one such source which varies proportional to temperature. Hence by combining these two in proper proportion, temperature insensitivity can be achieved. The ∆VBE is generated across the resistor between the OTA terminal and the BJT transistor [6, 16].

The base emitter voltage can be written as a sum of bandgap voltage of silicon (which is voltage at absolute zero obtained by extrapolating the curve from room temperature) and another function which is a function of temperature and varies complementary to its changes. The idea employed here is to cancel the one varying inversely with temperature with another one varying proportional to temperature. By doing so, bandgap voltage is tapped which is insensitive to temperature changes. Hence the name Bandgap reference voltage. 39

Typical value of bandgap voltage for silicon is 1.205 V. Hence in theory, output voltage is set to this value. But in practice it will be chosen slightly higher value to account for assumptions that collector current of BJT is insensitive to temperature. A basic architecture for implementing the circuit is shown in fig.3.9 [6] simple single stage differential pair OTA is used to maintain the potential at its input node without varying.

Fig3.9 Bandgap reference generation circuit implementation

40

The following formulas illustrate our ability to achieve temperature independency; 1) CTAT: VBE 1= η(kT/q)ln(Ic1/Is1)

--(3.18)

Where η=diode ideality factor, k = Boltzmann constant,

T = absolute temperature,q = charge

Ic1 = collector current

Is1 = reverse saturation current.

2) PTAT: (VBE1 – VBE2) = η(kT/q)ln(Is2/Is1)

--(3.19)

Assume Ic1 = Ic2, if Ae(Q2) = m*Ae(Q1), Is2 = m*Is1 ∆VBE = η(kT/q)ln(m)

3) CTAT + x*PTAT = TEMPRATURE INDEPENDENT

--(3.20)

4) FROM SIMULATIONS: fix I1 = 200uA;

I2 = 200uA

d(VBE1)/d(T) = -1.38m; ∆VBE = 0.1246 R1 = ∆VBE/I1 = 0.1246/200u = 623 R2 = (Vout – VBE1) / I2;

--(3.21)

Vout = VG0 + (r-n)kT/q;

--(3.22)

r = technology dependent curvature parameter. n = temperature power. Make r = n (by tweaking). Set Vout = 1.3V from the above. Also Vout = |VBE1| + R2*(∆VBE/R1) = (R2/R1)ln(m) * kT/q

41

--(3.23) --(3.24)

So, x = (R2/R1)ln(m);

--(3.25)

By simulations m = 64 d(Vout)/d(T) = 0 is needed; therefore (k/q)d(x)/d(T) = d(VBE)/d(T).

--(3.26)

Practically d(x)/d(T) (not = ) 0 because d(R2/R1)/d(T) (not = ) 0; Hence with simulator’s help set R1 and sweep R2 for various temperatures to get a temperature independent curve.

An OTA employed to force there input nodes equal. Aol = 28dB

UGB = 1.4GHz

power = 405uW.

Feedback nodes connected in such a way that negative feedback is stronger than positive feedback.

Due to the tweaking I1 and I2 changes and R1 too would be needed to be changed a bit. R1 = 650Ω R2 = 2.761KΩ m = 64

I1 = 196.9uA

Vout|27deg = 1.33V

I2 = 182.2uA

TOTAL POWER = 1.087mW

Output voltage variation due to temperature variation = about 31 PPM Output voltage variation due to power supply variation = about 72 PPM

42

3.3.2 SIMULATION RESULTS

TEMPEARUTE VARIATION OF REFERENCE VOLTAGE:

Fig3.10 Variation of reference voltage with temperature SUPPLY VARIATION

Fig3.11 variation of reference voltage with ± 10% supply

43

CHAPTER 4 MULTIPLYING DIGITAL TO ANALOG CONVERSION (MDAC)

Pipelined ADC is a modified form of Sub ranging ADC. It basically comprises of Multiplying DAC (MDAC), THA and comparator (sub ADC) blocks forming a single stage. Many such stages are pipelined to achieve higher resolution from lower resolution stages. The inter stage resolution of the sub ADC can be 1 bit or 2 bit or higher bits per stage resolution depending on the design criteria. The design of MDAC is the most challenging part as it involves in residue generation and amplification upon which later stages operate.

4.1 1.5 BIT/STAGE PIPELINED ADC

The architecture chosen for implementing 10bit pipelined ADC is a 1.5 bit per stage pipelined ADC. This architecture has been chosen to maximize efficiency in terms of chip area and speed. The choice of an optimum stage resolution is governed by two constraints, conversion rate and linearity. For the ADC, a conversion rate of 100 Ms/s was required. This corresponds to a conversion period of 10 ns which after being divided into two non overlapping clock phases by the clock generator, leaves an op-amp settling time of less than 5 ns. Furthermore, to get 10-bit resolution in the ADC, the op-amp open-loop gain must be high enough so that the inter stage gain is accurate to 10-bits. To meet these requirements, the minimum per stage resolution should be chosen. This minimizes the required inter stage gain and maximizes bandwidth (fixed gain-bandwidth product). On the contrary, it is necessary to have some redundancy in the intermediate digital 44

data to eliminate the effects of offsets within the ADC. Balancing these tradeoffs, a stage resolution of 1.5-bits is chosen. This resolution is implemented by having an inter stage gain of two with each stage producing three possible outputs. One bit of this output contributes to the final resolution of the ADC and the other 0.5-bit is redundant. Digital correction eliminates the redundancy and produces the final 10- bit word.

The sub ADC is implemented using flash architecture. In 1.5 bit sub ADC, only 2 comparators is used which makes it a 1.5 bit resolution instead of 2 bit in which case 3 comparators (2^(2)-1) are required. There are only 3 possible outputs (00, 01, and 10) instead of 4 possibilities in 2 bit flash ADC. Thus redundancy is introduced.

The following figure explains the operations of MDAC block employing 1.5 bit/stage sub ADC.

Fig4.1 1.5 bit/stage pipelined ADC Using a 1.5 bit/stage resolution implies 10 such MDAC blocks are needed to realize 10bit effective resolution of the ADC. In practice, last stages are replaced with 2 bit or higher resolution flash ADCs which reduces the total power requirement since it doesn’t involve OTA. 2 bit flash ADC is used in this architecture.

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4.2 FLIP AROUND ARCHITECTURE

Flip around architecture is being used to implement the MDAC block. In this architecture, two capacitors are used. During sampling phase input data is sampled across the two capacitors. During the next phase, one of the capacitor goes into feedback mode. By using this architecture, considerable amount of space is saved as same capacitor is being used for sampling in one phase and as feedback capacitor in second phase.

The function of MDAC block is to produce the residue in accordance with the comparator output. The design of MDAC is the most challenging part as it involves in residue generation and amplification upon which later stages operate. The residue is generated by first amplifying the signal and then performing subtraction operation on the signal by the reference signal. In 1.5 bit/stage architecture, one of the following three operations will be performed. Vres = 2*Vin – Vref

for

Vin > Vref/4

--(5.1)

= 2 *Vin

for -Vref/4 < Vin < Vref/4

--(5.2)

= 2*Vin + Vref

for

--(5.3)

Vin < -Vref/4

The MDAC block operation can be analyzed in two phases [8].

Phase I: In this phase, the MDAC block samples the incoming data into the two sampling capacitors.

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Phase II: In this phase, one of the capacitor goes to feedback where as second capacitor samples the reference voltage selected in accordance with the bits from comparator and the digital logic.

The following figure explains the operation of MDAC in two phases showing how one of the capacitor goes into feedback mode in one phase [3, 8].

Fig4.2Flip around architecture in MDAC block [8]

To maximize the power supply rejection ratio (PSRR) and to minimize even harmonic distortion, all analog signals are implemented differentially. Input data is sampled by the input sampling switches and also by the comparator. The comparator gives one of the three outputs depending on the input.

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The implementation of MDAC block along with comparator and digital logics are shown in figure.

Fig4.3 MDAC section implementation 4.3 SWITCHES AND DIGITAL LOGIC

The comparator decisions are used to select one of the three switches which select the reference voltage levels to be subtracted. The selection of switches is done using digital logic. The input sampling switches are implemented using BOOTSTRAPPED [3] switches to improve linearity for the signal path switch. Other switches are either realized using PMOS or NMOS or a transmission gate. The switch set is show in the following figure

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Fig4.4 Switch implementation in MDAC block The implementation of digital logic used in switch selection is shown in figure.

Fig4.5 Logic decoder using NAND gates The above diagram shows the digital logic implementation using NAND logic. Complementary signals of this is generated using NOR logic.

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NAND (and NOR) gates are realized using transistors as shown in the figure

Fig4.6 NAND gate implementation using CMOS transistors

Fig4.7 CMOS Inverter implementation

Fig4.8 Transmission gate switch implementation

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4.4 SIMULATION OF MDAC BLOCK MDAC block is tested for its residue plot by giving a slow varying ramp signal from - Vref to + Vref. The resulting residue plot for the first stage looks as shown in the figure.

Fig4.9 First stage residue plot When other MDAC blocks are cascaded with the first block, the residue plot of the later stage is as shown in figure.

Fig4.10 Second stage residue plot

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4.5 AUTO-ZERO TECHNIQUE As the time progresses, the offset error between the two input terminals of the OTA gets accumulated. This error significantly affects the output of MDAC section unless it is removed using suitable techniques. In the switches capacitor circuit, the OTA is operational in one phase and remains inactive during the other phase. This inactive phase can be used to cancel out the offset introduced in the OTA. The offset is cancelled by using a switch which shorts both the input terminals of the OTA.

4.6 INTEGRATION

The MDAC blocks designed and then they are replicated and integrated. The first and last stages differ slightly from the typical MDAC stage mentioned above. In the first stage, the SHA is configured for unitygain and no subtraction takes place. In the last stage, the ADC produces a full 2-bit word instead of a 1.5-bit word as is produced by the ADC in all other stages. The digital circuitry first aligns the ADC decisions of each stage with one another. Then, it adds the decisions together in a 1.5-bit/stage fashion and outputs a 10-bit digital word. Latch arrays are used to hold the signal of previous blocks till the signal traverses through all the stages. Ripple adder is used to add the bits and generate the 10-bit digital word.

The implementation is shown in the figure 4.11 in the following page.

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Fig4.11 Whole pipelined ADC implementation after integration The two bit flash ADC used in the last stage is show in the figure

Fig4.12 Two stage flash ADC implementation The transient output of the MDAC block for a dc input is shown in figure 4.13. 53

Fig4.13 Transient output of MADC block

4.7 STAGE SCALING

As one goes down the pipelined stages, the input referred noise reduces according to Friis Equation; Vinrefn=Vn1 + (Vn2/A1) + Vn3/(A1*A2) + Vn4/(A1*A2*A3*A4) + --(5.4) th

th

Where, Ai = gain of i stage and Vni = noise output voltage of the i stage From the above equation it can be clearly seen that the noise of the latter stages affect the input referred noise negligibly, due to the fact that, they are divided by the product of the gain of the previous stages. Hence the capacitor and OTA requirements of the last few stages could be relaxed, thereby saving power, but still maintaining the same performance. In the above work, the first stage sample and hold along with the first four stages MDAC consumes 65.5 percent of the net power, the next 2 stages consume 23.25 percent and the final 2 stages consume 11.25 percent of the net core analog power.

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The OTA design scaling is shown below; Sl. Specifications SHA No.

OTA-(14)

OTA-(5- OTA-(76) 8)

1.

77.6dB

77.6dB

74.34dB

72.03dB

0.96

0.48

0.46

0.44

1.1GHz

1.1GHz

660MHz 600MHz

2. 3. 4.

Open Loop gain (Aol) Feedback factor Unity-gain frequency Phase margin

58

o

58

o

62

5.

o

o

65 2Vp-p

Output 2Vp-p 2Vp-p 2Vp-p voltage swing 6. PSRR+ 71.1dB 71.1dB 72.92 79.92 7. PSRR 77.2dB 77.2dB 74.56 77.60 8. CMRR 74.8dB 74.8dB 72.97 70.02 3.66 13.79n 100.5 9. Input referred 3.66 thermal noise nV/ Hz nV/ Hz nV/ Hz nV/ Hz @ Nyquist 10. Power 5.07mW 5.07mW 4.40m W 1.80m W dissipation 11. Capacitor 1.35pF 1pF 600fF 400fF scaling Table 4.1 Stage Scaling For OTAs And Capacitors

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4.8 DIGITAL CORRECTION TECHNIQUE The advantage of 1.5bit/stage pipelined ADC, relaxes the accuracy of the analog modules. Adding one extra comparator in each stage relaxes the comparator accuracy. Redundant signed digit (RSD) algorithm ensures that the residue value will never enter the saturation range. The residue of any stage is governed by the following equations, Vresi = 2Vin + Vref if Vin <= 2Vin

if +

Vref 4

and B=00 --(5.5)

Vref Vref < Vin
= 2Vin - Vref if Vin>

Vref 4

and B=10 --(5.7)

where, Vresi is the residue of the ith stage, Vin is the input voltage, Vref is the reference voltage and B is the digital code produced by the ADSC of the ith stage .Each stage generates two digital bits as per the algorithm, by using overlap addition method the extra bit is removed from each stage is as shown in Fig 4.14(b) and Fig 4.15(b) respectively. Redundant signed algorithm and digital correction technique are used to correct the maximum of ±

VREF offset error 4

produced by any ADSC is illustrated in Fig 4.15(a). For example, if input of 0.3V is applied to the ideal 10-bit pipelined ADC and 10-bit pipelined ADC with comparator offset error in stage 2 and stage 7 is as shown in Fig.4.14(a) and Fig.4.15(a) respectively. The digital code and the residue values of each stage is illustrated in Fig.4.14 (a) & Fig 4.15(a) respectively. The residue propagation in figure 4.14(a) shows that the error produced in the particular stage is corrected in the forthcoming stages using RSD algorithm. The erroneous digital code produced by the ADCs is corrected by digital correction technique is as shown in Fig 4.15(b). The final digital output of the ideal pipelined ADC and the pipelined ADC

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with comparator offset are same as shown in Fig 4.14(b) and Fig 4.15(b) respectively. Hence it proves that the pipelined ADC is more robust for ±

VREF comparator offset error. 4

Stage 1 Stage 2 MDAC MDAC

Stage 3 Stage 4 MDAC MDAC

Stage 5 MDAC

Stage 6 MDAC

Stage 7 MDAC

Stage 8 Stage 9 MDAC 2BIT ADC

+1.0

0.6 0.4

0.3 +0.25

0.4 0.2

0.2

0 -0.2

-0.2

-0.25 -0.4

(a)

-1.0 B 1B 2

10

B 3B 4

B 5B 6

B 7B 8

00

01

10

B9B10

01

B11B12

10

B13B14

01

B15B16

10 01

B17B18

01

B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 D9 D8 D7

D6 D5 D4 D3 D2 D1 D0

(b) 1 0 1 0 1 0 1 0 0 1 Fig.4.14(a) Propagation of the residue value and ADSC output of the ideal 10bit pipelined ADC Fig4.14 (b) Digital correction algorithm

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Stage 1 Stage 2 MDAC MDAC

Stage 3 MDAC

Stage 4 MDAC

Stage 5 MDAC

Stage 6 MDAC

Stage 7 MDAC

Stage 8 Stage 9 MDAC 2BIT ADC

+1.0 0.6

0.3 +0.25

0.2 0.15

0 -0.2

-0.2

-0.25 -0.4 -0.45 -0.6

-0.6

-0.8 -1.0 B 1B 2

10

B 3B 4

B 5B 6

B 7B 8

01

00

00

B9B10

B11B12

01

B13B14

10

10

B15B16

00 01

B17B18

01

Fig.4.15 (a) Propagation of the residue value and ADSC output of the 10bit pipelined ADC with comparator offset error in stage 2 and stage 7. B1 B2 B3 B4 B5 B6 B7 B8

(+)

B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 D9 D8 D7

D6 D5 D4 D3 D2 D1 D0

1 0 1 0 1 0 1 00 1 Fig.4.15(b) Digital correction algorithm

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CHAPTER 5 SIMULATION RESULTS The static error performance of the ADC is given by two parameters INL and DNL. To measure the INL and DNL of the ADC, a slow varying ramp input is used. The ramp must be such that it traverses through all the codes. The reconstructed ramp signal is shown in the figure.

Fig5.1 Reconstructed ramp signal using ideal DAC The measured DNL is within +0.81 LSB and -0.69 LSB. The measured INL is within ±0.5 LSBs. The plots of INL and DNL are shown below.

Fig5.2DNL plot

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Fig5.3 INL plot The dynamic performance of the ADC is specified by various parameters such as SFDR, SNDR, SNR and ENOB. To measure the dynamic performance of the ADC, a single tone sine wave can be used and measure the performance. The following figure shows the reconstructed sine wave from the ADC.

Fig5.4 Reconstructed sine wave from ideal DAC From the reconstructed sine wave, dynamic performance of the ADC such as SFDR, SNDR, SNR, ENOB etc are measured.

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The frequency domain spectrum of the reconstructed sine wave is shown in the following figure.

Fig5.5 FFT spectrum of reconstructed sine wave The following figures show the variation of ENOB and SFDR with the input frequency. [18]

Fig5.6 ENOB vs. input frequency 61

Fig5.7 SFDR vs. input frequency

The following figure illustrates the SFDR variation as the input sampling frequency changes.[18]

Fig5.8 SFDR vs. sampling frequency

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SUMMARY OF THE SIMULATED PERFORMANCE Technology

UMC-180nm technology

digital

Resolution

10-bits

Architecture

Pipelined

Conversion rate

100Ms/S

Input range

2Vp-p

Supply voltage

1.8V

Temperature range

-550C to 850C

Reference Voltages INL

Vref(+)=1.4 Vref(-)=0.4 Vcmo=0.9 Vcmi=1.3 +0.5/(-0.38) LSB

DNL

+0.82/(-0.69) LSB

SNDR at 4M

53.11dB

ENOB at 4M

8.56

THD at 4M

(-)44.48dB

SFDR at 4M

56.51dB

Power dissipation

Analog: 37.75mW Digital: 150uW

Table 5.1 Summary of the Simulated Performance

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CMOS

CHAPTER 6 CONCLUSION

A 10 bit 100 MS/Sec PIPELINED analog to digital converter was successfully designed and its performance tested and evaluated using CADENCE. Flip around architectures both in Sample and Hold Amplifier and MDACs helped reduce area almost two fold. To improve the input signal switches’ linearity, Bootstrapping technique was implemented.

It was verified that stage scaling could be effectively used to reduce power consumption and area consumption. Also optimal design of the first few stages would need to be guaranteed for a good performance of the entire ADC. The latter stages’ specifications could be relaxed. The simulated results were found to lie in line with our expectations.

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REFERENCES 1) A. Abo et al, “A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-toDigital Converter” IEEE J. Solid-State Ckts., pp. 599, May 1999. 2) D. J. Allstot and W. C. Black, Jr., “Technological Design Considerations for Monolithic MOS Switched-Capacitor Filtering Systems,” Proc. IEEE, pp. 967-986, Aug. 1983 3) Andrew Masami Abo, Design for Reliability of Low-Voltage SC Circuits, Ph.D. thesis, 1999. 4) A. Abo Et Al, “A 1.5-V, 10-Bit, 14.3-Ms/S CMOS Pipeline Analog-ToDigital Converter,” IEEE J. SOLID-STATE CKTS., PP. 599, MAY 1999 5) Arnold R. Feldman, Member, Ieee, Bernhard E. Boser, Member, Ieee, And Paul R. Gray, Fellow, IEEE IEEE Journal Of Solid-State Circuits, Vol. 33, No. 10, October 1998 A 13-Bit, 1.4-Ms/S Sigma–Delta Modulator For Rf Baseband Channel Applications 6) Prof. Boris Murmann, STANFORD UNIVERSITY, Department of Electrical Engineering, EE315: VLSI Data Conversion Circuits- Spring 2007. 7) Byung-Moo Min, Senior Member, IEEE, Peter Kim, Member, IEEE, Frederick W. Bowman, III,David M. Boisvert, Member, IEEE, and Arlo J. Aude, Member, IEEE. IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 12, DECEMBER 2003. 8) T. B. Cho, "Low-Power Low-Voltage Analog-to-Digital Conversion Techniques using Pipelined Architectures", Ph.D. thesis, 1995. 9) Jirayuth Mahattanakul, Member, IEEE, and Jamorn Chutichatuporn. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 52, NO. 8, AUGUST 2005, Design Procedure for TwoStage CMOS OpampWith Flexible Noise-Power Balancing Scheme 10) Jipeng Li, Accuracy Enhancement Techniques in Low-Voltage HighSpeed Pipelined ADC Design, Ph.D. Thesis, Oregon State University, 2003.

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11) Kazutaka Honda, A Low Power, Low Voltage, 10 Bit, 100ms/Sec Pipelined ADC Using Capacitance Coupling Technique. IEEE JOURNAL OF SOLID STATE CIRCUITS. Pg:757-765. APR 2007 12) Kok Chin Chang CMOS Sample/Hold Circuits for High Speed A/D Conversion, 1991. 13) Krishnaswamy Nagaraj, Senior Member, IEEE, H. Scott Fetterman, Joseph Anidjar, Stephen H. Lewis, Member, IEEE, and Robert G. Renninger. A 250-mW, 8-b, 52-Msamples/s Parallel-Pipelined A/D Converter with Reduced Number of Amplifiers. IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 3, MARCH 1997 14) Ojas Choksi, Member, IEEE, And L. Richard Carley, Fellow, Ieee Analysis Of Switched-Capacitor Common-Mode Feedback Circuit. Ieee Transactions On Circuits And Systems—Ii: Analog And Digital Signal Processing, Vol. 50, No. 12, December 2003 15) I.Rajesh, Design, Simulation of A 10-bit, 40 MHz Pipelined A/D Converter, MS thesis, IIT Madras, April 2005. 16) Behzad Razavi, Design of Analog CMOS Integrated Circuits, Tata McGraw-ill Edition 2002. 17) Walt Kester, Which ADC Architecture Is Right for Your Application? Analog Dialogue, Analog devices Volume 39 – June 2005. 18) Wikner Jacob, Mikael Gustavsson, Nianxiong Nick, CMOS Data Converters for Communications, Kluwer Academic publishers 19) W. Yang et al., "A 3-V 340-mW 14-b 75-MSample/s CMOS ADC With 85-dB SFDR at Nyquist Input", IEEE J. Solid-State Circuits, pp. 1931-1936, Dec. 2001.

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