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IEEE ELECTRON DEVICE LETTERS, VOL. 27, NO. 4, APRIL 2006

Effect of Tensile Uniaxial Stress on the Electron Transport Properties of Deeply Scaled FD-SOI n-Type MOSFETs H. M. Nayfeh, D. V. Singh, J. M. Hergenrother, Member, IEEE, J. W. Sleight, Z. Ren, O. Dokumaci, L. Black, D. Chidambarrao, R. Venigalla, J. Pan, W. Natzle, B. L. Tessier, J. A. Ott, M. Khare, K. W. Guarini, M. Ieong, and W. Haensch

Abstract—In this letter, the effect of longitudinal uniaxial mechanical stress on electron mobility in high-performance fully depleted ultrathin silicon-on-insulator nFETs with a raised source/drain (RSD) architecture and channel lengths ranging from 1 µm (long channel) to 30 nm (deeply scaled) is reported. Longitudinal uniaxial stress in the channel was achieved using a stressed nitride contact liner technique. A dR/dL method was used to minimize errors in the mobility extraction due to uncertainties in external resistance and channel length. Significant mobility enhancement of 1.6–1.8 times was achieved despite the use of an RSD and strong channel doping of roughly 5 × 1018 cm−3 , required for short-channel effect control. Index Terms—Deeply scaled CMOS, fully depleted siliconon-insulator (FD-SOI), MOSFET, strained-Si, stress, ultrathin silicon-on-insulator SOI (UTSOI), uniaxial stress.

I. I NTRODUCTION

U

NIAXIAL tensile stress applied to deeply scaled nMOSFETs (sub-60-nm gate lengths) using the stressed contact liner technique has been shown to significantly enhance effective drive current in planar bulk and partially depleted devices [1], [2]. Stress-induced splitting of the sixfold degenerate conduction band results in a reduced intervalley scattering and a smaller effective transport mass giving rise to higher electron mobility in the channel [3]. CMOS technology based on fully depleted silicon-on-insulator (FD-SOI) devices provides reduced parasitic capacitance and offers the potential for improved short-channel control [4], [5]; however, its compatibility with this stress-liner technique has yet to be clarified. Simulations using a finite-element approach indicate that the channel stress induced by the contact liner is strongly influenced by both the channel thickness and the source/drain (S/D) topography. Although stress couples more effectively into a thinner channel, the raised S/D (RSD) region tends to degrade stress transfer. In this letter, we report the influence of stressed contact Manuscript received October 25, 2005. The review of this letter was arranged by Editor A. Chatterjee. H. M. Nayfeh, Z. Ren, O. Dokumaci, D. Chidambarrao, R. Venigalla, W. Natzle, B. L. Tessier, and M. Khare are with the IBM Systems and Technology Group, Hopewell Junction, NY 12533 USA (e-mail: [email protected]). D. V. Singh, J. M. Hergenrother, J. W. Sleight, J. A. Ott, K. W. Guarini, M. Ieong, and W. Haensch are with the IBM Semiconductor Research and Development Center, T. J. Watson Research Center, Yorktown Heights, NY 10598 USA. L. Black and J. Pan are with the Advanced Micro Devices, IBM Semiconductor Research and Development Center, Hopewell Junction, NY 12533 USA. Digital Object Identifier 10.1109/LED.2006.871542

liners on the electron transport properties of deeply scaled high-performance ultrathin SOI (UTSOI) nMOSFETs with an RSD architecture and channel lengths ranging from 1 µm to 30 nm. II. D EVICE F ABRICATION Deeply scaled nMOS devices with gate lengths down to 30 nm were fabricated on 300-mm
100-bonded SOI wafers. The initial SOI layer was thinned by thermal oxidation to target a final channel thickness tSi of 18 nm underneath the thin gate oxide, taking into account Si consumption during processing. Device isolation was achieved using a conventional STI approach with a reduced HF budget. The gate oxide consisted of a nitrided oxide with tinv ∼ 21.5 Å. A modified process flow described below was used to minimize parasitic series resistance Rs in these devices. In this flow, selective epitaxial silicon was grown on undoped S/D regions with a SiN disposable spacer encapsulating the gate. The nFET deep S/D was performed after RSD growth with the disposable spacer still in place. A subsequent annealing was performed to properly drive in these implants, eliminating the potential for weak links between the RSD regions and the thinner extension regions. The disposable spacer was then selectively removed, followed by tilted halo implants, formation of a thin offset spacer, and extension implants. The faceted nature of the epi minimizes any parasitic offset spacer formed on the RSD epi ledge. A final spacer slightly wider than the disposable spacer was then formed, followed by a spike rapid thermal annealing (RTA) and a conventional Ni salicide process. A Si3 N4 tensile stress liner film was then deposited over the nMOS devices [1]. For the unstrained Si controls, a blanket Ge implant was used to relax film stress over the entire wafer. A cross-sectional transmission electron microscopy (XTEM) of the final 30-nm UTSOI device structure including RSD, NiSi, and the Si3 N4 stress liner film is shown in Fig. 1. III. R ESULTS AND D ISCUSSION Effective channel mobility in MOSFETs is typically extracted from the ratio of the drain conductance gd and the inversion charge concentration Ninv , which is defined as

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µeff (Ninv ) = L2poly

gd (Ninv ) qNinv

NAYFEH et al.: EFFECT OF TENSILE UNIAXIAL STRESS ON DEEPLY SCALED FD-SOI n-TYPE MOSFETs

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Fig. 1. XTEM image of a completed 30-nm device showing an 18-nm-thick body, RSD, NiSi, and SiN stress liner.

where q is the charge of an electron, gd is obtained from phase–current (I–V ) measurements at low drain bias, and Qinv is determined by integrating the split capacitance–voltage (C–V ) curve [6]. However, in short-channel devices, the conventional approach for measuring mobility is prone to large errors arising from uncertainties in the channel length Lpoly and parasitic extrinsic resistance Rext . In the deep submicrometer gate length regime where Rext is comparable to the channel resistance Rch , errors in estimating Rext can have a significant impact on the measured value of gd and, hence, the extracted mobility. This effect is potentially exacerbated in devices on ultrathin silicon where parasitic resistance effects tend to be more pronounced. In this letter, we compare the electron mobility measured in UTSOI devices with and without stress liners and gate lengths ranging from 30 to 55 nm using a dRtotal /dL method, a technique that minimizes the effect of uncertainties in Lpoly and Rext on the measured mobility [7]. Using the dRtotal /dL approach, the effective mobility µeff (Ninv ) can be expressed as µeff (Ninv ) =


1 (Ninv ) qNinv dRtotal dLpoly



where Rtotal is the total device resistance measured at low Vds , Lpoly is the electrically determined gate length, and dRtotal /dLpoly is determined from a linear fit of Rtotal versus Lpoly . Extracted values of mobility represent an average value of mobility for the Lpoly range measured. Fig. 2 shows the measured Ron versus Lpoly curves at various gate overdrive voltages for UTSOI nFETs with a tensile stress liner. Linear regression coefficients > 0.9 indicate that the mobility is not a strong function of Lpoly in the range studied (30 nm < Lpoly < 55 nm). Inversion carrier concentration Ninv for different gate overdrive voltages was estimated by the parallel plate capacitor expression Cinv (Vgs − Vt ), where Cinv is the gate capacitance in inversion measured on a large area device. The Ninv extraction technique was tested for accuracy by comparing with the Ninv values obtained by integrating the measured split Cinv − Vgs curves, where the curves were adjusted to account for short-channel effects (i.e., drain-induced barrier lowering (DIBL), threshold voltage rolloff, and fringing capacitance) [8].

Fig. 2. Measured Ron versus Lpoly curves at various gate overdrive voltages (0.4, 0.45, . . ., 0.75, 0.8 V) for UTSOI nFETs with a tensile stress liner. Linear regression coefficients greater than 0.9 indicate that the mobility is not a strong function of Lpoly in the range studied (30 nm < Lpoly < 55 nm).

Fig. 3. Mobility data (open symbols) demonstrating an enhancement of 1.6–1.8 times for Ninv in the range of 4−8 × 1012 cm−2 over unstrained Si control devices. Also shown is the mobility extracted using the conventional approach on long-channel devices, Lpoly = 1 µm [6], for stress and no-stress liner cases, demonstrating that the stress-liner technique does not result in increased mobility for long-channel devices consistent with numerical stress calculations. The universal mobility curve [11] for bulk long-channel devices with Na = 5 × 1017 cm−3 and 5 × 1018 cm−3 are shown for reference.

It was found that the Ninv values obtained using the simple parallel plate capacitor expression closely match those obtained by integration of the full split C–V curves for sufficiently high gate overdrive voltage (Vgs − Vt > 0.4 V). Mobility data presented in Fig. 3 demonstrates an enhancement of 1.6–1.8 times for Ninv in the range 4−8 × 1012 cm−2 over unstrained Si control devices. The observed stress-induced enhancement decreases with increasing Ninv , which is consistent with theoretical predictions. At higher vertical effective fields (and, hence, Ninv ), quantization effects due to the large confinement potential reduce the impact of tensile strain on mobility [9]. Fig. 3 also compares the mobility extracted using the conventional approach on long-channel devices, Lpoly = 1 µm [6], for stress and no-stress liner cases, demonstrating that

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the stress-liner technique does not result in increased mobility for long-channel devices consistent with numerical stress calculations. The doping concentration for the long-channel devices was estimated to be ∼ 5 × 1017 cm−3 using an analytical equation for the long-channel threshold voltage for FD-SOI devices, and the channel doping concentration for the shortchannel devices was determined to have a spatial average of ∼ 5 × 1018 cm−3 based on TSUPREM numerical simulations [10]. The universal mobility curve [11] for bulk long-channel devices with Na = 5 × 1017 cm−3 and 5 × 1018 cm−3 are shown for reference. The short-channel devices (no-stress liner case) exhibit lower mobility at a given Ninv than the long-channel devices consistent with the higher doping in these devices. However, the mobility degradation for a given Ninv is less than what was predicted (assuming that mobility characteristics follow the universal mobility curve [11]) for the estimated body doping of approximately 5 × 1018 cm−3 . This can be attributed to the reduced effective vertical electric field for a given body doping in short-channel devices due to two-dimensional (2-D) charge sharing with the S/D. This effect was further investigated with 2-D numerical simulations using FIELDAY [12] to estimate the vertical effective field at the center of the channel. Two cases, namely, (1) long-channel (Lpoly = 1 µm gate) and (2) shortchannel (Lpoly = 45-nm gate) UTSOI devices with a channel thickness of 18 nm, were studied. To simplify the analysis, a uniform channel doping of 5 × 1018 cm−3 was assumed in both devices. The vertical effective field was defined as the weighted average of the electric field against the inversion charge concentration [13], which is expressed as  Ninv E dx . Eeff =  Ninv dx The effect of quantum–mechanical confinement on vertical effective field has been accounted for in the simulations. For a gate overdrive of 0.8 V, Eeff drops significantly from 1.8 MV/cm in the long-channel devices to 1.07 MV/cm in the short-channel devices (Lpoly = 30−50 nm). This corresponds to the change in the mobility from 135 to 250 cm2 /V · s if one assumes that mobility versus Eeff follows the universal curve. Reduced depletion charge due to the thin silicon body will also tend to decrease Eeff for a given body doping and inversion charge density.

IEEE ELECTRON DEVICE LETTERS, VOL. 27, NO. 4, APRIL 2006

IV. C ONCLUSION We have measured the impact of tensile stress liners on the channel mobility in high-performance UTSOI nMOSFETs with an RSD architecture and sub-50-nm gate lengths. A dR/dL method was used to minimize errors in the mobility extraction due to uncertainties in external resistance and channel length. Significant mobility enhancement of 1.6–1.8 times was achieved despite the use of an RSD and a strong channel doping of roughly 5 × 1018 cm−3 , which is required for short-channel effect control. The mobility enhancement obtained using the stressed nitride contact liner technique persists over a wide Ni range of 4−8 × 1012 cm−2 (or vertical Eeff ). The results reported in this letter clearly demonstrate the compatibility of stress liners with high-performance FD-SOI technology. R EFERENCES [1] H. S. Yang et al., “Dual stress liner for high performance sub-45 nm gate length SOI CMOS manufacturing,” in IEDM Tech. Dig., 2004, pp. 1075–1077. [2] S. E. Thompson et al., “A logic nanotechnology featuring strainedsilicon,” IEEE Electron Device Lett., vol. 25, no. 4, pp. 191–193, Apr. 2004. [3] T. Vogelsang and K. R. Hofmann, “Electron transport in strained Si on Si1−x Gex substrates,” Appl. Phys. Lett., vol. 63, no. 2, pp. 186–188, Jul. 1993. [4] B. Doris et al., “Extreme scaling with ultra-thin Si channel MOSFETs,” in IEDM Tech. Dig., 2002, pp. 267–270. [5] Z. Krivokapic, V. Moroz, W. Maszara, and M.-R. Lin, “Locally strained ultra-thin channel 25 nm narrow FDSOI devices with metal gate and isolation,” in IEDM Tech. Dig., 2003, pp. 18.51–18.53. [6] C. G. Sodini, T. W. Ekstedt, and J. L. Moll, “Charge accumulation and mobility in thin dielectric MOS transistors,” Solid State Electron., vol. 25, no. 9, pp. 833–841, Sep. 1982. [7] K. Rim, S. Narasimha, M. Longstreet, A. Mocuta, and J. Cai, “Low field mobility characteristics of sub-100 nm unstrained and strained Si MOSFETs,” in IEDM Tech. Dig., 2002, pp. 43–46. [8] A. Lochtefeld and D. A. Antoniadis, “Investigating the relationship between electron mobility and velocity in deeply scaled NMOS via mechanical stress,” IEEE Electron Device Lett., vol. 22, no. 12, pp. 591–593, Dec. 2001. [9] M. V. Fischetti, F. Gamiz, and W. Haensch, “On the enhanced electron mobility in strained-silicon inversion layers,” J. Appl. Phys., vol. 92, no. 12, pp. 7320–7324, Dec. 2002. [10] T-SUPREM4 Version 2002.3, Avant!, Palo Alto, CA, 1999. [11] S. Takagi, A. Toriumi, M. Iwase, and H. Tango, “On the universality of the inversion layer mobility, in Si MOSFETs part-I—Effects of substrate impurity concentration,” IEEE Trans. Electron Devices, vol. 41, no. 12, pp. 2357–2362, Dec. 1994. [12] FIELDAY Version No. 4.0, Oct. 31, 2002. [13] A. Sabnis and J. Clemens, “Characterization of the electron mobility in the inverted 100 Si surface,” in IEDM Tech. Dig., 1978, p. 18.