Grooming IC Designer through Apprenticeship Programme N.Intan1, M.Amir1, S.Sakrani2, M.Afham2 Research and Postgraduate Studies, Universiti Kuala Lumpur1 ICmic-UniKL Academy2 engineers in Penang, Malaysia alone will increase to 2000+ within 3-5 years, which will worsen the present shortage of IC designers. Intel, Altera, AMD, Agilent and other MNCs and local design houses continue to advertise job openings in local newspapers and engage human resource consultants, but these companies face a challenge in finding qualified candidates because not many EE graduates have a strong background in VLSI and IC Design. Some design centres have resorted to hiring foreigners because of this severe shortage.

Abstract - The rapid growth in the microelectronics industry and the challenges increasing such as globalization, technological changes and specialization has brought about a demand for skill manpower. Therefore, the apprenticeship program in IC Design which provided a comprehensive training is really significant to the industry need. The apprenticeship program was conducted at ICmic-UniKL Academy which focuses on Microelectronics competency development for Malaysian in producing commercial Integrated Circuit (IC) products. Through this apprenticeship, apprentice was exposed to the hands-on job with entrepreneurial skills who can directly participate in microelectronics design and related industries thus closing the gap with industry requirement. A supervisory circuit with watchdog timer feature was highlighted to show one of the project carried out by the apprentice. At the end of this apprenticeship, the apprentice will able to master the skills and has necessary knowledge to become a highly competent and entrepreneurial design engineer. timer,

IC designers require knowledge and skills. Many of them started their carrier by chance but few exploring by appointment. Graduates in EE or in related field, would spend few more years to specialize the process and master the state of the art. Therefore an intensive programme such as the academy is certainly required to generate IC design expert in more strategic way. Other factors particularly software tools are also key-factor that helps the learning process. The recent software tools are able to generate result which is almost 99% as good as actual product.

IC manufacturing is steadily growing despite economic depression in the last few months. Technologies relying on the usage of IC especially new products need new features for marketing enhancement. Small gadgets such as cell phone, hand held PC, pen-drive, notebooks are rapidly upgraded perhaps shorter than 18 months [3] as predicted by Moore’s Law: Technology changes for every 18 months.

The apprentice programmes specialised in IC design forecast to increase the numbers of IC designer. The apprentices are exposed with real work includes training, design layout, doing analysis, and reliability testing and also participate in marketing the products. A pilot project in setting up the apprenticeship program has been established in collaboration with several entities namely UniKL, ICMIC and Silvaco. The project is moving progressively with the aims to cater the demand of IC designers particularly in Malaysia and neighbouring countries like Singapore, Thailand, China and etc.

Keywords - Apprentice, watchdog supervisory circuit, IC design.

I. INTRODUCTION

The remainder of this paper, Section II, describes the structure of the training apprenticeship program. Section III addresses the research project carried out by the apprenticeship as an example and in Section IV discusses the opportunities and benefit gained through out the program. Finally, Section V

The people behind the technology so called IC designers are the group of people who are making the technology visible. However the pace of growing probably could be improved if there were enough number of IC designers. A government link Institute, Collaborative Research & Resource Centre (CRRC) has conducted a survey shows the demand for D&D

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highlights the conclusions of the apprenticeship project.

and provides hands-on experience of a wide range of product development skills.

II. APPRENTICESHIP PROGRAM

Once the intensive course is completed the apprentice will join an anchor project according to their interest namely digital, mixed-signal or analogue circuit design. At this stage apprentice have to show contribution in the form of products, design, IP and marketing strategy. Towards the end of this stage the novelty of the contribution is valued to award them a master degree for their academic qualification.

The program is managed by a group of expert socalled ICmiC-UniKL academy. The academy provides 18-month apprenticeship programme leading to be IC design expert and getting master degree at the end of the hard work. The apprentice undergoes a real on-the-job skill development for commercial level IC at which research elements are being integrated as part of the work. The novelty and originality of the works were then weighted to confer a master degree which is considerable as good as student undergoes conventional master study. However the apprentice graduates from this academy has more added value in term of specialised knowhow and practical skill.

III. COURSE CONTENTS The contents of the special course comprise five topics namely Semiconductor design process, IC design, IC layout, IC packaging and IC testing. The sequence of the delivery is shown in Fig. 1 as such help the apprentice to follow the learning easily. The details for each topic are explained as follow:

Previous efforts were [1] [2] relied on free software such as Magic, Electric and the course were carried out as module/subject for undergraduate program. The impact was good whereby graduate understood some fundamental issues especially HDL programming, layout and the process of fabrication. However the target is more inclined to train them to become Engineers rather than IC Designers.

Semiconductor Design Process

In this apprentice program the main target group is graduate who have basic knowledge particularly in electronics and semiconductor technology. The training is manned to coach the apprentice in enhancing their knowledge in IC design prior to perform actual works using industrial standard of software tools. They will experience the design process thoroughly involving time to market, market demands, Intellectual Property Issues, prototype development and skill to be entrepreneur for setting up IC design house.

IC Design

IC Testing

IC Layout IC Packaging

Fig 1: Step-by-step IC process

A. Semiconductor Design Process This topic provides the apprentice with the CMOS fabrication process. Here the apprentice designs an NMOS transistor using 130 nm CMOS technology. SILVACO ATHENA (Fabrication) is used to simulate its I-V characteristic of the transistor.

Strategically the program is structured for 2 stages. In the first two months apprentice are undergoing intensive course to understand the function as IC Designer in real market, the important of team work in developing prototype, strategy to achieve factor so called time to market and sitting assessment for competency development project. Apprentice is required to complete a series of short course and at the end of the course they have to sit assessment for competency test. The course exposes the apprentice with different stages in product development cycle

This exercise was good to help them visualize the NMOS fabrication process. While doing the simulation there are few parameters that need to be observed such as gate oxide thickness, the threshold voltage implant dose and doping energy in order to get the minimum leakage current.

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B.

IC Design

The apprentice is given a project at this stage to work with. One of the projects was watchdog timer circuit. The simulation works were done by using sophisticated tools namely Gateway Simucad and SmartSpice. Figure 6 shows the watchdog schematic and it uses to supervise microprocessor activity and resets a non-responsive system after a timeout period. During normal operation, the microprocessor should repeatedly toggle the WDI before the selected watchdog timeout period elapsed. This demonstrates that the system is processing the code properly. If the system does not provide a valid WDI transition before the timeout period expires, the watchdog timer send a reset signal to the system. These two rapports are shown in Figure 7 and 8.

Fig 2: NMOS 130 nm structure using Silvaco ATHENA

Specification

Circuit Design

Circuit Validation

Fig. 3: Ids vs. Vgs using Silvaco ATLAS Meet Spec

Layout

Layout Verification

Fig 4: Ids vs. Vds using Silvaco ATLAS Layout Extraction & Re-validation

Emphasis is always given to inform them that the fabrication process is not an easy process which requires thorough justifications and considerations. Lack of knowledge for this particular juncture may affect the whole device performance. Fig. 2, Fig. 3 and Fig. 4 shows the results produced by the apprentice.

GDSII Tapeout

Fig 5: Flow Chart for IC Design Software Tools

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Fig 6: Watchdog schematic using SimuCad Gateway

RSTB

WDI

Fig. 7: Watchdog timeout and reset signal for normal operation

VDD

RSTB

WDI

WDRST

  Fig. 8: Watchdog timeout and reset signal for active mode

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performance, power consumption and etc. The academy provides three laboratories for the apprentice to use which are IC Testing Lab (Fig. 10), Mixed-Signal Lab and RF Lab. These facilities facilitate the apprentice to conduct actual testing procedure as carried out by the industries.

C. IC Layout The apprentice uses Expert Layout Editor to design the layout. The layout is simulated to verify the functions until fulfils the operation as expected. There were two verification processes namely Layout Versus Schematic (LVS) and Design Rules Check (DRC). Finally the design process is concluded by sending the final layout design to the Fabrication Vendor at which SILTERRA, Malaysia is agreed to be the co-partner for the academy.

IV. DISCUSSION Apparently the main concern in setting up the academy is to groom highly skilled workers in IC design. The academy will provide latest technology, know-how, business opportunities and courses for the apprentice to undergo the complete process of IC design and its global business. One of the added values that enhance the quality of the graduate is the opportunities to work with IC Engineer who have been working in the area for many years. Another advantage is the package of software tools used by the apprentice, Silvaco, which is considered as one of the advanced commercial ID design tools available in the market. For the product development project, it is conducted in a team. The apprentice gains valuable experience where they are attached under mentormente scheme with professional engineer as their supervisors. They have experienced for more than 10 years which is a very valuable asset for the academy. The apprentices are working together with other apprentices as a team to complete the main mission so called anchor project. The complete task and division of task for the anchor project is illustrated in Figure 11 (as one of the examples). The challenge for the apprentice is the time schedule relatively short and they are required to contribute some research elements for the master studies. The schedule is very tight therefore apprentices are often working until late at night. However the hard work is paid off once their design is successfully fabricated and tested.

Fig. 9: Full chip layout using Expert Layout Editor

Fig. 10: Testing Equipment for Fabricated Chip

V. CONCLUSIONS With the rapid growth and evolution of the microelectronic technology, this is the great platform to train those who desire to enhance their further knowledge and career in IC design. Furthermore, the academy is also equipped with high-end facilities including the extensive IC Design software as well as the course contents reflect the need of IC design industry.

D. IC Packaging For this stage the apprentice explores several types of packaging. However there are two commons being used which are Quad Flat No Lead (QFN) and Small Outline Transistor (SOT). The decision to finalise the type of packaging is normally made by the anchor project leader according to his requirement and applications.

ACKNOWLEDGEMENT The authors would like to thank all the colleagues and staff of ICmic-UniKL academy and Universiti Kuala Lumpur for your commitment, support, knowhow, and facilities.

E. IC Testing Chip testing is carried out by the apprentice to analyse the imperfect of fabricated chip against its functionality. The imperfect issues may affect the specification of parameters particularly speed, 5

 

Fig. 11: Full Schematic for Anchor Project REFERENCES [7] J. Breckling, Ed., The Analysis of Directional Time Series: Applications to Wind Speed and Direction, ser. Lecture Notes in Statistics. Berlin, Germany: Springer, 1989, vol. 61. [8] S. Zhang, C. Zhu, J. K. O. Sin, and P. K. T. Mok, “A novel ultrathin elevated channel lowtemperature poly-Si TFT” IEEE Electron Device Lett., vol. 20, pp. 569–571, Nov. 1999. [9] M. Wegmuller, J. P. von der Weid, P. Oberson, and N. Gisin, “High resolution fiber distributed measurements with coherent OFDR” in Proc. ECOC’00, 2000, paper 11.3.4, p. 109. [10] R. E. Sorace, V. S. Reinhardt, and S. A. Vaughn, “High-speed digital-to-RF converter” U.S. Patent 5 668 842, Sept. 16, 1997. [11] A. Karnik, “Performance of TCP congestion control with rate feedback: TCP/ABR and rate adaptive TCP/IP” M. Eng. thesis, Indian Institute of Science, Bangalore, India, Jan. 1999. [12] J. Padhye, V. Firoiu, and D. Towsley, “A stochastic model of TCP Reno congestion avoidance and control” Univ. of Massachusetts, Amherst, MA, CMPSCI Tech. Rep. 99-02, 1999.

[1] M.Amir, D. Kinniment, G.Russel, “Designing IC Layout through In-expensive Software Tool”, 1st Proceeding of International Conference on Engineering Technology ICET07, December 2007. [2] Y.Ping Xu,”Two-Semester Project Based Mixed-Signal IC Design Course Using Commercial EDA Tools –From Design to Chip Evaluation” Proceeding of the 2003 IEEE International Conference on Microelectronics System Education (MSE’03), 2003. [3] R. Schaller, “Moore’s Law: Past, Present, and Future” IEEE Spectrum, June 1997, pp. 52-59. [4] R. E. Sorace, V. S. Reinhardt, and S. A. Vaughn, “High-speed digital-to-RF converter” U.S. Patent 5 668 842, Sept. 16, 1997. [5] Leon Huang and John J. Selman, “Watchdog Timer” U.S. Patent 4 627 060, Dec. 2, 1986. [6] Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specification, IEEE Std. 802.11, 1997.

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