ISSCC 2005 / SESSION 23 / WIRELESS RECEIVERS FOR CONSUMER ELECTRONICS / 23.7

23.7

A Single-Chip Receiver for Multi-User Low-Noise Block Down-Converters

Tino Copani1, Santo A. Smerzi2, Giovanni Girlando2, Giuseppe Ferla2, Giuseppe Palmisano1 1

University of Catania, Catania, Italy, STMicroelectronics, Catania, Italy

2

In digital video broadcasting via-satellite (DVB-S) systems the low-noise block down-converter (LNB) translates the RF satellite signal from the Ku-band (10.7 to 12.75GHz) to an IF which ranges in the L-band (0.95 to 2.15GHz). Recently, a monolithic LNB for single users in a silicon bipolar technology has been presented [1]. However, the greatest demand is presently for multiuser LNBs, which deliver satellite channels to more than one user. Up until now, to meet DVB-S challenging specifications, these complex systems have been built using a discrete approach by adopting GaAs HEMT or FET devices. In addition, dielectric resonant oscillators (DROs), that require manual tuning, are used to implement the LO. In this paper, an integrated receiver for multi-user LNBs is presented. The monolithic approach reduces both manufacturing costs and system complexity and avoids the tuning of DRO oscillation frequency. The block diagram of the proposed twin-LNB architecture, which is an LNB for two different users, is shown in Fig. 23.7.1. To obtain an overall noise figure (NF) as low as 0.6dB, external HEMTV and HEMTH devices amplify the vertical and the horizontal polarized channels, respectively. The grey box (IC) represents the integrated circuit. Two front-ends are fabricated on the same die to carry the vertical and horizontal polarized signals. Each front-end implements a heterodyne down-converter. A 10.2GHz PLL, locked to a 10MHz reference frequency, provides the LO for both mixers. The IF bands, which range from 0.5 to 2.55GHz, are fed to a 2×2 switch-matrix. Depending on user request (Select1,2), either vertical or horizontal RF bands are sent to the output buffers, which drive the 75Ω antenna cables. The monolithic approach required a considerable design effort to meet the challenging standard specifications [2]. Indeed, to relax HEMT stage requirements, an NF lower than 10dB and a conversion gain higher than 30dB has to be achieved by the integrated front-end. In addition, to successfully substitute DROs, the monolithic PLL must exhibit a phase noise as low as –95dBc/Hz at 100kHz offset from the 10.2GHz carrier. A bandwidth wider than two octaves has to be covered by both the switch-matrix and the output buffers with a gain variation lower than 5dB and an output 1dB compression point of +5dBm. Finally, a cross-polar rejection of 22dB must be guaranteed between the vertical and horizontal channels. To reduce the number of PCB discrete components, the receiver uses single-ended input and output terminals. The simplified schematic of a single front-end including the VCO is shown in Fig. 23.7.2. The front-end consists of two inductively degenerated cascode LNAs and a Gilbert cell. The input stage of the first LNA is designed for both a minimum NF and a 50Ω input impedance. A resonant load implemented by an integrated inductor is used between the two LNAs. An integrated transformer T, placed at the output of the second LNA, provides the load and the unbalanced to balanced signal conversion. This configuration eliminates the use of an active V/I converter, thus avoiding its impact on linearity performance.

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A three-stacked-turn transformer-based VCO is implemented thereby eliminating the need for both bias resistors and decoupling capacitors. This solution greatly improves the phase noise and tuning range performance. The capacitive degeneration CE allows the cross-coupled pair Q1-Q2 to extend the negative resistance behaviour, as required to sustain oscillation beyond 10GHz. The 2×2 switch-matrix and output buffers are shown in Fig. 23.7.3. These IF stages are DC-coupled to guarantee successful operation down to 500MHz without using large capacitors. The matrix implements two multiplexer circuits. Each multiplexer consists of two triple-tail emitter-coupled amplifiers, each fed by one of the mixers. Depending on the control signal (Select), Q5 and Q6 BJTs sink the bias current and thereby switching off one of the two degenerated pairs (Q1-Q2, Q3-Q4). This solution allows both isolation and linearity requirements to be met. The single-ended output needs a balanced to unbalanced converter (balun) to reject any in-band common-mode disturbance. Usually, integrated transformers are used to implement monolithic baluns. Although this approach is well suited for high-frequency applications, it is die-area consuming for an IF as low as 500MHz. Moreover, it requires high power consumption to guarantee high-linearity performance in broadband operation. The proposed buffer consists of a pair of emitter followers, Q7 and Q8, with active current sources, Q9 and Q10. It performs the differential to single-ended signal conversion through capacitor CD. This circuit achieves broadband output matching and meets the linearity performance required while avoiding high power consumption. The die micrograph is shown in Fig. 23.7.4. The receiver is integrated in a 0.8µm self-aligned-emitter silicon bipolar technology with a BJT fT of 50GHz. The IC is assembled using a die-on-board technique. The die area is 3.3×2mm2. Substrate parasitic effects are carefully taken into account to avoid desensitization, instability, and cross-polar interference [3]. The two front-ends are placed back-to-back to minimize signal crosstalk. Oxide trench guard rings and buried-layer contacts are used between the front-ends as well as between each critical block of the receiver. In particular, these isolation techniques are used for integrated inductors and transformers because they are devices that occupy large die area and operate in resonant condition. Finally, to reduce the LO-to-RF crosstalk, the transformer of the VCO is placed at a sufficient distance from the input LNAs. The measured conversion gain and the single-sideband (SSB) NF of the receiver are shown in Fig. 23.7.5. The integrated receiver exhibits a conversion gain of 32dB and a SSB NF of 7.8dB at 12GHz. The maximum conversion gain variation over the entire IF band is 2.5dB. The output 1dB compression point is +5dBm. The cross-polar rejection is 29dB, which is 7dB above the specifications, as shown in Fig. 23.7.6. The VCO phase noise is as low as –96dBc/Hz at 100kHz offset from the 10.2GHz carrier, as shown in Fig. 23.7.7. The VCO achieves a tuning range of 2.2GHz, which is wide enough to reliably cover the process variations. The LO-to-RF feed-through is –55dB. Finally, the IC draws 270mA from a 3.3V supply. Acknowledgments: The authors thank A. Castorina for testing the chip, and S. Zammataro, G. Zanti, A. Pinto, and C. Lombardo for carrying out the chip assembly. References: [1] G. Girlando, T. Copani, S. A. Smerzi, A. Castorina, and G. Palmisano, “A 12GHz Silicon Bipolar Receiver for Digital Satellite Applications,” ISSCC Dig. Tech. Papers, pp. 276-277, Feb., 2004. [2] ASTRA, “ASTRA Reception Equipment Recommendations for DTH and SMATV Systems,” Technical Recommendations, June, 2002. [3] R. G. Meyer, A. K Wong, “Blocking and Desensitization in RF Amplifiers,” IEEE J. Solid-State Circuits, vol. 30, no. 8, pp. 944-946, Aug., 1995.

• 2005 IEEE International Solid-State Circuits Conference

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ISSCC 2005 / February 9, 2005 / Salon 9 / 11:45 AM

Figure 23.7.1: Block diagram of the twin-LNB architecture.

Figure 23.7.2: Schematic of a single front-end including the VCO.

Figure 23.7.3: 2x2 switch-matrix and output buffers.

Figure 23.7.4: Die micrograph.

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Figure 23.7.5: Measured conversion gain and SSB noise figure.

Figure 23.7.6: Measured cross-polar rejection.

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ISSCC 2005 PAPER CONTINUATIONS

Figure 23.7.7: Measured VCO phase noise.

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• 2005 IEEE International Solid-State Circuits Conference

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