PG – 519

*PG519*

IV Semester M.Sc. Degree Examination, July 2013 Electronic Science EL 401 : VLSI TECHNOLOGY Time : 3 Hours

Max. Marks : 80

Instructions : Part – A : Answer all questions. Part – B : Answer any four full questions. PART – A 1. What is λ based design ? What are its merits and demerits ?

(4×5=20)

2. Draw the circuit diagram of an nMOS XOR gate. Assume negated inputs are available. 3. Explain the working of a pseudo nMOS inverter. What are its advantages and disadvantages ? 2

4. Given Rs = 0.03 Ω /square and area capacitance C = 4 × 10–4/ μm for 5μm devices, calculate the inverter pair delay. 5. Write a note on limits of scaling due to subthreshold currents. PART – B 6. a) What is gate restoring logic ? Explain. b) With band diagram explain what is threshold voltage in a MOSFET. c) Calculate the threshold voltage of a n – MOSFET, on a p substrate doped with Na = 1016 cm–3. The thickness of the oxide layer is 100 A°. [Given : εr of SiO2 is 4 and εr of Si is 12]. 7. a) Explain with a neat diagram the working of an enhancement mode MOSFET. b) Give the stick encoding of the basic layers of a MOS circuit. c) Briefly explain the rules for drawing the stick layout of a CMOS circuit.

3 4

8 7 4 4

8. a) Define the terms sheet resistance, area capacitance and delay unit with respect to VLSI technology. 5 b) Explain how nMOS inverters are cascaded to drive large capacitive loads. Calculate the delay with N inverters. 10 P.T.O.

*PG519*

PG – 519

9. a) Explain the 3 different scaling models, with a neat diagram. b) From 1st principles determine the effect of scaling in the 3 models on the following :

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i) Power dissipation/ gate ii) Gate capacitance and iii) Power speed product. c) Discuss the effect of scaling on the interconnect.

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10. a) Clearly explain why testing is important in VLSI circuits. Write a note on design for test. b) Explain the D algorithm for testing combinational circuits. c) In the circuit given in Fig. 1 determine the test vectors that can determine the stuck – at – 1 fault at d, stuck – at – 0 fault at a. 11. Write short notes on any three : a) Domino logic circuits b) Super – buffers c) Scan based testing circuits d) Latch up in MOS circuits e) Comparison of BJT and MOS devices.

Fig. 1 _______________________

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(3×5=15)