Large Marginal 2D Self-Aligned Via Patterning for Sub-5nm Technology Suhyeong Choia , Jae Uk Leeb , Victor M. Blanco Carballob , Peter Debackerb , Praveen Raghavanb , Ryoung-Han Kimb , and Youngsoo Shina a School
of Electrical Engineering, KAIST, Daejeon 34101, Korea b imec, Kapeldreef 75, B-3001 Leuven, Belgium ABSTRACT
Conventional via patterning which relies on immersion ArF (iArF) lithography and self-aligned via (SAV) becomes challenging in sub-7nm technology. EUV lithography (EUVL) is expected to achieve smaller feature patterning thanks to its short wave length, but edge placement error (EPE) margin remains as another bottleneck of pitch scaling; SAV can be aligned with metal on the top but not with the bottom of the via. Literary study shows previous work on 2D self-aligned via (2D SAV) which can be aligned with the both metals, but it cannot extend technology scaling beyond sub-5nm whose minimum metal pitch is expected as sub-20nm due to essential limitation of EPE margin. We propose large marginal 2D SAV which has three times large EPE margin than normal 2D SAV for extremely shrunk technology node (e.g. sub-5nm). Large marginal 2D SAV may allow further feature size scaling, but it requires four EUV masks. Therefore, we present two count reduction methods and corresponding mask decompositions and pattern re-targetings. Proposed re-targeted patterns are assessed by source mask optimization (SMO) in terms of maximum EPE and process variation band (PVB) width. Keyword: EUV lithography (EUVL), 2D self-aligned via (2D SAV), etch selectivity, edge placement error (EPE), source mask optimization (SMO)
1. INTRODUCTION As technology aggressively scales down, via patterning becomes more challenging. Currently double or triple patterning of immersion ArF (iArF) lithography has been widely used with self-aligned via (SAV) process.1 However, EUV lithography (EUVL), which has better resolution due to shorter wave length of 13.5nm, is expected to be introduced in sub-7nm technology because EUV single exposure, instead of multiple DUV masks, can save manufacturing cost. SAV process also faces its limitations as shown in Figure 1. Via pattern is extended (or re-targeted) in Mx direction, so that the via is self-aligned on Mx+1 layer under process variations (e.g. dose error, mask error, defocus, and overlay); especially, when it comes to EUVL, process variations such as mask 3D effect and resist stochastic are additionally taken into account.2 However, it can still be misaligned with Mx layer as illustrated in Figure 1(b), which causes a risk for time dependent dielectric breakdown (TDDB).3 Thus, it is challenging to persist technology scaling with conventional SAV.
Via contour with process variation
Via Mx layer
TDDB caution Mx+1 Dielectric
Re-targeted via
Mx
Mx+1 layer (a)
(b)
Figure 1. Misalignment of conventional SAV on Mx layer; (a) top and (b) cross-sectional views.
Design-Process-Technology Co-optimization for Manufacturability XI, edited by Luigi Capodieci, Jason P. Cain, Proc. of SPIE Vol. 10148, 101480J · © 2017 SPIE CCC code: 0277-786X/17/$18 · doi: 10.1117/12.2257924 Proc. of SPIE Vol. 10148 101480J-1 Downloaded From: http://proceedings.spiedigitallibrary.org/ on 04/02/2017 Terms of Use: http://spiedigitallibrary.org/ss/termsofuse.aspx
Material A
Material C
Re-targeted via
Via
Photo resist Material C
Etch
Etch
Material A Mx layer
Dielectric
Mx+1
Metal
Mx
Mx+1 layer
(b)
(a)
(c)
Figure 2. (a) Top-down view of 2D SAV with original and re-targeted via patterns, (b) horizontal, and (c) vertical cross-sectional views after selective etching of material A.
Via Conflict-I Conflict-II Mx layer Conflict-III
Mx+1 layer
Figure 3. Examples of mask color conflict.
Previous work has conceptually proposed 2D self-aligned via (2D SAV) which can be aligned with both upper and lower metal layers (or in vertical and horizontal directions).4 As illustrated in Figure 2, material A forms grating within each Mx and Mx+1 layer while material C is filled in the trench between the material A (Figure 2(a)). Via pattern is inflated (or re-targeted in square shape instead of rectangular one in conventional SAV), so that the original via location is always exposed under lithography process variations. Note that only material A and underneath dielectric are selectively etched while remaining material C and its underneath layers; thus, via is self-aligned with both Mx + 1 and Mx layers as shown in Figure 2(b) and (c), respectively, thanks to small etch rate of material C within both layers.
1.1 Analysis of 2D SAV We analyzed 2D SAV assuming EUVL to forecast the limitation of pitch scaling by counting the number of required masks and estimating overlay (OVL) and CD uniformity (CDU) requirements. Mask color conflict occurs if via center to center (C2C) distance is shorter than the via minimum C2C distance; the minimum distance was calculated as 36.8nm assuming λ = 13.5nm, k1 = 0.45, and N A = 0.33.5, 6 As illustrated in Figure 3, three types of conflicts can happen. If conflict-I is observed, two masks are required, and if either of conflict-II or conflict-III occurs, another mask is added. We summarized the mask count depending on vertical
Proc. of SPIE Vol. 10148 101480J-2 Downloaded From: http://proceedings.spiedigitallibrary.org/ on 04/02/2017 Terms of Use: http://spiedigitallibrary.org/ss/termsofuse.aspx
Table 1. EUV mask count considering via C2C distance
Mask counts
Vertical pitch (nm)
28 26 24 22 20 18 16
28 1 1 1 1 1 3 3
Horizontal pitch (nm) 26 24 22 20 18 1 1 1 1 3 1 1 2 2 3 1 2 2 2 3 2 2 2 2 3 2 2 2 2 3 3 3 3 3 4 3 3 3 3 4
16 3 3 3 3 3 4 4
Expected safe zone 2.2 OVL (3 ) [nm]
OVL (3 ) [nm]
2.2 1.8 1.4 1.0 0.6
1.8 1.4 1.0 0.6
0.6
1.0
1.4
1.8
2.2
0.6
1.0
1.4
1.8
CDU (3 ) [nm]
CDU (3 ) [nm]
(a)
(b)
2.2
Figure 4. Required OVL and CDU for (a) 18nm and (b) 16nm pitches. Table 2. Monte-Carlo simulation condition
Pitch (nm) 36 18 16
Re-target bias (nm) 9 4.5 4
OVL (3σ) (nm) 3.6 . .
CDU (3σ) (nm) 1.8 . .
LER (3σ) (nm) 2.7 2.0 2.0
and horizontal pitches in Table 1. From 24nm by 24nm metal grid, EUV double patterning starts to be necessary, and if either of vertical and horizontal pitch is smaller than 20nm, three or more EUV masks are needed. Required OVL and CDU for sub-20nm pitch were estimated in statistical manner. The space between the via and the adjacent metal intersection, which is half pitch, can be occupied by re-target bias and margin for OVL, CDU, and line edge roughness (LER). We attempted Monte-Carlo simulation to calculate probability of #f ailures failure (PoF) (= #total instances ) in which failure is counted if the simulated contour touches the adjacent metal intersection. PoFs of via patterning in 18nm pitch and 16nm pitch were obtained while swiping 3σ of CDU and OVL from 0.6nm to 2.2nm with the regular interval of 0.2nm; re-target bias and 3σ of LER were fixed as given in Table 2 for simplicity of the simulation; we assumed that OVL, CDU, and LER follow normal distributions. We also calculated reference PoF of via patterning which implies safe via patterning in 36nm pitch by using lithography requirements from ITRS 2015. Reference PoF was turned out as 1×10−7 , and we identified expected safe zone of OVL and CDU whose PoFs were comparable to or smaller than the reference one as illustrated in Figure 4. From this statistical analysis, we could conclude that 18nm pitch demands OVL and CDU of 1.0nm for safe via patterning, and even OVL and CDU of 0.8nm are required in 16nm pitch. Therefore, 2D SAV with EUVL may hardly drive pitch scaling beyond sub-20nm.
Proc. of SPIE Vol. 10148 101480J-3 Downloaded From: http://proceedings.spiedigitallibrary.org/ on 04/02/2017 Terms of Use: http://spiedigitallibrary.org/ss/termsofuse.aspx
Material A
Material C
Material B Material C
Re-targeted via
Via
Photo resist Etch
Etch
Material B Mx layer
Dielectric
Mx+1
Material A Metal
Mx
Mx+1 layer
(a)
(b)
(c)
Figure 5. (a) Top-down, (b) horizontal, and (c) vertical cross-sectional view of large marginal 2D SAV.
1.2 Large Marginal 2D SAV We propose a large marginal 2D SAV which targets via patterning in sub-20nm pitch. As shown in Figure 5(a), large marginal 2D SAV utilizes three different materials (A, B, and C) on cap-layer of Mx and on dielectric of Mx+1 ; material A and B alternately run within the metal trench of Mx+1 . Therefore, metal intersections, where vias will be formed, are identified as four different combinations of stacked materials (AA, AB, BA, and BB); AB intersection has material A and B within Mx+1 and Mx layers, respectively. Each combination is associated with a unique etch recipe; etch recipe AA, for example, can open a hole only at AA intersection using etch selectivity of material A, B, and C as shown in Figure 5(b) and (c). In this context, adjacent intersections are always free from opening unwanted hole, so we can obtain three times larger EPE margin compared to normal 2D SAV under process variations. We, however, need an individual mask for each etch recipe, so to pattern all vias in the layout four masks are required, which is not efficient in the perspective of manufacturing cost. To reduce the number of masks, we introduce two methods: 1) forbidden via rule and 2) merged etch recipe. The forbidden via rule restricts via appearance at some metal intersections during routing; for instance, if AB and BA intersections are restricted, then only two masks are required to open holes at AA and BB intersections. The rule makes routing less flexible, so its design impact is investigated in Section 4.2. In the second method, four different etch recipes are grouped into two to limit the mask count by two with no design restriction. Two masks for etch recipe AA and AB can be merged into one mask to be etched with recipe AAB which can make via holes at both AA and AB intersections; etch recipe AAB should etch material A longer than etch recipe AB. In this example, we need the other mask for etch recipe BBA instead of two masks for etch recipe BB and BA. Patterns which are obtained by our mask decomposition and re-targeting are investigated using source mask optimization (SMO) in terms of maximum edge placement error (EPE) and process variation band (PVB) width. The remainder of this paper is as follows: In the next section, one possible integration of large marginal 2D SAV is introduced. In Section III, we present initial mask image synthesis of the proposed two mask count reduction methods. In Section IV, SMO with the synthesized patterns is demonstrated. Section V summarize this paper, and remaining work is addressed.
2. LARGE MARGINAL 2D SAV INTEGRATION Large marginal 2D SAV integration includes two stages such as material stacking and via hole opening. The material stacking is illustrated in Figure 6: We first define a mandrel with two times of the metal pitch similarly to self-aligned double patterning (SADP) process. Spacer is then deposited around the mandrel and on low-k
Proc. of SPIE Vol. 10148 101480J-4 Downloaded From: http://proceedings.spiedigitallibrary.org/ on 04/02/2017 Terms of Use: http://spiedigitallibrary.org/ss/termsofuse.aspx
Low-k dielectric
Spacer Madrel
(a)
(b)
Photo resist
Metal
Material A
(c)
(d)
Rotation
Etch
Material C
(h)
(g)
Material B
(f)
(e)
Figure 6. Illustrative integration flow of large marginal 2D SAV.
dielectric (Figure 6(a)). The spacer is etched back and low-k dielectric is selectively etched to form a trench in between the mandrel lines (Figure 6(b)). Metal is then filled in the trench, and the over grown metal is planarized by chemical mechanical planarization (CMP); it is then recessed until it satisfies proper thickness (Figure 6(c)). We now deposit, planarize, and recess dielectric material A similarly to metal formation, so that cap-layer on Mx layer is settled (Figure 6(d)). Mandrel is then selectively etched while spacer and material A remain, and by repeating processes in Figure 6(b), (c), and (d), metal and another dielectric material B are placed within Mx layer and on the cap-layer, respectively (Figure 6(e)). The remaining spacer and low-k dielectric are selectively etched in the sequence while material A and B are intact. Then, another dielectric material C is also shallowly positioned in between material A and B (Figure 6(f)). We now stack Mx+1 layer in very similar manner to Mx layer stacking excluding metal fill; Figure 6(g) is the view in which Figure 6(f) is 90◦ rotated in horizontal direction, and Figure 6(a) is stacked on the top of it to repeat previous procedures in Figure 6(b), (d), (e), and (f). Unique interconnect structure for large marginal 2D SAV is finally obatined as shown in Figure 6(h). To form a via hole, we coat resist on the top and develop it after EUV exposure with via mask which is re-targeted with large margin and optimized by OPC tool. Although resist on the material B and C are also developed as shown in Figure 6(h) due to largely re-targeted via pattern, only material A is etched to form a via hole as illustrated in Figure 5(b) thanks to etch selectivity. To achieve a hole at AA intersection, we need to etch material A, low-k dielectric, and material A again, so etch recipe that can eliminate both material A and low-k dielectric at the same time is desired. After the selective etch process, resist for via patterning is removed, and another set of resist and mask is prepared for metal lithography of Mx+1 layer. Some regions of material A and B are then etched to form metal trenches. We finally fill metal into the via hole and the trench together (via first dual-damascene process). Note that, the cap-layer should be thick enough to reduce TDDB risk; metal on and underneath material B might interact each other if material B is too shallow.
Proc. of SPIE Vol. 10148 101480J-5 Downloaded From: http://proceedings.spiedigitallibrary.org/ on 04/02/2017 Terms of Use: http://spiedigitallibrary.org/ss/termsofuse.aspx
Etch target
Re-targeted via (square)
Re-targeted via (rectangle)
Forbidden via intersections Mx
Via
M
M at
er ial at B er ial A
Mx
Material A
Mx+1
Mx+1
Material B
(b)
(d)
Mx Etch target
Mx+1 (a)
Mx
Mx
Mx+1
Mx+1
(c)
(e)
Figure 7. Metal trench is simplified as lines. (a) Via layout with forbidden via rule; and decomposed mask images for vias on (b) AA and (c) BB intersections; corresponding re-targeted patterns (d) and (e), respectively.
Contour 1
Re-targeted via
Kissing corner
BP
(b)
Contour (a)
(d)
(c)
Figure 8. (a) Re-targeted via pattern with kissing corner, (b) peanut-shape contour, and (c) contour of two holes. (d) Re-targeted via pattern with BP.
Proc. of SPIE Vol. 10148 101480J-6 Downloaded From: http://proceedings.spiedigitallibrary.org/ on 04/02/2017 Terms of Use: http://spiedigitallibrary.org/ss/termsofuse.aspx
Re-targeted via (rectangle)
Etch target
Mx
M at
Via
M
er ial at B er ial A
Mx
BP
Material A
Mx+1
Mx+1
Material B
(b)
(d)
Mx Etch target
Mx+1 (a)
Mx
Mx
Mx+1
Mx+1
(c)
(e)
Figure 9. Metal trench is simplified as lines. (a) Via layout; and decomposed mask images for vias for (b) etch recipe AAB and (c) BBA; corresponding re-targeted patterns (d) and (e), respectively.
3. MASK COUNT REDUCTION 3.1 Forbidden Via Rule We propose to apply forbidden via rule to AB and BA intersections during placement and routing (PnR), so that vias are only located at AA and BB intersections as shown in Figure 7(a). Depending on via locations, we then decompose the layout into two mask images; one is for vias on AA intersection to be etched with etch recipe AA, and the other is for them on BB intersections as shown in Figure 7(b) and (c), respectively. We then re-target the via pattern in both directions; if, for instance, original via size is 9nm by 9nm, re-targeted via size becomes 36nm by 36nm thanks to large marginal 2D SAV integration. Note that, however, if some vias which are diagonally neighboring in original via layout should be inflated by half size in the direction of Mx+1 layer; thus, re-targeted via becomes 36nm by 18nm rectangle as shown in Figure 7(d) and (e). This is because if the neighboring vias are re-targeted as squares, either of AB and BA intersections that are exposed by both AA and BB masks must be etched; material A of AB intersection which is in the boundary of re-targeted via pattern for etch recipe AA is removed, and if the intersection is also involved in the boundary of re-targeted via pattern of etch recipe BB, then the rest material B is also removed, which is not desired. In re-targeted via mask images, we may find patterns in which their corners are kissed as shown in Figure 8(a). Due to lithography process variations two types of contour can be patterned as shown in Figure 8(b) and (c), which is problematic. In the stage of after-develop inspection (ADI), SEM image of every die is captured and compared to reference SEM image, so that different regions are flagged as defects.7 Therefore, we should unify the contour of Figure 8(a), otherwise, a number of defects are classified by ADI. Instead of increasing mask
Proc. of SPIE Vol. 10148 101480J-7 Downloaded From: http://proceedings.spiedigitallibrary.org/ on 04/02/2017 Terms of Use: http://spiedigitallibrary.org/ss/termsofuse.aspx
(a) f-1
f-4
f-3
f-2
(b) m-1
m-2
m-4
m-3
m-5
Figure 10. Popular re-targeted patterns of (a) forbidden via rule and (b) merged etch recipe. Table 3. Corner process conditions
Focus error (nm) ±40
Dose error (%) ±5
Mask error (nm) ±0.25
Flare error (%) ±1
Image blurring (nm) 3
count, putting small bridge pattern as illustrated in Figure 8(d) to form a peanut-shape contour consistently can be a solution.8
3.2 Merged Etch Recipe We propose another method which can reduce the mask count without sacrificing design flexibility. Via layout (Figure 9(a)) is decomposed into two mask images according to which intersection via is located on; vias on AA and AB intersections are extracted as illustrated in Figure 9(b) to be etched with the recipe AAB which is a sequential etch recipe of AA and AB, and the rest vias are drawn in the other mask image as shown in Figure 9(c) to be etched with the recipe BBA. We then re-target vias in mask images only into rectangular patterns because AA and AB intersections are adjacent in Mx+1 direction, so square shape re-targeting must open unwanted holes; BB and BA intersections are adjacent as well. BPs are also inserted at every kissing corners to avoid a number of defects in ADI; the final re-targeted via mask images for AAB and BBA are provided in Figure 9(d) and (e), respectively. Rectangular re-targeted patterns are merged if their edges are overlapped. The merged pattern is now more like line than via hole; in general, if ratio of vertical and horizontal length of pattern (or vise versa) is larger than three, the pattern is classified as line. CD observation in after-etch inspection (AEI) tells that CD of line width is more uniform than it of via hole,5 which is advantageous of line shape re-targeted pattern of large marginal 2D SAV. Tip of the pattern might has poor CDU, but it has large margin in that direction, so via is safely formed.
4. EXPERIMENTS We extracted via2 layer from logic design block (low density parity checker)9 which has metal grid was 42nm by 36nm, and scaled it into 18nm by 18nm one; thus, via size became 9nm by 9nm instead of 18nm by 18nm. By using Python script, two mask images with re-targeted patterns were generated in GDS format for each mask count reduction method. We investigated popular patterns of each method using Tflex SMO (ASML Brion); Figure 10(a) and (b) are the popular patterns in forbidden via rule and merged etch recipe, respectively. NXE3400 FlexPupil were used assuming N A = 0.33, and corner process conditions were summarized in Table 3; mask 3D effect was also taken into account in lithography simulation.
Proc. of SPIE Vol. 10148 101480J-8 Downloaded From: http://proceedings.spiedigitallibrary.org/ on 04/02/2017 Terms of Use: http://spiedigitallibrary.org/ss/termsofuse.aspx
Measurement range Metal intersection Target pattern
(a)
(b)
1.0
1.0
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0 2D SAV single via
f-1
f-2
f-3
f-4
m-1 m-2
m-3 m-4
m-5
Normalized Max. PVB width
Normalized Max. EPE
Figure 11. EPE measurement guide for (a) proposed re-targeted patterns and (b) conventional one of normal 2D SAV.
Re-targeted patterns
Figure 12. Maximum EPE and PVB width of proposed patterns.
4.1 Assessment of Re-targeted Patterns While square re-targeted via has 13.5nm space from target pattern to adjacent metal intersection in vertical and horizontal directions, but rectangular one has only 4.5nm space in vertical direction (or Mx+1 direction). We measured EPE of the most outer contour and process variation band (PVB) width in the measurement range in Figure 11, and the maximums were only collected; for instance, pattern m-2 in Figure 11(a) has four edges facing the metal intersections, so we measured EPEs and PVB widths for the four edges in the corresponding measurement ranges, and the maximums were turned out. Maximum EPE and PVB with of re-targeted patterns in normal 2D SAV were also obtained as a reference; however, its measurement ranges were given in vertical and horizontal because there were equal chances to touch the adjacent metal intersection in both directions. Maximum EPE and PVB width of the popular patterns which were normalized by the reference one are provided in Figure 12. Patterns in forbidden via rule were improved by at least 40% and 30% in terms of maximum EPE and PVB width, respectively. Pattern f-1, -2, and -3 which do not include rectangular patterns are all safe because of large space to adjacent metal intersection as well as small EPE and PVB width. Pattern f-4 is identified as the most concerned one due to relatively large PVB width, which was, however, 69% of the reference. As we expected, pattern m-1 in merged etch recipe method was the most safe pattern in terms of maximum EPE and PVB width. We also realized that pattern m-5 is required to be further optimized due to relatively large EPE and PVB width; this is because notch part in the pattern provided unstable contours.
4.2 Design Impact of Forbidden Via Rule We applied forbidden via rule to via2 layer during routing. IC Compiler (Synopsys) was used with commercial 28nm standard cell library for PnR. We simply applied blockage boxes at AB and BA intersections, but we observed that around 45% vias were violating the rule. As shown in Figure 13, we increased chip area to
Proc. of SPIE Vol. 10148 101480J-9 Downloaded From: http://proceedings.spiedigitallibrary.org/ on 04/02/2017 Terms of Use: http://spiedigitallibrary.org/ss/termsofuse.aspx
100
Area
80
0.9 0.8
60
Rule violating via
40
0.7
20
0.6
0 0.7
0.6
0.5
0.4
Ratio of rule violating vias (%)
Normalized chip area
1.0
Utilization factor
Figure 13. Chip area and ratio of rule violating vias along utilization factor.
provide more routability by reducing utilization factor, but still the ratio was intact. Therefore, we realized that conventional routing algorithm does not observe forbidden via rule.
5. CONCLUSION We conceptually proposed large marginal 2D SAV, which can be one solution for via patterning in sub-20nm pitch metal grid. We addressed two masks count reduction methods: 1) forbidden via rule and 2) merged etch recipe, and corresponding mask decompositions and pattern re-targetings were introduced. By demonstrating mask optimization lithography simulation with Tflex SMO, we figured out critical patterns in terms of max. EPE and PVB width. However, to actualize large marginal 2D SAV, integration realization and studies on routing algorithm for forbidden via rule are demanded.
REFERENCES 1. L. Hu et al., “Multi-layer VEB model: capturing interlayer etch process effects for self-aligned via in multipatterning process scheme,” in Proc. SPIE Advanced Lithography, Mar 2016, pp. 1–7 (97 800N). 2. I. Kamohara, W. Gao, U. Klostermann, T. Schm¨oller, W. Demmerle, K. Lucas, D. De Simone, E. Hendrickx, and G. Vandenberghe, “Experimental validation of stochastic modeling for negative-tone develop EUV resists,” in Proc. SPIE Advanced Lithography, 2015, pp. 1–15 (942 223). 3. S. Halder, M. Gallagher, J.-H. Franke, P. Leray, A. Junckers, and W. Clark, “EPE analysis of sub-N10 BEOL structure with Coventor’s SEMulator3D,” in Proc. SPIE Advanced Lithography, Mar 2017, pp. 1–8 (10 145–81). 4. D. C. Edelstein et al., “Interconnect structures with fully aligned vias,” Apr. 26 2016, US Patent 9,324,650. 5. T.-B. Chiou et al., “Impact of EUV patterning scenario on different design styles and their ground rules for 7nm/5nm node BEOL layers,” in Proc. SPIE Advanced Lithography, Mar 2016, pp. 1–17 (978 107). 6. T. Huynh-Bao, J. Ryckaert, S. Sakhare, A. Mercha, D. Verkest, A. Thean, and P. Wambacq, “Toward the 5nm technology: layout optimization and performance benchmark for logic/SRAMs using lateral and vertical GAA FETs,” in Proc. SPIE Advanced Lithography, Mar 2016, pp. 1–12 (978 102). 7. D. K. Lam, K. M. Monahan, E. D. Liu, C. Tran, and T. Prescop, “Multiple column high-throughput E-beam inspection (EBI),” in Proc. SPIE Advanced Lithography, Mar 2012, pp. 1–6 (83 240G). 8. S. Choi, J. U. Lee, V. M. B. Carballo, R.-H. Kim, and Y. Shin, “2D self-aligned via patterning strategy with EUV single-exposure in 3nm technology,” in Proc. SPIE Advanced Lithography, Mar 2017, pp. 1–8 (10 143–90). 9. OpenCores. [Online]. Available: http://www.opencores.org/
Proc. of SPIE Vol. 10148 101480J-10 Downloaded From: http://proceedings.spiedigitallibrary.org/ on 04/02/2017 Terms of Use: http://spiedigitallibrary.org/ss/termsofuse.aspx
