Redundant Via Insertion in Self-Aligned Double Patterning Youngsoo Song* † , Jinwook Jung* , and Youngsoo Shin* * School

of Electrical Engineering, KAIST, Daejeon 34141, Korea † Samsung Electronics, Hwasung 18448, Korea

ABSTRACT Redundant via (RV) insertion is employed to enhance via manufacturability, and has been extensively studied. Self-aligned double patterning (SADP) process, brings a new challenge to RV insertion since newly created cut for each RV insertion has to be taken care of. Specifically, when a cut for RV, which we simply call RV-cut, is formed, cut conflict may occur with nearby line-end cuts, which results in a decrease in RV candidates. We introduce cut merging to reduce the number of cut conflicts; merged cuts are processed with stitch using lithoetch-litho-etch (LELE) multi-patterning method. In this paper, we propose a new RV insertion method with cut merging in SADP for the first time. In our experiments, a simple RV insertion yields 55.3% vias to receives RVs; our proposed method that considers cut merging increases that number to 69.6% on average of test circuits.

1. INTRODUCTION With down scaling of semiconductor technology, 1-D based design is required due to the complexity of patterning process. For this reason, a single via is usually used, which is susceptible to process defects or electro-migration,1 RV insertion is a common practice as a complementary method for chip design using single via to enhance chip yield and reliability.2 RV insertion can form a 2-D layout depending on the RV position for original via, which makes fabrication process complex, but it is required continuously because it can prevent electrical short caused by defects and mitigate the adverse effect of electro-migration. The RV insertion is performed through a graph formulation, with the goal of inserting as many RVs as possible while ensuring the manufacturability.3 Consider a layout shown in Figure 1(a), where the RV candidates for each via are identified. A conflict graph is introduced in which a vertex represents an RV candidate. RV of net 2 can only be placed in the position denoted by 2a, because 2d causes electrical short with other nets, right position is blocked by different net and a position below is also blocked by net 4. For net 4, 4b and 4d are candidate locations; we do not place two RVs, so 4b and 4d has a conflict modeled as an edge. Similarly, 3a, 3c, and 3d are candidates for net 3, and are connected by an edge. For 2a and 3d have a via color conflict as an odd cycle error when we assume two mask for via layer, and an edge is also created. Therefore, for RV candidates, the RV insertion problem can be reduced to the maximum independent set (MIS) problem on the conflict graph; the MIS corresponds to RV candidates of the maximum number without any conflict.

1.1 Motivation and Contributions When RV is inserted in SADP process, it can also be formulated as a conflict graph, and MIS corresponds to desired solution. However, new problem is created in RV insertion, which there are less candidate RV positions (thus less number of vertices) and more conflicts (and thus more edges) due to conflicts between adjacent cuts, either line-end or RV. Consider a layout shown in Figure 1(b), if RV is inserted in 4d, we need an RV-cut∗ for metal2; it may be too close to line-end cut introduced for metal line above, so 4d is dropped from a candidate. For similar reason, 4b is also dropped from conflict graph, which causes no available RVs for net 4. Furthermore, as shown in Figure 1(c), if RV is inserted in 3c, an metal3 RV-cut is assigned and it is also excluded as a RV candidates due to small space conflict with below line-end cut. On the other hand, if RV-cuts are assigned in 2a and 3a, they have a distance which can not be decomposable to different color, and then an edge is created. The conflict graph now has few vertex, so we cannot insert RVs as many as possible for the example layout. Conflicts ∗

We define the new cut assigned to form the RV position as an RV-cut. Design-Process-Technology Co-optimization for Manufacturability XI, edited by Luigi Capodieci, Jason P. Cain, Proc. of SPIE Vol. 10148, 1014806 · © 2017 SPIE CCC code: 0277-786X/17/$18 · doi: 10.1117/12.2258036 Proc. of SPIE Vol. 10148 1014806-1

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Net4

Line-end cut RV-cut

2d Net2

RV-cut

2a

2a

4d

4d

2a

3d Net3

3a

3c

3a

4b

3c

4b

3a

3c

Space conflict 2a

4d

2a

3d 3a

3c

Line-end cut

4d

3d

4b

3a

4d

2a 3d

3c

4b

3a

4b

3c

Conflict graph (a)

(b)

(c)

Figure 1. (a) RV candidates modeled as a conflict graph; a vertex corresponds to RV candidate, and an edge represents a conflict between two candidates, (b) conflict graph after cut conflict in metal2 is considered, and (c) conflict graph after cut conflict in metal3 is also considered. Mandrel

Target pattern

Spacer

Mandrel & spacer (Litho-Etch)

Cut mask (Litho-Etch)

Block mask (Litho-Etch)

Patterning

Figure 2. SADP process based on SID which consists of mandrel, cut, and block mask.

between cuts caused by RV insertion and adjacent line-end cuts should be minimized so that the maximum number of RVs can be accommodated. In this paper, we propose an RV insertion method for SADP process that effectively removes the cut conflict caused by the RVs, and thereby increases the number of RVs to be inserted. The proposed method consists of two steps: the identification of RV candidates without SADP conflict and the graph-based RV insertion considering SADP constraint. We introduce the concept of cut merging to reduce the number of cut conflicts because less number of RVs is generated on a conflict graph in SADP. For RV candidates after detailed routing, we first check each RV candidate which the corresponding RV-cut is mergeable with neighboring line-end cuts or RV-cut. We then formulate a conflict graph with the RV candidates having mergeable RV cuts, and insert RVs by solving the MIS problem. Our method is applied to various test circuits using an industrial SADP process. The effectiveness of the proposed approach in the increase of the number of RVs will be demonstrated by comparing to the conventional RV insertion method without consideration of cut conflicts. The remainder of this paper is organized as follows. Section 2 describes SADP process, and defines of line-end cut and RV-cut in SADP process. Our solution and its cut merging condition for RV insertion in SADP are introduced in Section 3. Section 4 shows experimental results, and Section 5 gives some concluding remarks.

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Metal2 extension

Metal2 RV-cut

Metal3 line-end cut

Metal3 extension

RV Via2

Net2

M3

M2 (a)

(b)

(c)

Figure 3. (a) Example layout with RV, (b)-(c) metal extension and cut mask assignment for metal2 and metal3, respectively. Metal

Line-end cut

Dummy metal

(a) For isolation from dummy metal Dummy metal RV

RV-cut 3x metal width

Target pattern

Mandrel & Spacer

After RV-cut

Block mask

Final results

(b)

Figure 4. (a) Definition of line-end cut and (b) formation procedure of extended metal to RV using RV-cut and block mask in SADP process.

2. PRELIMINARIES 2.1 SADP Process Conventional SADP process, which consists of mandrel, cut, and block mask, is illustrated in Figure 2. For a given target pattern, mandrel is regularly arrayed every two pitches of metal wire. Self-aligned sidewall spacers, which is different material having etch selectivity for the mandrel, are formed by mandrel etch-back process. Based on spacer-is-dielectric (SID) process, unnecessary sidewall spacers to isolate the metal wire are removed by using a cut mask and filled with the same material as mandrel.4 Wide and 2-D metal pattern are formed by block mask as a post process. Finally, the required metal wires can be formed with copper and dummy metal is defined for remaining area which is no metal wire. The advantage of SADP process can make uniform and regular patterns following a series of these process. Furthermore, process variations by lithography or loading effect of etch process can be reduced by relatively large pattern align margin since a mask can be placed between arrayed patterns.

2.2 RV Formation in SADP The purpose of RV insertion is to supplement yield by adding additional vias where it is vulnerable to metal connections in a limited chip area. Assuming that metal2 has a reserved routing of horizontal direction and

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Cut optimization

Place & Routing

RV cut assignment

Cut merge

1. General constraint - Avoid different net

1. RV-cut and adjacent line-end cut

2. SADP constraint - Cut conflict

2. RV-cut and RV-cut

RV maximization by MIS

Fabrication process

Figure 5. Overall flow of the proposed method.

metal3 is routed in vertical direction, metal2 and metal3 can form 2-D pattern depending on the RV position for via2 layer. RV insertion requires metal extension as well as cut mask assignment in SADP. In Figure 3(a), if RV is inserted in the north position for via2 layer, both metal2 and metal3 should be extended so that they can be connected through RV. The metal2, which is reserved for horizontal connections, is extended in non-preferred vertical direction and this requires new cut for RV, which is RV-cut (Figure 3(b)). On the other hand, metal3 is extended in its original vertical direction, which simply requires line-end cut to be re-positioned as shown in Figure 3(c). We introduce an RV-cut to form the RV position with newly assigned cut as we mentioned in Section 1. Generally, in SADP process, line-end cut simply divides long metal wire, formed through SADP process, into real signal wire and dummy metal (Figure 4(a)). However, RV-cut is very different and more complex. Assume that RV is inserted in target pattern of Figure 4(b) , and horizontal metal should be extended in non-preferred vertical direction. RV-cut, whose width is 3 times that of metal, is formed. This is to ensure enough space from dummy metal on the left- and right-side. Actual extension in vertical direction is made through a block mask, which finally yields a target pattern with dummy metals in final results. In this way, RV formation in SADP process has a complex process, but it has the advantage of forming an RV without additional masks.

3. PROPOSED SOLUTION 3.1 Overall Flow The overall flow for the proposed RV insertion in SADP process is shown in Figure 5. It optimizes the relationship between RV-cuts and line-end cuts (in two metal layers under consideration) so that the number of inserted RVs is maximized. An input of the proposed method is a target via layout as well as upper and lower metal layouts after detailed routing. Line-end cuts in two metal layers are first identified by standard cut optimization.5 Final RV candidates are filtered out by SADP constraint such as cut color conflict in RV position; in this case, it is applied sequentially to metal2 and metal3 layers. If RV-cut formed at the RV position can be merged with nearby line-end cut or other RV-cut, corresponding edge is dropped or a node that has been removed due to cut conflict re-appears. Merged cuts should be separated by stitch using LELE process. The final graph is solved through MIS,6 considering the design rule check which is performed on the final added RVs by cut merging. If there are no design rule violations, dummy metal for each layer is generated to meet the metal density.

3.2 Cut Merging When RV is inserted after cut assignment, some of RV cuts are eliminated to resolve conflicts with pre-existing line-end cuts and RV-cuts. RV insertion is performed on RV cuts surviving from conflicts. It is done by a standard MIS-based RV insertion method; a conflict graph for RV insertion is created with those RV candidates. Then the RV insertion problem is reduced to a MIS problem and RVs can be inserted by MIS solution. When the RV insertion is performed in the SADP process, the biggest consideration is to minimize the conflicts by SADP constraints. Since the pre-existing line-end cuts do not consider RV-cut for RV position, the conflict RV-cut with the adjacent line-end cuts can be occurred and a conflict graph in SADP yields less number of RVs. Thus,

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1a RV-cut

1a

1a 1b

2b

RV-cut

1b

2b

1a 1b

1b

2b

2b

Net2 1a Net1

(b)

1a 1b

1b

2b

2b

Line-end cut RV-cut 2c

(a)

1b

2b

2c

1a 1b

2b

2c 1b

2b

2c

1a 1b

2b

(c)

Figure 6. (a) RV candidates, (b) cut merging allows the edge between 1b and 2b to be dropped, and (c) cut merging yields a new vertex 2c.

we introduce the concept of cut merging to reduce the number of cut conflicts. For instance, the identified RV candidates by general constraints are shown in Figure 6(a). In Figure 6(b), 1b which is RV position for net 1 and 2b which is RV position for net 2 has an edge, because their corresponding RV cuts are too close. However, if the two RV-cuts are merged, two RVs can be placed together which allows us to remove the edge. In the second example denoted as Figure 6(b), 2c is not valid vertex in the original conflict graph because its RV-cut is too close to line-end cut for vertical connection of net 2. However, if the two cuts, RV-cut and line-end cut in this case, are merged, 2c is now a valid vertex.

3.3 Conditions for Cut Merging In SADP process favorable for 1-D grid based design, the conflicts by SADP constraint can make RV insertion worse and it is not enough for enhancement of chip yield. As a solution to increase the RV insertion rate, we propose cut merging between RV cuts and RV cuts or line-end cuts. A prerequisite for a cut merging is involved, merged cut must be decomposable by stitches since it can form a variety of shapes. For a given 1-D based layout, we assign line-end cut locations considering to different cut masks. And then, for the RV candidates survived by the general constraint, the cut merging is determined sequentially for metal2 and metal3 cut. We categorize cut merging conditions in Figure 7 and how they can be merged as follows: • RV-cut and adjacent line-end cut are abutted or overlapped each other, which are merged. And then, RV from RV-cut location becomes valid vertex as shown in Figure 7(a). They are then patterned using mask A and mask B with some stitch. • In case one line-end cut is placed with less than different color space for RV-cut, they can be merged each other and become valid vertex if there is no metal in-between them (Figure 7(b)). However, in case two line-end cuts are located in different color boundary, they should be as far apart as different color space since merged two line-end cuts for RV-cut should be patterned to same mask by LELE process (Figure 7(c)). • If RV cuts are aligned on the same track vertically or horizontally, and they have a small distance which can not be decomposable to different color, two RV-cuts can be placed together which allows us to remove the edge (Figure 7(d)).

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RVL cut

Line-end cut

RV-cut

Mask A

Stitch

Mask B

< Minimum space

(a)

Line-end cut

Different color boundary

RV-cut

(b) RV-cut

Different color boundary

RV-cut

< Minimum space

< Diff color space

RV-cut

< Minimum space (c)

(d)

Figure 7. (a) Abutted or overlapped RV cut and line-end cut, (b) RV-cut and line-end cut within a minimum coloring distance, (c) RV-cut and two line-end cuts within minimum coloring distance, and (d) aligned RV-cuts on the same track vertically or horizontally.

4. EXPERIMENTAL RESULTS We implemented the proposed method with Python and C++, and adopted Gurobi7 as the ILP solver for cut mask optimization after detailed routing. Various test circuits from OpenCores,8 ITC’999 and ISCAS’8910 benchmarks were used to obtain experimental results. They were synthesized using a 28-nm industrial library; placement and routing were performed assuming a 1D-gridded design rule. RV insertion is demonstrated in via2 layer that connects metal2 and metal3. So for each RV candidate, its RV-cut and line end-cut are identified both in metal2 and metal3 layers. The metal2, metal3 and via2 layers for each circuit were appropriately shrunk to follow a 10-nm design rule. Metal track pitch is 50nm, and a single via has a size of 50nmby50nm. We assumed two masks are available for cut optimization. To solve MIS, the algorithm presented in Boppana et al.11 was employed. Three RV insertion methods (Unconstrained, SADP RV, and Proposed) are compared in terms of the RV insertion rate in Table 1. The number of vias ranges from 3k (s5378) to 120k (fpu) as shown in the second column of Table 1; test circuits are designed with place and routing of utilization factor 0.7. The UC is the method that electrical short for different net as general constraint is only considered for given layout. The average percentage of RV using UC is 96.5%, but via results in a large number of non-zero defect probability (i.e. unmanufacturable vias) in SADP as indicated in the fourth column. For the sake of reference of comparison, the RV insertion without cut merging in SADP, named SADP RV, and the proposed method considered cut merging for RV insertion in SADP, are applied. In the case of SADP RV, only 56.0% vias on average of test circuits receive RVs due to the conflict of inserted RV-cuts and adjacent cuts. In the proposed method, on the other hand, Cut merging allows us to increase the percentage to 69.6% on average, which is 13.6% higher than SADP RV. In the test circuit, the RV insertion rate is uniform regardless of the number of vias. For some test circuits, as shown in Figure 8, if layout area decreases and routing becomes more denser due to increased utilization factor, we expect more number of conflicts and thus less number of RVs. This in fact is true in two example circuits shown in this chart, but the RV insertion percentage (compared to RV insertion without cut merging) does not vary that much. This proves the robustness of proposed cut merging; in other words, even if layout area is small and routing is dense, many cuts can still be merged.

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Table 1. Comparison of three RV insertion methods. Circuit

#Vias

s5378 3,524 des3 area 9,421 b15 19,870 s38417 27,235 b14 1 29,775 ac97 ctrl 31,864 usb funct 38,323 aes core 44,936 sd card 45,547 b17 60,666 fpu 124,279 Average 100 90

UC SADP RV Proposed #RVs (%) #Conflicts #RVs (%) #RVs (%) 97.3 3,237 60.6 73.7 95.1 8,737 51.1 65.2 96.0 18,260 54.8 67.5 97.2 24,849 60.3 74.7 96.7 27,783 54.7 68.3 97.2 29,603 59.9 74.5 96.1 35,495 56.4 69.9 94.7 41,567 49.2 62.0 97.1 41,849 59.6 74.4 96.1 55,717 53.9 67.4 97.5 116,937 55.4 68.4 96.5 56.0 69.6

Without cut merging (ave. 52.6%)

des3_area

fpu

With cut merging

des3_area

fpu

(ave. 65.6%)

RV insertion rate (%)

80 70 60 50 40 30 20 10 0

0.65

0.70

0.75

0.80

Utilization factor

0.85 Small area Denser routing

Figure 8. Comparison of RV insertion without- and with-cut merging (for two test circuits), while utilization factor is varied.

5. CONCLUSIONS We have proposed a RV insertion method to enhance chip yield in SADP process. RV candidates are first selected by the general constraint to insert as many RVs as possible. And then, considering the SADP constraint, the cut conflict graph has been formed from the relationship of RV-cuts and adjacent line-end cuts. The RV can be inserted maximally by solving maximum independent set; conflict edge can disappear and vertex can revive through cut merging to increase RV insertion rate in SADP process. Our proposed method has been demonstrated in sub10nm technology using various test circuits. Experimental results have indicated that the RV insertion rate for proposed method is around 69.6% on average of test circuits. In our experiment, RV insertion is only performed for via2 layer that connects metal2 and metal3, but it can be applied to other layers using SADP process. This study presents for the first time RV insertion method with cut merging in SADP after place and routing stage. To improve RV insertion rate in SADP, an extension to cut mask optimization, which is considered line-end cut and RV-cut simultaneously, is left for future investigation.

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ACKNOWLEDGMENTS This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP) (No. 2015R1A2A2A01008037).

REFERENCES 1. J. Pak, B. Yu, and D. Z. Pan, “Electromigration-aware redundant via insertion,” in Proc. Asia South Pacific Design Automation Conf., Jan. 2015, pp. 544–549. 2. P. Gupta and E. Papadopoulou, “Yield analysis and optimization,” The handbook of algorithms for VLSI physical design automation, 2008. 3. K.-Y. Lee and T.-C. Wang, “Post-routing redundant via insertion for yield/reliability improvement,” in Proc. Asia South Pacific Design Automation Conf., Jan. 2006, pp. 303–308. 4. Y. Du, Q. Ma, H. Song, J. Shiely, G. Luk-Pat, A. Miloslavsky, and M. Wong, “Spacer-is-dielectric-compliant detailed routing for self-aligned double patterning lithography,” in Proc. Design Automation Conf. (DAC), May 2013, pp. 1–6. 5. J. Kuang, E. F. Young, and B. Yu, “Incorporating cut redistribution with mask assignment to enable 1d gridded design,” in Proc. Int. Conf. Computer-Aided Design (ICCAD), Nov. 2016, pp. 48–55. 6. K. Y. Lee, T. C. Wang, and K. Y. Chao, “Post-routing redundant via insertion and line end extension with via density consideration,” in Proc. Int. Conf. Computer-Aided Design (ICCAD), Nov. 2006, pp. 633–640. 7. Gurobi optimizer reference manual. [Online]. Available: http://www.gurobi.com 8. OpenCores. [Online]. Available: http://www.opencores.org 9. ITC99. [Online]. Available: http://www.cerc.utexas.edu/itc99-benchmarks/bench.html 10. “ISCAS89.” [Online]. Available: http://www.cbl.ncsu.edu/benchmarks/ISCAS89/ 11. R. Boppana and M. M. Halld´ orsson, “Approximating maximum independent sets by excluding subgraphs,” BIT Numerical Mathematics, vol. 32, no. 2, pp. 180–196, Jun. 1992.

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