Sample Questions-2014 SUB: Digital Electronics & Logic Design Sub Code: EC402 STREAM: ECE
1.
Sem: 4th
Group A (Answer any ten)
(i) Decimal equivalent of binary number1111.01 is (a) 14.25 (b) 15.25 (c)15.01 (d) 7.25 (ii) Which of the following code is a weighted code? (a) Excess-3 code (b) shift-counter code (c) gray code (d) 5111 code (iii)The gray code equivalent of binary number (1000001)2 is (a) 1100001 (b) 1100011 (c) 1000011 (d) 110101 (iv) ASCII code is used as a (a) Alphabetic code (b) cyclic code (c) weighted code (d) alphanumeric code (v) Half adder is also known as (a) AND circuit (b) NAND circuit
(c) NOR circuit (d) XNOR circuit
(vi) Which gate is called ‘Controlled inverter’? (a) AND gate (b) OR gate (c) XOR gate
(d) NAND gate
(vii)
Which of the following gates is known as “coincidence detector”? (a) AND (b) OR (c) NOT (d) NAND
(viii)
The open collector output of 2 input NAND gates are connected to a common pull up resistor. If the input to the gates are P,Q and R,S respectively, the output is equal to (a) (P.Q)/(R.S)/ (b) (P.Q)/+(R.S)/ (c) P.Q+R.S (d) P.Q.R.S
(ix) In standard TTL gates, the totem pole output stage is primarily used to(a) Increase the noise margin of the gate (b) decrease the output switching delay (c) facilitate a wired or logic connection (d) increase the output impedance of the circuit (x)
The number of comparisons carried out in a 4 bit flash type A/D converter is (a) 16 (b) 15 (c) 4 (d) 4
(xi) The digital Multiplexer is basically a combination logic circuit to perform the operation (a) AND-AND (b) OR-OR (c) AND-OR (d) OR-AND (xii) A switch tail ring counter is made by using a single D FF. The resulting circuit is (a) SR flip-flop (b) JK flip-flop (c) D flip-flop (d) T flip-flop
Group B (Answer any three) 1. (a) Describe the Demorgan’s Law. (b) Simplify the expressions by Boolean Algebra. (A+B)(A+A/B)C + A/(B+C/) + A/B + ABC 2. (a) Simplify using K-Map in SOP form and make the circuit. f(A,B,C,D)=∑m(1,2,4,5,9,10) +d(6,7,8,13) (b) Obtain the simplified expression in POS form using K Map. F ( A, B, C, D) m (0,1,2,3,4,5) d (10,11,12,13,14,15) 3. Design a Full Adder circuit using two Half adder and an OR gate. Explain it. 4. (a) Subtract using the 9’s complement method: 436.62-745.81. (b) Add 27.125 to -79.625 using the 12 bit 2’s complement arithmatic. 5. Explain a 4bit BCD adder circuit. 6. Design a 3 bit Even parity generator and checker circuit. 7. Describe a Successive approximation type A/D converter. 8. What is the difference between Ring Counter & Jonson Counter? Group C (Answer any three) 9. (a) Design the binary to Gray code converter. 10. Design a 4 to 16 Decoder using 3 to 8 Decoder 11. What is Priority encoder? Design a 4 to 2 Priority Encoder. 12. (a) Design AND, OR, XOR, XNOR using NAND gate. (b) Using the Tabular Method ,obtain the minimal expression for F=∑m(6,7,8,9)+d(10, 11, 12, 13, 14, 15) 13. (a) (b)Implement the following logic function using an 8:1MUX. F(A,B,C,D)=∑m (1,3,4,11,12,13,14,15) (c) Design a 16:1 MUX using 4:1 MUX 14. (a) Convert a D flip-flop to J-K flip-flop. (b) Describe the SISO & PIPO Shift register. (c) Design a MOD- 6 Up - Down Counter. 15. Short Notes: (answer any three) (a) Operation of TTL NAND gate and calculate its FAN-OUTS. (b) Describe the PLA & PAL & PROM using a suitable example. (c) Race around condition & its solution. (d) Describe the Weighted –Resistor type DAC. (e) Describe the555 Timer