Sigma Delta Modulators with Modified Hybrid Integrators Shankar Thirunakkarasu, Abul Bashar M Ishteak Hossain and Bahar Jalali Farahani Department of Electrical Engineering, Arizona State University, Tempe, AZ [email protected], [email protected], [email protected] Abstract- This paper describes a modified second-order sigmadelta (ΣΔ) modulator using hybrid integrators that is designed for WLAN applications. Hybrid integrators are composed of analog and digital integrators where the overflow of an analog integrator is processed by a digital integrator which results in the improvement of dynamic range. It is shown that the presented modulator achieves 8-dB improvement in dynamic range compared to conventional sigma delta modulator with the same oversampling ratio (OSR) and also it is very robust incase of any mismatch between the analog and the digital blocks. Another significant advantage of this scheme is that the overload level (OL) is increased by about 8.6-dB. The presented modulator architecture is implemented using a sampling frequency of 320MHz for a 10MHz signal bandwidth with an oversampling ratio of 16.

I.

INTRODUCTION

Sigma Delta converters are able to achieve high resolution without the need for high-precision analog circuits using oversampling and noise shaping techniques. In particular, single-loop 1-bit sigma-delta (ΣΔ) ADCs are very popular for their simplicity and insensitivity to imperfections of analog circuits [1]. However, performance of higher order single-loop modulators is limited because of stability concern. A common technique to realize a stable high-order modulator is to use multistage or MASH architectures. However, multistage architectures are prone to noise leakage due to the inevitable mismatch between analog loop filters and the digital noisecancellation filters. Although high-order modulators can be stabilized using multibit quantizer, it enforces stringent requirement on the linearity of the feedback digital-to-analog converter (DAC) [1]. The accuracy of the DAC needs to be as good as the accuracy of the overall modulator. Higher order modulators have degraded performance due to the early saturation or overload of the integrators. Also as supply voltage reduces due to the technology scaling, the available signal swing is reduced, thereby limiting the dynamic range of the modulator and even jeopardizing stability. These problems could be minimized by using local feedbacks around the loop-filter integrators. An overload estimating unit (OLE) for judging the saturation or overload of an integrator can be employed in the local feedback path of each integrator. If the integrator is expected to be overloaded or saturated, the OLE subtracts a pre-defined value from the integrator input. Meanwhile, the same amount is added to and processed by the

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digital integrator. In this manner, the effective signal swing of the integrator can be increased which leads to the improvement of the dynamic range of the modulator [2]. This paper describes a second-order modulator that employs mixed-mode integrators designed for WLAN applications. To understand the novelty of the hybrid mixed-mode sigma delta data converter, a comparison with a general 2nd order sigma delta converter will be demonstrated in terms of DR, SNR and OL. Significant improvements with respect to these performance metrics are reported here. The paper is organized as follows. Section II briefly describes the modulator architecture. The improvements of the modulator structure are brought in section III. Section IV shows an example of system level implementation of this modulator in MATLAB together with its advantages over the conventional design. Section V addresses circuit implementation done in TSMC 0.35um technology. The paper is concluded in section VI. II. MODULATOR ARCHITECTURE The modulator architecture is shown in Fig. 1. The mixedmode integrator is a combination of an analog integrator and a digital integrator. The modulator described in [2], [4] can be viewed as a single-loop modulator with analog integrators Analog

Digital

Fig.1. Block diagram of the hybrid integrator scheme replaced by mixed-mode integrators. In contrast to the conventional design, no global feedback exists in the analog path. That removes the need for a DAC whose accuracy is a limiting factor to the conventional high resolution sigma delta converters.

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No global feedback in analog signal path also guarantees stability provided that the local feedbacks around the analog integrators work properly. The overload estimator (OLE) as shown in Fig. 2 monitors both the input and the output of the integrator in order to decide whether the integrator will be saturated or not. If the integrator output is expected to exceed +vref, then +vref is subtracted from the input of the integrator. Similarly, if the output exceeds –vref then +vref is added to the input. This ensures that the integrator output stays within the range of [-vref, +vref].

Fig.3. Conventional Architecture

Similar to the MASH structure, sigma delta modulators with

III. PROPOSED IMPROVED ARCHITECTURE Here we consider a feedback architecture. The original architecture for a first order hybrid sigma delta modulator as proposed in [2], [4] in addition to feedback is depicted in Fig. 3. The input-output relationship is as follows:

Fig.2. Block diagram of the OLE hybrid integrators are prone to leakage noise caused by the mismatch between the digital and analog integrators. Calibration techniques similar to the one used in the MASH sigma delta modulator should be employed. This topic is outside the scope of this paper.

From the above equations, it can be seen that in case of a mismatch between the analog and digital paths, the mismatch error will appear at the output with a unit delay.

In this work, we used two important modifications to the design of the sigma delta modulator with hybrid integrators as proposed in [4]. Using these techniques result in significant improvement in signal to noise ratio (SNR) and Dynamic Range (DR) of the modulators. The modifications are discussed here. A. OLE +/- vref level change Significant improvement of SNR, OL and DR can be made by changing the OLE levels. In the modified design of [4], +/2vref is subtracted from the input instead of +/-vref in the conventional design during saturation. This ensures that the input to the integrator always remains close to the full-scale where it results in the maximum SNR. B. Change in one bit quantizer levels In this architecture, the output of the quantizer is fed only to the digital path and the input full scale is related only with the signal swing of the first mixed-mode integrator. As a result, the quantizer output level can be reduced by half. Since the input to the quantizer is the output of a mixed-mode integrator, the input is strictly limited within [-vref, +vref] and the maximum error due to quantization is vref/2, which is half of the maximum error of a conventional quantizer. Improvement of SNR, OL and DR can be observed by changing the quantizer levels.

Fig.4. Proposed Architecture Our proposed architecture is shown in Fig. 4 and its inputoutput relationship is derived:

In this case, it is shown that if there is a mismatch error, it will be high pass filtered before it appears at the output. This architecture is therefore more robust to the mismatch error compared to the conventional architecture discussed in [2], [4]. To illustrate the performance improvement occurring in the proposed architecture, a plot of SNR degradation versus the mismatch is shown in the Fig.5.

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output 1st analog integrator

output 2nd analog integrator

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Fig.5 SNR Degradation vs Mismatch factor

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Fig. 7. Output of analog and digital integrators

IV. SYSTEM LEVEL IMPLEMENTATION System level implementation in MATLAB was done for the hybrid integrator. Output power spectral density is given in Fig. 6. Transient outputs of the analog and digital integrators are shown in Fig. 7. Here the analog integrator outputs are within +/- vref levels but the digital integrator outputs can go beyond +/- vref which is expected. SNR as a function of input amplitude is plotted in Fig. 8. The hybrid integrator was compared with a conventional modulator and with the architectural improvements discussed in section II and III. It can be seen that the SNR improves by almost 19-dB as compared to the conventional scheme. Also OL and DR increases by 8.6-dB and 8-dB respectively. The achieved results are given in Table 1. TABLE I Comparison of different modulator schemes SNR Peak

Conventional Modulator 55.26 dB

Conventional Hybrid 61.94 dB

Improved Hybrid Scheme 74.84 dB

OL

-9.8 dB

-3.2 dB

-1.2 dB

DR

54.2 dB

59.1 dB

62.1 dB

Fig. 8. SNR vs input amplitude V. CIRCUIT LEVEL IMPLEMENTATION The modulator is designed targeting WLAN applications. Although the dynamic range requirement for this application depend on the receiver architecture, typically more than 65 dB over a 10-MHz signal bandwidth is required. The proposed modulator can meet these requirements with low OSRs of 16. The corresponding clock frequency is 320 MHz. A. Analog Integrator The closed loop gain of the integrator is designed to be unity and the sampling capacitor and the feedback capacitor are of the same size of 300fF.

Fig. 6. Output spectra of the second order hybrid modulator

The operational amplifier shown in Fig.9, which is a fully differential telescopic cascode amplifier with folded cascode gain boost stages and a switched-capacitor common-mode feedback circuit. The Opamp is designed to have unity gain bandwidth of 1GHz with 0.5pF load and a dc gain of 120 dB. It has a phase margin of 49 degrees and consumes 15mW power. In order to reduce signal-dependent resistance, the integrator input is connected to the sampling capacitors through

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bootstrapped switches [3]. Other switches are transmission gates. The integrator is driven by non-overlapping two-phase clocks and their delayed versions. The timing of clocks is illustrated in Fig. 10. While Φ1 is on, signals are sampled on capacitors and the next output of the integrator is estimated by the OLE. During the non-overlapping interval between Φ1and Φ2, the OLE determines the local feedback signal using a comparator shown in Fig. 11 that consists of a pre-amplifier and a latch whose conversion time is less than 1ns. When Φ2 is on, the next actual output of the integrator is evaluated and the OLE is tracking the integrator output for use in the next cycle.

Fig. 11. Comparator with pre-amplifier

B. Overload Estimator (OLE) The OLE roughly calculates the next integrator output before

Fig. 12. Overload Estimator (OLE) and negative terminals of the Opamp respectively and 1.5V and 2.5V is given when it exceeds the negative threshold. The bit widths of the digital integrator should be carefully determined. OL_H = High if, (Vip-Vin)+(Vop-Von) > (Vrefp-Vrefn) (8) OL_L = High if, (Vip-Vin)+(Vop-Von) < -(Vrefp-Vrefn) (9) Therefore, the round-off errors do not deteriorate the performance. The register of the digital integrator needs 14 bits with some margins for proper operation of the modulator.

Fig. 9. Fully differential telescopic cascode amplifier with a switched-capacitor common-mode feedback

VI. CONCLUSION Sigma delta modulators using hybrid integrators offer increased dynamic range, SNR and OL compared to their conventional counterparts. However, the performance would be limited due to the inevitable mismatch between the analog and digital filters. Our proposed second-order hybrid modulator shows a robust performance while meeting the dynamic range requirements of WLAN applications. It is attractive for modern VLSI technologies, wherein the swing of analog signal is seriously limited while digital circuit performance is improved in size and power consumption.

Fig. 10. Phase timing diagram the real value is evaluated in order to check whether the integrator will be saturated or not. A simple passive network of switches and capacitors as shown in Fig. 12 is used for the OLE. The OL_H and OL_L signals are fed at Φ2 and vrefp, vrefn or gnd is sampled to the integrator input for proper estimation based on the following (8) and (9) equations. The OLE function could be described as follows: when the addition of the difference in the input and output exceeds a positive threshold, OLE gives 2.5V and 1.5V to the positive

REFERENCES [1] [2] [3] [4]

S. R. Norsworthy, R. Schreier, and G. C. Temes, Delta-Sigma Data Converters: Theory, Design, and Simulation. NewYork: IEEE Press, 1997. B. Kim and T. Kim, “Sigma-Delta Analog-to-Digital Converter using Mixed-Mode Integrator,” U.S. Patent 6,424,279, Jun. 23, 2000. A. Abo and P. R. Gray, “A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 599–606, May 1999. J.Shim, I. Park and B. Kim, "A third-order ΣΔ modulator in 0.18 um CMOS with calibrated mixed-mode integrators," IEEE J. Solid-State

Circuits vol. 40, no.4, pp. 918–925, April 2005.

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