Sigma Delta Modulators with Hybrid Integrators ( Final Project of Oversampling Σ∆ Class, Fall 2007 ) Abul Bashar M Ishteak Hossain Department of Electrical Engineering Arizona State University Tempe, AZ [email protected]

Shankar Thirunakkarasu Department of Electrical Engineering Arizona State University Tempe, AZ [email protected]

Abstract- This paper describes a modified second-order sigmadelta (Σ∆) modulator using mixed-mode integrators designed for WLAN applications. Hybrid Sigma Delta modulators use analog and digital integrators to improve the dynamic range. In these modulators, digital integrators process the overflow of the analog integrators hence delay the saturation of analog integrators which in turn results in extended dynamic range. The presented modulator achieves 8-dB (19 dB) improvement in dynamic range (signal to noise ratio) compared to conventional modulator with the same oversampling ratio (OSR). Another significant advantage of the proposed structure is that the overload level (OL) increases about 8.6-dB. The presented modulator architecture is implemented using a sampling frequency of 320MHz for a 10MHz signal bandwidth with an oversampling ratio of 16.

I.

INTRODUCTION

Sigma Delta converters are able to achieve a high conversion resolution without the need for high-precision analog circuits due to the oversampling and noise shaping techniques. In particular, single-loop 1-bit sigma-delta (Σ∆) ADCs have been popular for their simplicity and insensitivity to imperfections of analog circuits [1]. However single loop structures results in loss of performance for high order modulation because of stability concern. A popular way to realize a stable high-order modulator is to use a multistage or MASH structure. However, MASH modulators are prone to noise leakage due to mismatch among analog filters and the digital noise-cancellation filters. Although high-order modulator can be stabilized using multibit quantizer, it enforces stringent linearity requirements on the feedback digital-to-analog converter (DAC) [1]. The accuracy of the DAC needs to be as good as the accuracy of the overall modulator. In the design of high-order stable modulators performance degradation occurs due to the saturation or overload of the integrators. Also as supply voltage reduces as a result of technology scaling, the available signal swings of analog circuits decrease, thereby limiting the dynamic range of the modulator and even jeopardizing stability. These problems can be avoided by using an overload detection mechanism. An overload estimating unit (OLE) is used to detect the saturation or overload of each integrator in the modulator. If the integrator is expected to be overloaded or saturated, the OLE

Bahar Jalali Farahani Department of Electrical Engineering Arizona State University Tempe, AZ [email protected]

subtracts a pre-defined value from the integrator input. Meanwhile, the same amount, which can be seen as the overflow of the analog integrator, is added to and processed by the digital integrators. In this manner, the maximum stable input of the modulator can be increased which leads to improvement in the dynamic range of the modulator [2]. This paper describes a second-order modulator designed for WLAN applications that employs this technique. To demonstrate benefits of the hybrid sigma delta data converter, a comparison with a general 2nd order sigma delta converter will be shown. Simulation results show significant improvements in SNR, OL as well as DR. The paper is organized as follows. Section II briefly describes the modulator architecture. The improvements of the modulator structure are brought in section III. Section IV shows an example of system level implementation of this modulator in MATLAB Simulink together with its advantages over the conventional design. Section V addresses circuit implementation done in TSMC 0.35um technology. The paper is concluded in section VI. II. MODULATOR ARCHITECTURE The modulator structure is shown in Fig. 1. The mixed-mode integrator is a combination of an analog integrator and a digital integrator. The modulator can be viewed as a conventional single-loop modulator with analog integrators replaced by Analog Signals

Digital Signals

Fig.1. Block diagram of the hybrid integrator scheme mixed-mode integrators. In contrast to the conventional design, no global feedback exists in the analog path.

As a result, stability of the analog path is readily verified provided that the local feedbacks around the analog integrators work properly. The digital path will remain stable as long as the amplitude of signals in this path does not exceed the length of the digital word. The overload estimator (OLE) as shown in Fig. 2 monitors both the input and the output of the integrator in order to decide whether the integrator would be saturated or not. If the integrator output is expected to exceed +vref then +vref is subtracted from the input of the analog integrator while +vref is added to the digital integrator. If the addition exceeds –vref then +vref is added to the analog integrator and subtracted from the digital one. This mechanism ensures that

Fig.2. Block diagram of the OLE the analog integrator output remains within [-vref, +vref] all the time. Sigma Delta modulators with hybrid integrators are suffering from the leakage noise due to the mistamtch between the analog and digital paths similar to a MASH structure.

Vout

Vout

Vref

Vref

-Vref Vref

-Vref

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Vref

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-Vref

(a)

(b)

Fig. 3. Transfer function of 1 bit quantizer. (a) conventional (b) modified.

IV. SYSTEM LEVEL IMPLEMENTATION System level implementation in MATLAB Simulink was done for the hybrid integrator along with the architectural improvements discussed above. Output power spectral density of the modulator is given in Fig. 4. Transient outputs of the analog and digital integrators are shown in Fig. 5. Here the analog integrator outputs are within +/- vref levels but the digital integrator outputs have let to exceed +/- vref. SNR vs input amplitude plot is given in Fig. 6. The hybrid

III. ARCHITECTURAL IMPROVEMENT We proposed two important modifications with respect to the prior work. These modifications are explained here: A. OLE +/- vref level change It is shown that significant improvement in SNR, OL and DR can be made by adding/subtracting +2vref instead of +vref when an overload situation is detected. The reason why this helps to improve the dynamic range can be understood intuitively: adding/subtracting +2vref instead of +vref makes the input of the integrator move to the other extreme (i.e. -vref if the integrator where exceeding +vref initially). Since the SNR is maximized for larger inputs, this helps to keep the modulator around the peak SNR region. B. Change in one bit quantizer levels In this architecture, the output of the quantizer is fed only to the digital path and the input full scale is related only with the signal swing of the first mixed-mode integrator. As a result, the quantizer output level can be reduced by half as illustrated in Fig. 3. Since the input to the quantizer is the output of a mixedmode integrator, the input is strictly limited within [-vref, +vref] and the maximum error due to quantization is vref/2, which is half of the maximum error of a conventional quantizer. Improvement of SNR, OL and DR can be observed by changing the quantizer levels.

Fig. 4. Output spectra of the second order hybrid modulator output 1st analog integrator

output 2nd analog integrator

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Fig. 5. Output of analog and digital integrators

integrator was compared with a conventional modulator and with the architectural improvements considered. We can see that the SNR improves about 19-dB compared to the conventional scheme. Also OL and DR increase 8.6-dB and 8dB respectively. The achieved results are given in tabular form in Table 1. TABLE I

Fig. 12. Integrator output integrator Fig. 7. Fully differential switch capacitor The integrator is driven by non-overlapping two-phase clocks and their delayed versions. The timing of clocks is illustrated in Fig. 9. While Φ1 is on, signals are sampled on capacitors and during the next phase, the output of the

Fig. 6. SNR vs input amplitude Comparison of different modulator schemes SNR Peak

Conventional Modulator 55.26 dB

Conventional Hybrid 61.94 dB

Architectural Improved Hybrid Scheme 74.84 dB

OL

-9.8 dB

-3.2 dB

-1.2 dB

DR

54.2 dB

59.1 dB

62.1 dB

V. CIRCUIT LEVEL IMPLEMENTATION The modulator is designed to be used in WLAN systems. Although the dynamic range requirements for this application depend on the receiver architecture, typically more than 65 dB over a 10-MHz signal bandwidth are required. The proposed modulator can meet these requirements with low OSR, specifically 16. The corresponding clock frequency is 320 MHz. A. Analog Integrator A fully differential switched-capacitor implementation was used. Fig.7 shows the schematic of the integrator. The closed loop gain of the integrator is designed to be unity and the sampling capacitor and the feedback capacitor are of the same size of 300fF each. The operational amplifier is shown in Fig.8, and is a fully differential telescopic cascode amplifier with folded cascode gain boosting and a switched-capacitor common-mode feedback circuit. The Opamp is designed to have unity gain bandwidth of 1GHz with 0.5pF load and a dc gain of 120 dB. It has a phase margin of 49 degrees and consumes 15mW of power. In order to reduce the signal-dependent resistance, the integrator input is connected to the sampling capacitors through bootstrapped switches [3]. Other switches are transmission gates.

Fig. 8. Fully differential telescopic cascode amplifier with a switchedcapacitor common-mode feedback circuit (gain boost not shown)

integrator is estimated by the OLE. During the nonoverlapping interval between Φ1and Φ2, OLE determines the local feedback signal using a comparator shown in Fig. 10 that consists of a pre-amplifier and a latch whose conversion time is less than 1ns. When Φ2 is on, the next actual output of the integrator is evaluated and OLE is tracking the integrator output to be used in the future sample.

Fig. 9. Phase timing diagram

shown in Fig. 13. Similarly 1.5V and 2.5V is given when it exceeds the negative threshold.

B. Overload Estimator (OLE)

VI. CONCLUSION

Fig. 10. Comparator with pre-amplifier The OLE roughly calculates the next integrator output before the real value is evaluated in order to check whether the integrator will be saturated or not. A simple passive network of switches and capacitors as shown in Fig. 11 is used for the OLE. The OL_H and OL_L signals are fed at Φ2 and vrefp, vrefn or gnd is sampled to the integrator input for proper

The sigma-delta modulator using hybrid integrators has improved dynamic range. The overflow of analog integrators is processed by digital ones results in an increase in dynamic range as well as SNR and OL. We proposed two modifications to the previous sigma-delta modulator with hybrid integrators that can further enhance the performance of these modulators. A second-order modulator was designed based on this technique that satisfies the requirements of WLAN systems. The proposed technique is especially attractive for modern CMOS technologies, where the signal swing is limited and hence modulators are getting saturated with lower OL. The overhead digital circuitry consumes less power and area compared to the analog core and is also scaled down with technology.

Fig. 13. OLE timing diagram Fig. 11. Overload Estimator (OLE) estimation based on the following (1) and (2) equations [4]. OL_H = High if, (Vip-Vin)+(Vop-Von) > (Vrefp-Vrefn) OL_L = High if, (Vip-Vin)+(Vop-Von) < -(Vrefp-Vrefn)

REFERENCES [1]

(1) (2)

[2] [3]

C. Digital Integrator [4]

The bit widths of the digital integrator should be carefully determined so that the round-off errors do not deteriorate the performance of the modulator. The register of the digital integrator needs 14 bits with some margins for proper operation of the modulator. Fig. 12 shows the differential outputs of the hybrid integrator. OLE function is illustrated using the timing diagram. When the addition of the difference in the input and output exceeds a positive threshold, OLE block gives 2.5V and 1.5V to the positive and negative terminals of the opamp respectively as

S. R. Norsworthy, R. Schreier, and G. C. Temes, Delta-Sigma Data Converters: Theory, Design, and Simulation. NewYork: IEEE Press, 1997. B. Kim and T. Kim, “Sigma-Delta Analog-to-Digital Converter using Mixed-Mode Integrator,” U.S. Patent 6,424,279, Jun. 23, 2000. A. Abo and P. R. Gray, “A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 599–606, May 1999. J.Shim, I. Park and B. Kim, "A third-order Σ∆ modulator in 0.18 um CMOS with calibrated mixed-mode integrators," IEEE J. Solid-State Circuits vol. 40, no.4, pp. 918–925, April 2005.