Code No: 35116
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Set No - 1
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1. Explain how Op-amp can be used in the following applications.
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III B.Tech I Semester Supplimentary Examinations,Nov/Dec 2009 LINEAR AND DIGITAL IC APPLICATIONS Common to Bio-Medical Engineering, Electronics And Computer Engineering, Electronics And Telematics, Electronics And Control Engineering Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ?????
(a) Rectifiers. (b) Logarithmic Amplifiers. (c) Peak detector.
[6+6+4]
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2. (a) Design a first order high pass filter at a cutoff frequency of 400Hz and a pass band gain of 2. (b) What is the Butterworth response? (c) Define a Notch filter.
[8+5+3]
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3. (a) Design a conversion circuit to convert a SR flip-flop to T flip-flop? (b) Write short notes on shift shift register.
[8+8]
4. (a) Give the logic diagram of 74×139? Explain with the help of truth table? Using this device design a 3 to 8 decoder and provide the truth table? (b) Design the logic circuit for odd parity checker? 5. (a) Explain how the input off set voltage compensated for Op-amp.
[10+6] [8+6+2]
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(b) How fast can the output of an Op-amp change by 10V, if its slew rate is 1V/µs? (c) Define thermal drift.
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6. (a) Design a TTL three-state NAND gate and explain the operation with the help of function table? (b) What are the parameters that are necessary to define the electrical characteristics of CMOS circuits? Mention the typical values of a CMOS NAND gate? [8+8]
7. (a) Write short notes on : i. Balanced Modulator. ii. Voltage Controlled Oscillator. iii. Digital Phase Detector. (b) Give any one applications of PLL and explain it in detail. 1
[4+4+4+4]
Code No: 35116
R05
Set No - 1
8. (a) Explain the operation of a successive Approximation type Analog to Digital converter. (b) Calculate the No.of bits required to represent a full scale voltage of 10 volts with a resolution of 5m Volts approximately. [10+6]
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Code No: 35116
R05
Set No - 2
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1. (a) Briefly describe three uses of an analog multiplier.
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III B.Tech I Semester Supplimentary Examinations,Nov/Dec 2009 LINEAR AND DIGITAL IC APPLICATIONS Common to Bio-Medical Engineering, Electronics And Computer Engineering, Electronics And Telematics, Electronics And Control Engineering Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ?????
(b) What do you mean by sampling? Explain the basic circuit for sample and hold circuit. [8+8]
2. (a) Explain the operation of a delay equalizer circuit with neat sketches. Derive an expression relating input and output voltages of the equalizer.
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(b) For the all pass filter, determine the phase shift between input and output at f=2 KHz. (c) Give the condition for oscillations?
[6+6+4]
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3. Explain the functional block diagram of PLL emphasizing the importance of capture range and Lock range. [16] 4. (a) Explain 4 bit serial in parallel out register. (b) Draw the circuit of edge trigged SR flip flop made up of by basic gates & explain the operation. Sketch the wave form. [8+8] 5. (a) Give the design procedure of a compensating network for an Op-amp which uses ± 10V supply voltages. Assume necessary data.
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(b) In the circuit of figure 1??, R1 =100 Ω, RF = 4.7K Ω, CMRR=90 db. If the amplitude of the induced 60-Hz noise at the output is 5mV (rms). Calculate the amplitude of the common-mode input voltage Vcm . [8+8]
Figure 1?? 6. (a) Give the logic diagram of 74×139 and explain its truth table?
3
Code No: 35116
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Set No - 2
(b) What is an encoder? Write short notes on decimal to binary encoder? [8+8] 7. (a) What is the necessity of separate interfacing circuit to connect CMOS gate to TTL gate? Draw the interface circuit and explain the operation? (b) Design a 4-input CMOS AND-OR-INVERT gate? Draw the logic diagram and function table? [8+8]
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8. (a) Explain the operation of a dual slope type Analog to Digital converter.
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(b) A dual slope Analog to Digital converter uses a 16-bit counter and operates at 4 MHz clock rate. The maximum input voltage is +8volts. Find the value of integrator resistor ‘R’ if the maximum output voltage of the integrator is -6V after 2n counts for an integrator capacitor of 0.1µF. [8+8]
4
Code No: 35116
R05
Set No - 3
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III B.Tech I Semester Supplimentary Examinations,Nov/Dec 2009 LINEAR AND DIGITAL IC APPLICATIONS Common to Bio-Medical Engineering, Electronics And Computer Engineering, Electronics And Telematics, Electronics And Control Engineering Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ?????
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1. (a) In which type of Analog to Digital converter, a Digital to Analog converter is used? Explain its operation in detail.
(b) List important specifications of Analog to Digital and Digital to Analog converters indicating their typical values. [8+8] 2. (a) Explain the significance of each of comparator and also operation of 555 timer. [8+8]
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(b) Explain the application of 555 timer as Linear ramp generator.
3. (a) What are the advantages of active filters? Explain wideband band pass filter together with it?s amplitude response. (b) What is phase shifter? With respect to schematic explain the operation.[8+8]
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4. (a) Draw the circuit of a Totem-pole TTL NAND gate ? What is the purpose of using a diode at the output stage? Explain its operation and verify the truth table. (b) When do we use open-collector TTL gate? (c) Which is the fastest logic gate and why?
[8+4+4]
5. (a) With the help of logic diagram explain 74×157 multiplexer? [8+8]
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(b) Design a serial binary adder?
6. (a) Explain the application of three terminal adjustable voltage regulator. (b) With the help of block diagram explain LF398 sample and hold IC along with wave forms. [8+8]
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7. (a) Why is emitter resistor RE replaced by a constant current bias circuit in differential amplifier stage of an Op-amp? (b) Explain why open loop configurations are not used in linear applications. (c) For an Op-amp, PSRR=70Db (min), CMRR = 105 , differential mode gain Ad = 105 . The output voltage changes by 20V in 4 microseconds. Calculate i. Numerical value of PSRR. ii. Common mode gain. iii. Slew rate of the Op-amp.
[6+4+6]
5
Code No: 35116
R05
Set No - 3
8. (a) Design a 4-bit binary synchronous counter using 74×74? (b) Draw the circuit and explain the crystal controlled clock generators.
[8+8]
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Code No: 35116
R05
Set No - 4
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1. (a) What are the desirable features of CMOS gates?
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III B.Tech I Semester Supplimentary Examinations,Nov/Dec 2009 LINEAR AND DIGITAL IC APPLICATIONS Common to Bio-Medical Engineering, Electronics And Computer Engineering, Electronics And Telematics, Electronics And Control Engineering Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ?????
(b) Sketch the circuit of CMOS NAND gate and verify that it satisfies the Boolean NAND equation. i. ii. iii. iv. v.
Fan-in Fan-out Standard load Current sink Current source.
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(c) Define the following terms:
[5+6+5]
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2. (a) Write short notes on synchronous up/down counter.
(b) Draw the circuit of gated SR latch and explain its operation using truth tables. [8+8] 3. (a) Design a 3 bit BCD adder circuit and explain its working. (b) What is multiplexer? Draw the logic diagram of 8 to 1 line multiplexer?[8+8]
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4. (a) Explain how the deficiencies of weighted resistor type DAC can be overcome through an R-2R ladder type network. Explain the conversion procedure in R-2R ladder type DAC. (b) The logic levels used in an 8-bit R-2R ladder type DAC are logic ‘1’=+5 volts and logic ‘0’= 0 volts. Find the output voltage for an input of 10110110.[10+6]
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5. (a) Describe how frequency division and multiplication can be achieved using a Phase Locked Loop. (b) Draw the circuit of a PLL AM detector and explain its operation.
[12+4]
6. (a) Explain the principle of operation of IC723 general purpose regulator with neat block diagram. (b) Write short notes on Schmitt trigger circuit using Op-amp and derive the expression for hysteresis voltage. [10+6] 7. (a) Explain the design procedure (with suitable circuit diagram of a fourth order Butterworth low-pass filter). 7
Code No: 35116
Set No - 4
R05
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(b) A certain narrow band-pass filter has been designed to meet the following specifications: fC =2 kHz. Q=20, and AF =10. What modifications are necessary in the filter circuit to change the center frequency ‘fc’ to 1 kHz, keeping the gain and band-width constant given (figure 1??)? [10+6]
Figure 1 ??
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8. (a) Define common mode rejection ratio (CMRR)? Explain why for an CM RR → ∞ emitter coupled differential amplifier where RE → ∞. (b) Why is cascade configuration used in an Op-amp?
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(c) Explain with the figures how two supply voltages V + and V − are obtained from a single supply. [8+4+4]
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