Code No: 33057

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II B.Tech I Semester Supplimentary Examinations,Nov/Dec 2009 SWITCHING THEORY AND LOGIC DESIGN Common to BME, ICE, E.COMP.E, E.CONT.E, EIE, EEE Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ?????

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1. (a) Draw the ASM chart for the following state transistion, start from the initial state T1 , then if xy=00 go to T2 , if xy=01 go to T3 , if xy=10 go to T1 , other wise go to T3 . (b) Show the exit paths in an ASM block for all binary combinations of control variables x, y and z, starting from an initial state. [8+8]

(a) Obtain State - Diagram. (b) Also obtain state - Table.

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2. A clocked sequential circuit is provided with a single input x and single output Z. Whenever the input produce a string of pulses 1 1 1 or 0 0 0 and at the end of the sequence it produce an output Z = 1 and overlapping is also allowed.

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(c) Find equivalence classes using partition method & design the circuit using D - flip-flops. [4+4+8] 3. (a) Simplify the following Boolean expressions to minimum no. of literals. i. ii. iii. iv.

ABC + A’B + ABC’ (BC’ + A’D)(AB’ + CD’) x’yz + xz xy + x (wz + wz’)

(b) Obtain the Dual of the following Boolean expressions.

[8]

AB + A(B + C) + B’(B + D) A + B + A‘B’C A’B + A’BC’ + A’BCD + A’BC’D’E ABEF + ABE’F’ + A’B’EF

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i. ii. iii. iv.

[8]

4. (a) Design an SOP logic circuit, which will output a 1(logic High) whenever the input binary equivalent of decimal 0,1,5,7,8,10,13,15,16,17,23,24and31. (b) Draw the Karnaugh map to represent the following Boolean function. ¯D ¯ + A). F= (B [12+4]

5. A 12-bit Hamming code word containing 8-bits of data and 4 parity bits is read from memory. What was the original 8-bit data word that was written in to memory if 12-bit words read out is as follows? [4 × 4 = 16] (a) 001111101010 1

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(b) 101110010110 (c) 101110110100 (d) 110011010111 6. (a) List the PLA programming table for the BCD to excess-3 code converter.

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(b) A ROM chip of 4,096 x 8 bits has two clip select inputs and operates from a 5-volt power supply. How many pins are needed for the integrated circuit package? Draw the block diagram of this ROM. [8+8]

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7. What are the advantages of a carry look ahead adder? Draw logic diagram of carry lookahead adder of a bit and explain the working of it. [4+!2] 8. (a) Find a modulo-6 gray code using k-Map & design the corresponding counter. (b) Compare synchronous & Asynchronous.

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2

[10+6]

Code No: 33057

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II B.Tech I Semester Supplimentary Examinations,Nov/Dec 2009 SWITCHING THEORY AND LOGIC DESIGN Common to BME, ICE, E.COMP.E, E.CONT.E, EIE, EEE Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ?????

i. ii. iii. iv.

AB’ (C + BD) + A’B’ A’B’C + (A + B + C’)’ + A’B’C’D ABCD + AB(CD)’ + (AB)’CD (A + A’)(AB + ABC’)

[8]

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1. (a) Reduce the following Boolean expressions.

i. ii. iii. iv.

ABC + A’B + ABC’ (BC’+ A’D)(AB’ + CD’) x’yz + xz xy + x (wz + wz’)

[8]

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(b) Obtain the complement of the following Boolean expressions.

2. (a) What is a Hazard in a Digital system?

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(b) What are the various types of Hazards that may be encountered in a combinational logic? Explain in detail how Hazards are eliminated? [4+12] 3. (a) Differentiate prime implicant and essential prime implicant?

[4]

(b) Minimize the following P function using tabular minimization. F (A, B, C, D) = m(0, 1, 2, 8, 9, 15, 17, 21, 24, 25, 27, 31)

[12]

4. (a) Using the method of flip flop conversion carry out the following conversions.

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i. S-R to T ii. J-K to D

[4x2=8]

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(b) Verify that the circuit and explain its function. With the timing waveforms. Shown in figure 4 [8]

3

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Figure 4

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Code No: 33057

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5. A Clocked sequential circuit with two inputs x and y and a single output Z using J - K flip flops is as shown in figure 5:

Figure 5

(a) Obtain input equations.

(b) List the state table (c) Draw the corresponding state diagram. (d) Derive state - equations.

[4+4+4+4] 4

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6. (a) Generate Hamming code for the given 11 bit message 11001001100 and rewrite the entire message with Hamming code. [8] (b) The binary numbers listed have a sign bit in the left most position and, if negative numbers are in 1’s complement form. Perform the arithmetic operations indicated and verify the answers. [4X2=8] 101011 001111 111001 101111

+ 111001 + 110010 - 011010 - 100110

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i. ii. iii. iv.

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7. (a) Derive the PLA programming table for the combinational circuit that squares a 3 bit number.

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(b) For the given 3-input, 4-output truth table of a combinations circuit,tabulate the PAL programming table for the circuit. [8+8] Inputs Output x y z A B C D 0 0 0 0 1 0 0 0 0 1 1 1 1 1 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 0 0 1 0 1 0 1 0 1 0 0 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1

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8. For the ASM chart given 8:

5

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Code No: 33057

Figure 8

(a) Draw the state diagram.

(b) Design the control unit using D flip-flops and a decoder.

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[8+8]

Code No: 33057

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II B.Tech I Semester Supplimentary Examinations,Nov/Dec 2009 SWITCHING THEORY AND LOGIC DESIGN Common to BME, ICE, E.COMP.E, E.CONT.E, EIE, EEE Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ????? 1. (a) Compare synchronous & Asynchronous circuits

[6+10]

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(b) Design a Mod-6 synchronous counter using J-K flip flops. 2. Convert the following to Decimal and then to Octal. (a) 25716 (b) 19916 (d) 110011002 (e) 34410 (f) 76610

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(c) 101100012

[3+3+3+3+2+2]

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3. (a) For the given Boolean function F = xy’z + x’y’z + w’xy + wx’y + wxy

[8]

i. Draw the logic diagram ii. Simplify the function to minimal literals using Boolean algebra. (b) Obtain the Dual of the following Boolean expressions. AB’C + AB’D + A’B’ A’B’C + ABC’ + A’B’C’D ABCD + ABC’D’ + A’B’CD AB + ABC’

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i. ii. iii. iv.

[8]

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4. A Clocked sequential circuit with two inputs x and y and a single output Z is defined by the following T - flip-flop input and output equation of Z. T1 = Q1 Q2 y + Q1 Q2 x + Q2 xy T2 = Q1 Q2 + Q1 xy + Q1 Q2 x Z = (Q1 + Q2 )x + y (a) Draw the schematic logic circuit diagram.

(b) Derive state- table and state diagram. (c) Derive state equations.

[4+8+4]

5. (a) Simplify Q the following function using K-map. F= M (1, 2, 7, 9, 11, 12, 13, 14, 15).d(0, 3, 4, 5, 6)

7

[8]

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(b) For the truth table given below ,Write the expressions in minimal POS and SOP form using K-map. [8]

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Inputs Output A B C (Y) 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1 1 1 1 0 0 1 1 1 1

6. Implement the BCD to Seven segment Display Decoder, Showing the truth table, K-map simplification and Realization using Logic Gates. [16]

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7. For the ASM chart given 7:

Figure 7

(a) Draw the state diagram

(b) Design the control unit using multiplexers.

[8+8]

8. (a) Specify the size of a ROM (number of words and numbers bits per word) that will accommodate the truth table of a BCD to seven segment decoder with an enable input. 8

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(b) Write a brief note on programmable logic devices.

[8+8]

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Code No: 33057

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II B.Tech I Semester Supplimentary Examinations,Nov/Dec 2009 SWITCHING THEORY AND LOGIC DESIGN Common to BME, ICE, E.COMP.E, E.CONT.E, EIE, EEE Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ????? 1. (a) Explain ,the determination of all possible minimal expressions from a reduced prime implicant chart. [8]

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(b) Make a K-map of the following expression and obtain the minimal SOPand ¯ + (AB) + (C) + (AD) + (ABC) ¯ + (ABC). POS forms. (AC) [8] 2. Write a brief note on: (a) Architecture of PLDs

[8+8]

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(b) Capabitation and the limitations of threshold gates.

3. (a) Draw the logic diagram using only two input NAND gates to implement the following expression. [8] (AB + A’B’)(CD’ ? + C’D)

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(b) Obtain the complement of the following Boolean expressions. i. B’C’D + (B + C + D)’ + B’C’D’E ii. AB + (AC)’ + (AB + C)

[4]

(c) Obtain the dual of the following Boolean expressions. i. A’B’C’ + A’BC’ + AB’C’ + ABC’ ii. AB + (AC)’ + AB’C

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4. (a) For the state diagram 4a shown design a draw mod-5 counter.

10

[4] [10]

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Code No: 33057

Figure 4a

(b) Explain the following counters

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i. Ring counters ii. Twisted ring counter.

[3×2=6]

5. (a) Express the Decimal Digits 0 - 9 in BCD, 2421, 84-2-1 and Excess-3. (b) Convert the Hexadecimal number 1010 to Decimal and then to Binary. [12+4] 6. (a) Design a POS circuit that will generate an even parity bit for a 4-bit input. (b) Implement 4:1multiplexer using 2:4 decoder and some logic gates.

[8+8]

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7. (a) For the given ASM chart, obtain equivalent state-diagram 7b.

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(b) Design the circuit using multiplexers.

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[8+8]

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Code No: 33057

Figure 7b

8. A clocked sequential circuit is defined by the following state - table:

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(a) Find equivalence classes using partition method.

(b) Give proper assignment. (c) And design the circuit using D -Flip-Flops.

12

[4+4+8]

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Present state Next state q v+1 Out put Z P.S q v x=0 x=1 x=0 x=1 A A E 1 0 B A E 0 0 C B F 0 0 D B F 0 0 E C G 0 1 F C G 0 1 G D H 0 1 H D H 0 1

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Code No: 33057